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Improve read_verilog debug output capabilities 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-03-21 20:52:29 +01:00
parent 8c0740bcf7
commit 9b0e7af6d7
3 changed files with 42 additions and 15 deletions
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26
frontends/ast/ast.cc
View File

@ -45,7 +45,7 @@ namespace AST {
// instantiate global variables (private API) // instantiate global variables (private API)
namespace AST_INTERNAL { namespace AST_INTERNAL {
bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit; bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
AstNode *current_ast, *current_ast_mod; AstNode *current_ast, *current_ast_mod;
std::map<std::string, AstNode*> current_scope; std::map<std::string, AstNode*> current_scope;
@ -562,7 +562,8 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
case AST_CONCAT: case AST_CONCAT:
fprintf(f, "{"); fprintf(f, "{");
for (auto child : children) { for (int i = GetSize(children)-1; i >= 0; i--) {
auto child = children[i];
if (!first) if (!first)
fprintf(f, ", "); fprintf(f, ", ");
child->dumpVlog(f, ""); child->dumpVlog(f, "");
@ -926,23 +927,28 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
ast_before_simplify = ast->clone(); ast_before_simplify = ast->clone();
if (flag_dump_ast1) { if (flag_dump_ast1) {
log("Dumping Verilog AST before simplification:\n"); log("Dumping AST before simplification:\n");
ast->dumpAst(NULL, " "); ast->dumpAst(NULL, " ");
log("--- END OF AST DUMP ---\n"); log("--- END OF AST DUMP ---\n");
} }
if (flag_dump_vlog1) {
log("Dumping Verilog AST before simplification:\n");
ast->dumpVlog(NULL, " ");
log("--- END OF AST DUMP ---\n");
}
if (!defer) if (!defer)
{ {
while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { } while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
if (flag_dump_ast2) { if (flag_dump_ast2) {
log("Dumping Verilog AST after simplification:\n"); log("Dumping AST after simplification:\n");
ast->dumpAst(NULL, " "); ast->dumpAst(NULL, " ");
log("--- END OF AST DUMP ---\n"); log("--- END OF AST DUMP ---\n");
} }
if (flag_dump_vlog) { if (flag_dump_vlog2) {
log("Dumping Verilog AST (as requested by dump_vlog option):\n"); log("Dumping Verilog AST after simplification:\n");
ast->dumpVlog(NULL, " "); ast->dumpVlog(NULL, " ");
log("--- END OF AST DUMP ---\n"); log("--- END OF AST DUMP ---\n");
} }
@ -1016,14 +1022,15 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
} }
// create AstModule instances for all modules in the AST tree and add them to 'design' // create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
{ {
current_ast = ast; current_ast = ast;
flag_dump_ast1 = dump_ast1; flag_dump_ast1 = dump_ast1;
flag_dump_ast2 = dump_ast2; flag_dump_ast2 = dump_ast2;
flag_no_dump_ptr = no_dump_ptr; flag_no_dump_ptr = no_dump_ptr;
flag_dump_vlog = dump_vlog; flag_dump_vlog1 = dump_vlog1;
flag_dump_vlog2 = dump_vlog2;
flag_dump_rtlil = dump_rtlil; flag_dump_rtlil = dump_rtlil;
flag_nolatches = nolatches; flag_nolatches = nolatches;
flag_nomeminit = nomeminit; flag_nomeminit = nomeminit;
@ -1357,7 +1364,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
current_ast = NULL; current_ast = NULL;
flag_dump_ast1 = false; flag_dump_ast1 = false;
flag_dump_ast2 = false; flag_dump_ast2 = false;
flag_dump_vlog = false; flag_dump_vlog1 = false;
flag_dump_vlog2 = false;
flag_nolatches = nolatches; flag_nolatches = nolatches;
flag_nomeminit = nomeminit; flag_nomeminit = nomeminit;
flag_nomem2reg = nomem2reg; flag_nomem2reg = nomem2reg;

2
frontends/ast/ast.h
View File

@ -282,7 +282,7 @@ namespace AST
}; };
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
// parametric modules are supported directly by the AST library // parametric modules are supported directly by the AST library

29
frontends/verilog/verilog_frontend.cc
View File

@ -81,6 +81,9 @@ struct VerilogFrontend : public Frontend {
log(" -assert-assumes\n"); log(" -assert-assumes\n");
log(" treat all assume() statements like assert() statements\n"); log(" treat all assume() statements like assert() statements\n");
log("\n"); log("\n");
log(" -debug\n");
log(" alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
log("\n");
log(" -dump_ast1\n"); log(" -dump_ast1\n");
log(" dump abstract syntax tree (before simplification)\n"); log(" dump abstract syntax tree (before simplification)\n");
log("\n"); log("\n");
@ -90,7 +93,10 @@ struct VerilogFrontend : public Frontend {
log(" -no_dump_ptr\n"); log(" -no_dump_ptr\n");
log(" do not include hex memory addresses in dump (easier to diff dumps)\n"); log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
log("\n"); log("\n");
log(" -dump_vlog\n"); log(" -dump_vlog1\n");
log(" dump ast as Verilog code (before simplification)\n");
log("\n");
log(" -dump_vlog2\n");
log(" dump ast as Verilog code (after simplification)\n"); log(" dump ast as Verilog code (after simplification)\n");
log("\n"); log("\n");
log(" -dump_rtlil\n"); log(" -dump_rtlil\n");
@ -197,7 +203,8 @@ struct VerilogFrontend : public Frontend {
bool flag_dump_ast1 = false; bool flag_dump_ast1 = false;
bool flag_dump_ast2 = false; bool flag_dump_ast2 = false;
bool flag_no_dump_ptr = false; bool flag_no_dump_ptr = false;
bool flag_dump_vlog = false; bool flag_dump_vlog1 = false;
bool flag_dump_vlog2 = false;
bool flag_dump_rtlil = false; bool flag_dump_rtlil = false;
bool flag_nolatches = false; bool flag_nolatches = false;
bool flag_nomeminit = false; bool flag_nomeminit = false;
@ -258,6 +265,14 @@ struct VerilogFrontend : public Frontend {
assert_assumes_mode = true; assert_assumes_mode = true;
continue; continue;
} }
if (arg == "-debug") {
flag_dump_ast1 = true;
flag_dump_ast2 = true;
flag_dump_vlog1 = true;
flag_dump_vlog2 = true;
frontend_verilog_yydebug = true;
continue;
}
if (arg == "-dump_ast1") { if (arg == "-dump_ast1") {
flag_dump_ast1 = true; flag_dump_ast1 = true;
continue; continue;
@ -270,8 +285,12 @@ struct VerilogFrontend : public Frontend {
flag_no_dump_ptr = true; flag_no_dump_ptr = true;
continue; continue;
} }
if (arg == "-dump_vlog") { if (arg == "-dump_vlog1") {
flag_dump_vlog = true; flag_dump_vlog1 = true;
continue;
}
if (arg == "-dump_vlog2") {
flag_dump_vlog2 = true;
continue; continue;
} }
if (arg == "-dump_rtlil") { if (arg == "-dump_rtlil") {
@ -410,7 +429,7 @@ struct VerilogFrontend : public Frontend {
if (flag_nodpi) if (flag_nodpi)
error_on_dpi_function(current_ast); error_on_dpi_function(current_ast);
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
if (!flag_nopp) if (!flag_nopp)
delete lexin; delete lexin;