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Some cleanups in "clean"

This commit is contained in:
Clifford Wolf 2015-02-24 22:31:30 +01:00
parent 81fa4e81a6
commit 9ae21263f0
3 changed files with 26 additions and 7 deletions
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8
kernel/rtlil.h
View File

@ -807,6 +807,14 @@ struct RTLIL::Design
bool selected_module(RTLIL::Module *mod) const;
bool selected_whole_module(RTLIL::Module *mod) const;
RTLIL::Selection &selection() {
return selection_stack.back();
}
const RTLIL::Selection &selection() const {
return selection_stack.back();
}
bool full_selection() const {
return selection_stack.back().full_selection;
}

4
passes/opt/opt.cc
View File

@ -145,6 +145,10 @@ struct OptPass : public Pass {
}
}
design->optimize();
design->sort();
design->check();
log_header(fast_mode ? "Finished fast OPT passes.\n" : "Finished OPT passes. (There is nothing left to do.)\n");
log_pop();
}

21
passes/opt/opt_clean.cc
View File

@ -296,8 +296,14 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
module->connect(y, a);
delcells.push_back(cell);
}
for (auto cell : delcells)
for (auto cell : delcells) {
if (verbose)
log(" removing buffer cell `%s': %s = %s\n", cell->name.c_str(),
log_signal(cell->getPort("\\Y")), log_signal(cell->getPort("\\A")));
module->remove(cell);
}
if (!delcells.empty())
module->design->scratchpad_set_bool("opt.did_something", true);
rmunused_module_cells(module, verbose);
rmunused_module_signals(module, purge_mode, verbose);
@ -353,6 +359,10 @@ struct OptCleanPass : public Pass {
rmunused_module(module, purge_mode, true);
}
design->optimize();
design->sort();
design->check();
ct.clear();
ct_reg.clear();
log_pop();
@ -404,13 +414,10 @@ struct CleanPass : public Pass {
count_rm_cells = 0;
count_rm_wires = 0;
for (auto mod : design->selected_whole_modules()) {
if (mod->has_processes())
for (auto module : design->selected_whole_modules()) {
if (module->has_processes())
continue;
do {
design->scratchpad_unset("opt.did_something");
rmunused_module(mod, purge_mode, false);
} while (design->scratchpad_get_bool("opt.did_something"));
rmunused_module(module, purge_mode, false);
}
if (count_rm_cells > 0 || count_rm_wires > 0)