mirror of https://github.com/YosysHQ/yosys.git
Refactor Verific SVA importer property parser
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
261cf706f4
commit
9ab2498c55
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@ -29,7 +29,7 @@
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// seq |-> not seq until seq.triggered
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//
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// Currently supported sequence operators:
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// expr ##[N:M] seq
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// seq ##[N:M] seq
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// seq or seq
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// expr throughout seq
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// seq [*N:M]
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@ -753,6 +753,31 @@ struct VerificSvaImporter
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// ----------------------------------------------------------
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// SVA Importer
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struct ParserErrorException {
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};
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[[noreturn]] void parser_error(std::string errmsg)
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{
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if (!importer->mode_keep)
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log_error("%s", errmsg.c_str());
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log_warning("%s", errmsg.c_str());
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throw ParserErrorException();
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}
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[[noreturn]] void parser_error(std::string errmsg, linefile_type loc)
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{
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if (!importer->mode_keep)
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log_error("%s at %s:%d.\n", errmsg.c_str(), LineFile::GetFileName(loc), LineFile::GetLineNo(loc));
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log_warning("%s at %s:%d.\n", errmsg.c_str(), LineFile::GetFileName(loc), LineFile::GetLineNo(loc));
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throw ParserErrorException();
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}
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[[noreturn]] void parser_error(Instance *inst)
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{
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parser_error(stringf("Verific SVA primitive %s (%s) is currently unsupported in this context",
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inst->View()->Owner()->Name(), inst->Name()), inst->Linefile());
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}
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int parse_sequence(SvaFsm *fsm, int start_node, Net *net)
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{
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Instance *inst = net_to_ast_driver(net);
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@ -860,41 +885,16 @@ struct VerificSvaImporter
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return node;
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}
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// Handle unsupported primitives
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if (!importer->mode_keep)
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log_error("Verific SVA primitive %s (%s) is currently unsupported in this context.\n", inst->View()->Owner()->Name(), inst->Name());
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log_warning("Verific SVA primitive %s (%s) is currently unsupported in this context.\n", inst->View()->Owner()->Name(), inst->Name());
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return start_node;
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parser_error(inst);
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}
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void import()
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SigBit parse_property(Net *net)
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{
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module = importer->module;
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netlist = root->Owner();
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if (verific_verbose)
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log(" importing SVA property at root cell %s (%s) at %s:%d.\n", root->Name(), root->View()->Owner()->Name(),
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LineFile::GetFileName(root->Linefile()), LineFile::GetLineNo(root->Linefile()));
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RTLIL::IdString root_name = module->uniquify(importer->mode_names || root->IsUserDeclared() ? RTLIL::escape_id(root->Name()) : NEW_ID);
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clocking = VerificClocking(importer, root->GetInput());
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if (clocking.body_net == nullptr)
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log_error("Failed to parse SVA clocking at %s (%s) at %s:%d.", root->Name(), root->View()->Owner()->Name(),
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LineFile::GetFileName(root->Linefile()), LineFile::GetLineNo(root->Linefile()));
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// parse SVA sequence into trigger signal
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SigBit prop_okay;
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Net *net = clocking.body_net;
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Instance *inst = net_to_ast_driver(net);
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if (inst == nullptr)
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{
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prop_okay = importer->net_map_at(net);
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return importer->net_map_at(net);
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}
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else
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if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||
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@ -934,12 +934,8 @@ struct VerificSvaImporter
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consequent_inst = net_to_ast_driver(consequent_net);
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if (until_inst != nullptr) {
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if (until_inst->Type() != PRIM_SVA_TRIGGERED) {
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if (!importer->mode_keep)
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log_error("Currently only boolean expressions or sequence.triggered is alowed in SVA_UNTIL condition.\n");
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log_warning("Currently only boolean expressions or sequence.triggered is alowed in SVA_UNTIL condition.\n");
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return;
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}
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if (until_inst->Type() != PRIM_SVA_TRIGGERED)
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parser_error("Currently only boolean expressions or sequence.triggered is allowed in SVA_UNTIL condition", until_inst->Linefile());
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until_net = until_inst->GetInput();
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}
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@ -976,6 +972,7 @@ struct VerificSvaImporter
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node = parse_sequence(&consequent_fsm, consequent_fsm.startNode, consequent_net);
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consequent_fsm.createLink(node, consequent_fsm.acceptNode);
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SigBit prop_okay;
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if (mode_cover) {
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prop_okay = consequent_not ? consequent_fsm.getReject() : consequent_fsm.getAccept();
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} else {
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@ -987,6 +984,8 @@ struct VerificSvaImporter
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log(" Consequent FSM:\n");
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consequent_fsm.dump();
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}
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return prop_okay;
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}
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else
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if (inst->Type() == PRIM_SVA_NOT || mode_cover)
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@ -995,43 +994,70 @@ struct VerificSvaImporter
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int node = parse_sequence(&fsm, fsm.startNode, mode_cover ? net : inst->GetInput());
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fsm.createLink(node, fsm.acceptNode);
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SigBit accept = fsm.getAccept();
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prop_okay = module->Not(NEW_ID, accept);
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SigBit prop_okay = module->Not(NEW_ID, accept);
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if (verific_verbose) {
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log(" Sequence FSM:\n");
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fsm.dump();
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}
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return prop_okay;
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}
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else
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{
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// Handle unsupported primitives
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if (!importer->mode_keep)
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log_error("Verific SVA primitive %s (%s) is currently unsupported in this context.\n", inst->View()->Owner()->Name(), inst->Name());
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log_warning("Verific SVA primitive %s (%s) is currently unsupported in this context.\n", inst->View()->Owner()->Name(), inst->Name());
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return;
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parser_error(inst);
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}
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}
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// add final FF stage
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void import()
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{
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try
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{
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module = importer->module;
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netlist = root->Owner();
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SigBit prop_okay_q = module->addWire(NEW_ID);
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clocking.addDff(NEW_ID, prop_okay, prop_okay_q, Const(mode_cover ? 0 : 1, 1));
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if (verific_verbose)
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log(" importing SVA property at root cell %s (%s) at %s:%d.\n", root->Name(), root->View()->Owner()->Name(),
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LineFile::GetFileName(root->Linefile()), LineFile::GetLineNo(root->Linefile()));
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// generate assert/assume/cover cell
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RTLIL::IdString root_name = module->uniquify(importer->mode_names || root->IsUserDeclared() ? RTLIL::escape_id(root->Name()) : NEW_ID);
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RTLIL::Cell *c = nullptr;
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clocking = VerificClocking(importer, root->GetInput());
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if (eventually) {
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log_error("No support for eventually in Verific SVA bindings yet.\n");
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// if (mode_assert) c = module->addLive(root_name, prop_okay_q, prop_start_q);
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// if (mode_assume) c = module->addFair(root_name, prop_okay_q, prop_start_q);
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} else {
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if (mode_assert) c = module->addAssert(root_name, prop_okay_q, State::S1);
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if (mode_assume) c = module->addAssume(root_name, prop_okay_q, State::S1);
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if (mode_cover) c = module->addCover(root_name, prop_okay_q, State::S1);
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if (clocking.body_net == nullptr)
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parser_error(stringf("Failed to parse SVA clocking at %s (%s) at %s:%d.", root->Name(), root->View()->Owner()->Name(),
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LineFile::GetFileName(root->Linefile()), LineFile::GetLineNo(root->Linefile())));
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// parse SVA sequence into trigger signal
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Net *net = clocking.body_net;
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SigBit prop_okay = parse_property(net);
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// add final FF stage
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SigBit prop_okay_q = module->addWire(NEW_ID);
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clocking.addDff(NEW_ID, prop_okay, prop_okay_q, Const(mode_cover ? 0 : 1, 1));
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// generate assert/assume/cover cell
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RTLIL::Cell *c = nullptr;
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if (eventually) {
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parser_error("No support for eventually in Verific SVA bindings yet.\n");
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// if (mode_assert) c = module->addLive(root_name, prop_okay_q, prop_start_q);
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// if (mode_assume) c = module->addFair(root_name, prop_okay_q, prop_start_q);
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} else {
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if (mode_assert) c = module->addAssert(root_name, prop_okay_q, State::S1);
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if (mode_assume) c = module->addAssume(root_name, prop_okay_q, State::S1);
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if (mode_cover) c = module->addCover(root_name, prop_okay_q, State::S1);
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}
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importer->import_attributes(c->attributes, root);
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}
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catch (ParserErrorException)
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{
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}
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importer->import_attributes(c->attributes, root);
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}
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};
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