mirror of https://github.com/YosysHQ/yosys.git
enable dff context initialization
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@ -71,21 +71,25 @@ module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
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endmodule
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endmodule
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module \$_DFF_P_ (input D, C, output Q);
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module \$_DFF_P_ (input D, C, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
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NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
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endmodule
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endmodule
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module \$_DFF_N_ (input D, C, output Q);
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module \$_DFF_N_ (input D, C, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
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NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
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endmodule
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endmodule
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module \$_DFFE_PP_ (input D, C, E, output Q);
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module \$_DFFE_PP_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
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NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
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endmodule
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endmodule
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module \$_DFFE_NP_ (input D, C, E, output Q);
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module \$_DFFE_NP_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
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NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
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endmodule
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endmodule
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@ -302,11 +302,11 @@ struct SynthNanoXplorePass : public ScriptPass
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if (check_label("map_ffs"))
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if (check_label("map_ffs"))
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{
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{
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std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
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std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
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if (help_mode) {
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if (help_mode) {
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dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]";
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dfflegalize_args += " [-cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]";
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} else if (!nodffe) {
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} else if (!nodffe) {
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dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r";
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dfflegalize_args += " -cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r";
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}
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}
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dfflegalize_args += " -cell $_DLATCH_?_ x";
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dfflegalize_args += " -cell $_DLATCH_?_ x";
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run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
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run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
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