mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs
sf2: replace sf2_iobs with {clkbuf,iopad}map
This commit is contained in:
clairexen
GitHub
commit
9a5d6e1789
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@ -1,6 +1,5 @@
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OBJS += techlibs/sf2/synth_sf2.o
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OBJS += techlibs/sf2/sf2_iobs.o
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$(eval $(call add_share_file,share/sf2,techlibs/sf2/arith_map.v))
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$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_map.v))
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@ -1,7 +1,6 @@
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// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf
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module ADD2 (
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input A, B,
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output Y
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);
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@ -76,6 +75,7 @@ endmodule
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module CLKINT (
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input A,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A;
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@ -83,6 +83,7 @@ endmodule
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module CLKINT_PRESERVE (
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input A,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A;
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@ -90,6 +91,7 @@ endmodule
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module GCLKINT (
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input A, EN,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A & EN;
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@ -97,6 +99,7 @@ endmodule
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module RCLKINT (
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input A,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A;
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@ -104,6 +107,7 @@ endmodule
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module RGCLKINT (
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input A, EN,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A & EN;
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@ -113,6 +117,7 @@ module SLE (
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output Q,
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input ADn,
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input ALn,
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(* clkbuf_sink *)
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input CLK,
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input D,
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input LAT,
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@ -155,9 +160,41 @@ endmodule
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// module SYSRESET
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// module SYSCTRL_RESET_STATUS
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// module LIVE_PROBE_FB
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// module GCLKBUF
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// module GCLKBUF_DIFF
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// module GCLKBIBUF
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(* blackbox *)
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module GCLKBUF (
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(* iopad_external_pin *)
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input PAD,
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input EN,
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(* clkbuf_driver *)
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output Y
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);
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endmodule
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(* blackbox *)
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module GCLKBUF_DIFF (
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(* iopad_external_pin *)
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input PADP,
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(* iopad_external_pin *)
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input PADN,
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input EN,
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(* clkbuf_driver *)
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output Y
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);
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endmodule
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(* blackbox *)
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module GCLKBIBUF (
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input D,
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input E,
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input EN,
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(* iopad_external_pin *)
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inout PAD,
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(* clkbuf_driver *)
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output Y
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);
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endmodule
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// module DFN1
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// module DFN1C0
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// module DFN1E1
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@ -288,38 +325,118 @@ module XOR8 (
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endmodule
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// module UJTAG
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// module BIBUF
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// module BIBUF_DIFF
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// module CLKBIBUF
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module BIBUF (
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input D,
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input E,
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(* iopad_external_pin *)
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inout PAD,
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output Y
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);
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assign PAD = E ? D : 1'bz;
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assign Y = PAD;
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endmodule
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(* blackbox *)
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module BIBUF_DIFF (
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input D,
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input E,
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(* iopad_external_pin *)
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inout PADP,
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(* iopad_external_pin *)
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inout PADN,
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output Y
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);
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endmodule
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module CLKBIBUF (
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input D,
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input E,
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(* iopad_external_pin *)
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inout PAD,
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(* clkbuf_driver *)
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output Y
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);
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assign PAD = E ? D : 1'bz;
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assign Y = PAD;
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endmodule
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module CLKBUF (
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(* iopad_external_pin *)
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input PAD,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = PAD;
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endmodule
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// module CLKBUF_DIFF
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(* blackbox *)
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module CLKBUF_DIFF (
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(* iopad_external_pin *)
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input PADP,
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(* iopad_external_pin *)
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input PADN,
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(* clkbuf_driver *)
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output Y
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);
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endmodule
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module INBUF (
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(* iopad_external_pin *)
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input PAD,
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output Y
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);
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assign Y = PAD;
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endmodule
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// module INBUF_DIFF
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(* blackbox *)
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module INBUF_DIFF (
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(* iopad_external_pin *)
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input PADP,
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(* iopad_external_pin *)
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input PADN,
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output Y
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);
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endmodule
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module OUTBUF (
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input D,
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(* iopad_external_pin *)
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output PAD
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);
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assign PAD = D;
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endmodule
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// module OUTBUF_DIFF
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// module TRIBUFF
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// module TRIBUFF_DIFF
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(* blackbox *)
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module OUTBUF_DIFF (
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input D,
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(* iopad_external_pin *)
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output PADP,
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(* iopad_external_pin *)
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output PADN
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);
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endmodule
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module TRIBUFF (
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input D,
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input E,
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(* iopad_external_pin *)
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output PAD
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);
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assign PAD = E ? D : 1'bz;
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endmodule
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(* blackbox *)
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module TRIBUFF_DIFF (
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input D,
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input E,
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(* iopad_external_pin *)
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output PADP,
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(* iopad_external_pin *)
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output PADN
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);
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endmodule
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// module DDR_IN
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// module DDR_OUT
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// module RAM1K18
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@ -1,197 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void handle_iobufs(Module *module, bool clkbuf_mode)
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{
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SigMap sigmap(module);
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pool<SigBit> clk_bits;
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pool<SigBit> handled_io_bits;
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dict<SigBit, SigBit> rewrite_bits;
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vector<pair<Cell*, SigBit>> pad_bits;
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for (auto cell : module->cells())
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{
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if (clkbuf_mode && cell->type == ID(SLE)) {
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for (auto bit : sigmap(cell->getPort(ID::CLK)))
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clk_bits.insert(bit);
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}
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if (cell->type.in(ID(INBUF), ID(OUTBUF), ID(TRIBUFF), ID(BIBUF), ID(CLKBUF), ID(CLKBIBUF),
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ID(INBUF_DIFF), ID(OUTBUF_DIFF), ID(BIBUFF_DIFF), ID(TRIBUFF_DIFF), ID(CLKBUF_DIFF),
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ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF))) {
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for (auto bit : sigmap(cell->getPort(ID(PAD))))
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handled_io_bits.insert(bit);
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}
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}
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for (auto wire : vector<Wire*>(module->wires()))
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{
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if (!wire->port_input && !wire->port_output)
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continue;
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for (int index = 0; index < GetSize(wire); index++)
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{
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SigBit bit(wire, index);
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SigBit canonical_bit = sigmap(bit);
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if (handled_io_bits.count(canonical_bit))
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continue;
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if (wire->port_input && wire->port_output)
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log_error("Failed to add buffer for inout port bit %s.\n", log_signal(bit));
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IdString buf_type, buf_port;
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if (wire->port_output) {
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buf_type = ID(OUTBUF);
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buf_port = ID::D;
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} else if (clkbuf_mode && clk_bits.count(canonical_bit)) {
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buf_type = ID(CLKBUF);
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buf_port = ID::Y;
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} else {
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buf_type = ID(INBUF);
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buf_port = ID::Y;
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}
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Cell *c = module->addCell(NEW_ID, buf_type);
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SigBit new_bit = module->addWire(NEW_ID);
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c->setPort(buf_port, new_bit);
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pad_bits.push_back(make_pair(c, bit));
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rewrite_bits[canonical_bit] = new_bit;
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log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
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}
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}
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auto rewrite_function = [&](SigSpec &s) {
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for (auto &bit : s) {
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SigBit canonical_bit = sigmap(bit);
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if (rewrite_bits.count(canonical_bit))
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bit = rewrite_bits.at(canonical_bit);
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}
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};
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module->rewrite_sigspecs(rewrite_function);
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for (auto &it : pad_bits)
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it.first->setPort(ID(PAD), it.second);
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}
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static void handle_clkint(Module *module)
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{
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SigMap sigmap(module);
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pool<SigBit> clk_bits;
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vector<SigBit> handled_clk_bits;
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for (auto cell : module->cells())
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{
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if (cell->type == ID(SLE)) {
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for (auto bit : sigmap(cell->getPort(ID::CLK)))
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clk_bits.insert(bit);
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}
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if (cell->type.in(ID(CLKBUF), ID(CLKBIBUF), ID(CLKBUF_DIFF), ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF),
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ID(CLKINT), ID(CLKINT_PRESERVE), ID(GCLKINT), ID(RCLKINT), ID(RGCLKINT))) {
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for (auto bit : sigmap(cell->getPort(ID::Y)))
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handled_clk_bits.push_back(bit);
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}
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}
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for (auto bit : handled_clk_bits)
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clk_bits.erase(bit);
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for (auto cell : vector<Cell*>(module->cells()))
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for (auto &conn : cell->connections())
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{
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if (!cell->output(conn.first))
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continue;
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SigSpec sig = conn.second;
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bool did_something = false;
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for (auto &bit : sig) {
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SigBit canonical_bit = sigmap(bit);
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if (clk_bits.count(canonical_bit)) {
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Cell *c = module->addCell(NEW_ID, ID(CLKINT));
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SigBit new_bit = module->addWire(NEW_ID);
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c->setPort(ID::A, new_bit);
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c->setPort(ID::Y, bit);
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log("Added %s cell %s for clock signal %s.\n", log_id(c->type), log_id(c), log_signal(bit));
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clk_bits.erase(canonical_bit);
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did_something = true;
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bit = new_bit;
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}
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}
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if (did_something)
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cell->setPort(conn.first, sig);
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}
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for (auto bit : clk_bits)
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log_error("Failed to insert CLKINT for clock signal %s.\n", log_signal(bit));
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}
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struct Sf2IobsPass : public Pass {
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Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" sf2_iobs [options] [selection]\n");
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log("\n");
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log("Add SF2 I/O buffers and global buffers to top module as needed.\n");
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log("\n");
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log(" -clkbuf\n");
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log(" Insert PAD->global_net clock buffers\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool clkbuf_mode = false;
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log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-clkbuf") {
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clkbuf_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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Module *module = design->top_module();
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if (module == nullptr)
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log_cmd_error("No top module found.\n");
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handle_iobufs(module, clkbuf_mode);
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handle_clkint(module);
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}
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} Sf2IobsPass;
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PRIVATE_NAMESPACE_END
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@ -210,10 +210,12 @@ struct SynthSf2Pass : public ScriptPass
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if (check_label("map_iobs"))
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{
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if (help_mode)
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run("sf2_iobs [-clkbuf]", "(unless -noiobs)");
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else if (iobs)
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run(clkbuf ? "sf2_iobs -clkbuf" : "sf2_iobs");
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if (help_mode || iobs) {
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if (help_mode || clkbuf) {
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run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD", "(if -clkbuf, unless -noiobs)");
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}
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run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs");
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}
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run("clean");
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}
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