From 4d4117c998db8f58a436ec9ea9c930bce85febef Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Fri, 22 Jun 2018 11:15:03 +0200 Subject: [PATCH 01/57] added ENABLE_PYTHON option in build environment --- Makefile | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 11803ec0a..e8fcf933b 100644 --- a/Makefile +++ b/Makefile @@ -14,9 +14,13 @@ ENABLE_READLINE := 1 ENABLE_EDITLINE := 0 ENABLE_VERIFIC := 0 ENABLE_COVER := 1 -ENABLE_LIBYOSYS := 0 +ENABLE_LIBYOSYS := 1 ENABLE_PROTOBUF := 0 +# python wrappers +ENABLE_PYTHON := 1 +PYTHON_VERSION := 3.5 + # other configuration flags ENABLE_GPROF := 0 ENABLE_DEBUG := 0 @@ -228,6 +232,11 @@ ifeq ($(ENABLE_LIBYOSYS),1) TARGETS += libyosys.so endif +ifeq ($(ENABLE_PYTHON),1) +LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system +CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -fPIC -D WITH_PYTHON +endif + ifeq ($(ENABLE_READLINE),1) CXXFLAGS += -DYOSYS_ENABLE_READLINE ifeq ($(OS), FreeBSD) From a27fa1833e6dadf02645a12febb78853b5786151 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 25 Jun 2018 17:08:29 +0200 Subject: [PATCH 02/57] added wrappers for Design, Modules, Cells and Wires --- Makefile | 1 + kernel/python_wrappers.cc | 244 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 245 insertions(+) create mode 100644 kernel/python_wrappers.cc diff --git a/Makefile b/Makefile index e8fcf933b..09cf18497 100644 --- a/Makefile +++ b/Makefile @@ -235,6 +235,7 @@ endif ifeq ($(ENABLE_PYTHON),1) LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -fPIC -D WITH_PYTHON +OBJS += kernel/python_wrappers.o endif ifeq ($(ENABLE_READLINE),1) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc new file mode 100644 index 000000000..d6c1a7796 --- /dev/null +++ b/kernel/python_wrappers.cc @@ -0,0 +1,244 @@ +#ifdef WITH_PYTHON + +#include "yosys.h" +#include + +void yosys_setup() +{ + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + + Yosys::yosys_setup(); + Yosys::yosys_banner(); +} + +void run(std::string command) +{ + Yosys::run_pass(command); +} + +void yosys_shutdown() +{ + Yosys::yosys_shutdown(); +} + +struct YosysCell +{ + unsigned int hashid; + + YosysCell(unsigned int hashid) + { + this->hashid = hashid; + } + + YosysCell(Yosys::RTLIL::Cell* ref) + { + this->hashid = ref->hashidx_; + } + + Yosys::RTLIL::Cell* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + for(auto &mod_it : active_design->modules_) + { + for(auto &cell_it : mod_it.second->cells_) + if(cell_it.second->hashidx_ == this->hashid) + return cell_it.second; + } + return NULL; + } +}; + +std::ostream &operator<<(std::ostream &ostr, const YosysCell &cell) +{ + ostr << "Cell with id " << cell.hashid; + return ostr; +} + +struct YosysWire +{ + unsigned int hashid; + + YosysWire(unsigned int hashid) + { + this->hashid = hashid; + } + + YosysWire(Yosys::RTLIL::Wire* ref) + { + this->hashid = ref->hashidx_; + } + + Yosys::RTLIL::Wire* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + for(auto &mod_it : active_design->modules_) + { + for(auto &wire_it : mod_it.second->wires_) + if(wire_it.second->hashidx_ == this->hashid) + return wire_it.second; + } + return NULL; + } +}; + +std::ostream &operator<<(std::ostream &ostr, const YosysWire &wire) +{ + ostr << "Wire with id " << wire.hashid; + return ostr; +} + + +struct YosysModule +{ + unsigned int hashid; + + YosysModule(unsigned int hashid) + { + this->hashid = hashid; + } + + YosysModule(Yosys::RTLIL::Module* ref) + { + this->hashid = ref->hashidx_; + } + + Yosys::RTLIL::Module* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + for(auto &mod_it : active_design->modules_) + { + if(mod_it.second->hashidx_ == this->hashid) + return mod_it.second; + } + return NULL; + } + + boost::python::list get_cells() + { + Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + boost::python::list result; + if(cpp_mod == NULL) + return result; + for(auto &cell_it : cpp_mod->cells_) + { + result.append(new YosysCell(cell_it.second)); + } + return result; + } + + boost::python::list get_wires() + { + Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + boost::python::list result; + if(cpp_mod == NULL) + return result; + for(auto &wire_it : cpp_mod->wires_) + { + result.append(new YosysWire(wire_it.second)); + } + return result; + } +}; + +std::ostream &operator<<(std::ostream &ostr, const YosysModule &module) +{ + ostr << "Module with id " << module.hashid; + return ostr; +} + +struct YosysDesign +{ + unsigned int hashid; + + YosysDesign(unsigned int hashid) + { + this->hashid = hashid; + } + + YosysDesign() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design != NULL) + { + printf("design is not null and has id %u\n", active_design->hashidx_); + this->hashid = active_design->hashidx_; + /* + for (auto &mod_it : active_design->modules_) + { + printf("found module in design!!!\n"); + //design->add(it.second->clone()); + + for (auto &wire_it : mod_it.second->wires_) + { + printf("found wire in module!!!\n"); + } + + for (auto &cell_it : mod_it.second->cells_) + { + printf("found cell in module!!!\n"); + } + }*/ + } + } + + boost::python::list get_modules() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + boost::python::list result; + if(active_design == NULL) + return result; + for(auto &mod_it : active_design->modules_) + { + result.append(new YosysModule(mod_it.second)); + } + return result; + } +}; + +std::ostream &operator<<(std::ostream &ostr, const YosysDesign &design) +{ + ostr << "Design with id " << design.hashid; + return ostr; +} + +BOOST_PYTHON_MODULE(libyosys) +{ + using namespace boost::python; + + class_("YosysDesign", init()) + .def(init<>()) + .def("get_modules", &YosysDesign::get_modules) + ; + + class_("YosysModule", init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_cells", &YosysModule::get_cells) + .def("get_wires", &YosysModule::get_wires) + ; + + class_("YosysCell", init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("YosysWire", init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + + def("yosys_setup",yosys_setup); + def("run",run); + def("yosys_shutdown",yosys_shutdown); +} + +#endif + From ccb4dcd013c1fbe005b8e8212efd22a4f0f63ff0 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 28 Jun 2018 14:44:28 +0200 Subject: [PATCH 03/57] changed references from hash-ids to IdString names --- kernel/python_wrappers.cc | 96 +++++++++++++-------------------------- 1 file changed, 32 insertions(+), 64 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index d6c1a7796..ae141c808 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -3,6 +3,11 @@ #include "yosys.h" #include +struct YosysDesign; +struct YosysModule; +struct YosysCell; +struct YosysWire; + void yosys_setup() { Yosys::log_streams.push_back(&std::cout); @@ -24,16 +29,13 @@ void yosys_shutdown() struct YosysCell { - unsigned int hashid; - - YosysCell(unsigned int hashid) - { - this->hashid = hashid; - } + Yosys::RTLIL::IdString name; + Yosys::RTLIL::IdString parent_name; YosysCell(Yosys::RTLIL::Cell* ref) { - this->hashid = ref->hashidx_; + this->name = ref->name; + this->parent_name = ref->module->name; } Yosys::RTLIL::Cell* get_cpp_obj() @@ -41,34 +43,27 @@ struct YosysCell Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); if(active_design == NULL) return NULL; - for(auto &mod_it : active_design->modules_) - { - for(auto &cell_it : mod_it.second->cells_) - if(cell_it.second->hashidx_ == this->hashid) - return cell_it.second; - } - return NULL; + if(active_design->modules_[this->parent_name] == NULL) + return NULL; + return active_design->modules_[this->parent_name]->cells_[this->name]; } }; std::ostream &operator<<(std::ostream &ostr, const YosysCell &cell) { - ostr << "Cell with id " << cell.hashid; + ostr << "Cell with name " << cell.name.c_str(); return ostr; } struct YosysWire { - unsigned int hashid; - - YosysWire(unsigned int hashid) - { - this->hashid = hashid; - } + Yosys::RTLIL::IdString name; + Yosys::RTLIL::IdString parent_name; YosysWire(Yosys::RTLIL::Wire* ref) { - this->hashid = ref->hashidx_; + this->name = ref->name; + this->parent_name = ref->module->name; } Yosys::RTLIL::Wire* get_cpp_obj() @@ -76,35 +71,27 @@ struct YosysWire Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); if(active_design == NULL) return NULL; - for(auto &mod_it : active_design->modules_) - { - for(auto &wire_it : mod_it.second->wires_) - if(wire_it.second->hashidx_ == this->hashid) - return wire_it.second; - } - return NULL; + if(active_design->modules_[this->parent_name] == NULL) + return NULL; + return active_design->modules_[this->parent_name]->wires_[this->name]; } }; std::ostream &operator<<(std::ostream &ostr, const YosysWire &wire) { - ostr << "Wire with id " << wire.hashid; + ostr << "Wire with name " << wire.name.c_str(); return ostr; } - struct YosysModule { - unsigned int hashid; - - YosysModule(unsigned int hashid) - { - this->hashid = hashid; - } + Yosys::RTLIL::IdString name; + unsigned int parent_hashid; YosysModule(Yosys::RTLIL::Module* ref) { - this->hashid = ref->hashidx_; + this->name = ref->name; + this->parent_hashid = ref->design->hashidx_; } Yosys::RTLIL::Module* get_cpp_obj() @@ -112,12 +99,9 @@ struct YosysModule Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); if(active_design == NULL) return NULL; - for(auto &mod_it : active_design->modules_) - { - if(mod_it.second->hashidx_ == this->hashid) - return mod_it.second; - } - return NULL; + if(active_design->hashidx_ != this->parent_hashid) + printf("Somehow the active design changed!\n"); + return active_design->modules_[this->name]; } boost::python::list get_cells() @@ -149,7 +133,7 @@ struct YosysModule std::ostream &operator<<(std::ostream &ostr, const YosysModule &module) { - ostr << "Module with id " << module.hashid; + ostr << "Module with name " << module.name.c_str(); return ostr; } @@ -169,22 +153,6 @@ struct YosysDesign { printf("design is not null and has id %u\n", active_design->hashidx_); this->hashid = active_design->hashidx_; - /* - for (auto &mod_it : active_design->modules_) - { - printf("found module in design!!!\n"); - //design->add(it.second->clone()); - - for (auto &wire_it : mod_it.second->wires_) - { - printf("found wire in module!!!\n"); - } - - for (auto &cell_it : mod_it.second->cells_) - { - printf("found cell in module!!!\n"); - } - }*/ } } @@ -217,19 +185,19 @@ BOOST_PYTHON_MODULE(libyosys) .def("get_modules", &YosysDesign::get_modules) ; - class_("YosysModule", init()) + class_("YosysModule", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("get_cells", &YosysModule::get_cells) .def("get_wires", &YosysModule::get_wires) ; - class_("YosysCell", init()) + class_("YosysCell", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; - class_("YosysWire", init()) + class_("YosysWire", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; From 7911379d4a3806af8141e5737e217a2b05368d6c Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 28 Jun 2018 15:07:21 +0200 Subject: [PATCH 04/57] Introduced namespace and removed class-prefixes to increase readability --- kernel/python_wrappers.cc | 348 +++++++++++++++++++------------------- 1 file changed, 175 insertions(+), 173 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index ae141c808..78011a8c5 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -3,210 +3,212 @@ #include "yosys.h" #include -struct YosysDesign; -struct YosysModule; -struct YosysCell; -struct YosysWire; +namespace YOSYS_PYTHON { -void yosys_setup() -{ - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; + struct Design; + struct Module; + struct Cell; + struct Wire; - Yosys::yosys_setup(); - Yosys::yosys_banner(); -} - -void run(std::string command) -{ - Yosys::run_pass(command); -} - -void yosys_shutdown() -{ - Yosys::yosys_shutdown(); -} - -struct YosysCell -{ - Yosys::RTLIL::IdString name; - Yosys::RTLIL::IdString parent_name; - - YosysCell(Yosys::RTLIL::Cell* ref) + void yosys_setup() { - this->name = ref->name; - this->parent_name = ref->module->name; + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + + Yosys::yosys_setup(); + Yosys::yosys_banner(); } + + void run(std::string command) + { + Yosys::run_pass(command); + } + + void yosys_shutdown() + { + Yosys::yosys_shutdown(); + } + + struct Cell + { + Yosys::RTLIL::IdString name; + Yosys::RTLIL::IdString parent_name; + + Cell(Yosys::RTLIL::Cell* ref) + { + this->name = ref->name; + this->parent_name = ref->module->name; + } - Yosys::RTLIL::Cell* get_cpp_obj() + Yosys::RTLIL::Cell* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + if(active_design->modules_[this->parent_name] == NULL) + return NULL; + return active_design->modules_[this->parent_name]->cells_[this->name]; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const Cell &cell) { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->modules_[this->parent_name] == NULL) - return NULL; - return active_design->modules_[this->parent_name]->cells_[this->name]; + ostr << "Cell with name " << cell.name.c_str(); + return ostr; } -}; -std::ostream &operator<<(std::ostream &ostr, const YosysCell &cell) -{ - ostr << "Cell with name " << cell.name.c_str(); - return ostr; -} - -struct YosysWire -{ - Yosys::RTLIL::IdString name; - Yosys::RTLIL::IdString parent_name; - - YosysWire(Yosys::RTLIL::Wire* ref) + struct Wire { - this->name = ref->name; - this->parent_name = ref->module->name; - } + Yosys::RTLIL::IdString name; + Yosys::RTLIL::IdString parent_name; + + Wire(Yosys::RTLIL::Wire* ref) + { + this->name = ref->name; + this->parent_name = ref->module->name; + } - Yosys::RTLIL::Wire* get_cpp_obj() + Yosys::RTLIL::Wire* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + if(active_design->modules_[this->parent_name] == NULL) + return NULL; + return active_design->modules_[this->parent_name]->wires_[this->name]; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const Wire &wire) { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->modules_[this->parent_name] == NULL) - return NULL; - return active_design->modules_[this->parent_name]->wires_[this->name]; - } -}; - -std::ostream &operator<<(std::ostream &ostr, const YosysWire &wire) -{ - ostr << "Wire with name " << wire.name.c_str(); - return ostr; -} - -struct YosysModule -{ - Yosys::RTLIL::IdString name; - unsigned int parent_hashid; - - YosysModule(Yosys::RTLIL::Module* ref) - { - this->name = ref->name; - this->parent_hashid = ref->design->hashidx_; + ostr << "Wire with name " << wire.name.c_str(); + return ostr; } - Yosys::RTLIL::Module* get_cpp_obj() + struct Module { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->hashidx_ != this->parent_hashid) - printf("Somehow the active design changed!\n"); - return active_design->modules_[this->name]; - } + Yosys::RTLIL::IdString name; + unsigned int parent_hashid; - boost::python::list get_cells() - { - Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); - boost::python::list result; - if(cpp_mod == NULL) + Module(Yosys::RTLIL::Module* ref) + { + this->name = ref->name; + this->parent_hashid = ref->design->hashidx_; + } + + Yosys::RTLIL::Module* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + if(active_design->hashidx_ != this->parent_hashid) + printf("Somehow the active design changed!\n"); + return active_design->modules_[this->name]; + } + + boost::python::list get_cells() + { + Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + boost::python::list result; + if(cpp_mod == NULL) + return result; + for(auto &cell_it : cpp_mod->cells_) + { + result.append(new Cell(cell_it.second)); + } return result; - for(auto &cell_it : cpp_mod->cells_) - { - result.append(new YosysCell(cell_it.second)); } - return result; - } - boost::python::list get_wires() - { - Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); - boost::python::list result; - if(cpp_mod == NULL) + boost::python::list get_wires() + { + Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + boost::python::list result; + if(cpp_mod == NULL) + return result; + for(auto &wire_it : cpp_mod->wires_) + { + result.append(new Wire(wire_it.second)); + } return result; - for(auto &wire_it : cpp_mod->wires_) - { - result.append(new YosysWire(wire_it.second)); } - return result; - } -}; + }; -std::ostream &operator<<(std::ostream &ostr, const YosysModule &module) -{ - ostr << "Module with name " << module.name.c_str(); - return ostr; -} - -struct YosysDesign -{ - unsigned int hashid; - - YosysDesign(unsigned int hashid) + std::ostream &operator<<(std::ostream &ostr, const Module &module) { - this->hashid = hashid; + ostr << "Module with name " << module.name.c_str(); + return ostr; } - YosysDesign() + struct Design { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design != NULL) + unsigned int hashid; + + Design(unsigned int hashid) { - printf("design is not null and has id %u\n", active_design->hashidx_); - this->hashid = active_design->hashidx_; + this->hashid = hashid; } - } - boost::python::list get_modules() - { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - boost::python::list result; - if(active_design == NULL) + Design() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design != NULL) + { + printf("design is not null and has id %u\n", active_design->hashidx_); + this->hashid = active_design->hashidx_; + } + } + + boost::python::list get_modules() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + boost::python::list result; + if(active_design == NULL) + return result; + for(auto &mod_it : active_design->modules_) + { + result.append(new Module(mod_it.second)); + } return result; - for(auto &mod_it : active_design->modules_) - { - result.append(new YosysModule(mod_it.second)); } - return result; + }; + + std::ostream &operator<<(std::ostream &ostr, const Design &design) + { + ostr << "Design with id " << design.hashid; + return ostr; + } + + BOOST_PYTHON_MODULE(libyosys) + { + using namespace boost::python; + + class_("Design", init()) + .def(init<>()) + .def("get_modules", &Design::get_modules) + ; + + class_("Module", no_init) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_cells", &Module::get_cells) + .def("get_wires", &Module::get_wires) + ; + + class_("Cell", no_init) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("Wire", no_init) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + + def("yosys_setup",yosys_setup); + def("run",run); + def("yosys_shutdown",yosys_shutdown); } -}; -std::ostream &operator<<(std::ostream &ostr, const YosysDesign &design) -{ - ostr << "Design with id " << design.hashid; - return ostr; } - -BOOST_PYTHON_MODULE(libyosys) -{ - using namespace boost::python; - - class_("YosysDesign", init()) - .def(init<>()) - .def("get_modules", &YosysDesign::get_modules) - ; - - class_("YosysModule", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_cells", &YosysModule::get_cells) - .def("get_wires", &YosysModule::get_wires) - ; - - class_("YosysCell", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - ; - - class_("YosysWire", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - ; - - - def("yosys_setup",yosys_setup); - def("run",run); - def("yosys_shutdown",yosys_shutdown); -} - #endif - From 8ebaeecd83b22db5c196356844f01ce69d0b4bea Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 9 Jul 2018 15:48:06 +0200 Subject: [PATCH 05/57] multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues --- kernel/python_wrappers.cc | 92 ++++++++++++++++++++------------------- kernel/rtlil.cc | 55 +++++++++++++++++++++++ kernel/rtlil.h | 16 +++++++ 3 files changed, 118 insertions(+), 45 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 78011a8c5..c778f3919 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -31,79 +31,64 @@ namespace YOSYS_PYTHON { struct Cell { - Yosys::RTLIL::IdString name; - Yosys::RTLIL::IdString parent_name; + unsigned int id; Cell(Yosys::RTLIL::Cell* ref) { - this->name = ref->name; - this->parent_name = ref->module->name; + this->id = ref->hashidx_; } - Yosys::RTLIL::Cell* get_cpp_obj() + Yosys::RTLIL::Cell* get_cpp_obj() const { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->modules_[this->parent_name] == NULL) - return NULL; - return active_design->modules_[this->parent_name]->cells_[this->name]; + return Yosys::RTLIL::Cell::get_all_cells()->at(this->id); } }; std::ostream &operator<<(std::ostream &ostr, const Cell &cell) { - ostr << "Cell with name " << cell.name.c_str(); + if(cell.get_cpp_obj() != NULL) + ostr << "Cell with name " << cell.get_cpp_obj()->name.c_str(); + else + ostr << "deleted cell"; return ostr; } struct Wire { - Yosys::RTLIL::IdString name; - Yosys::RTLIL::IdString parent_name; + unsigned int id; Wire(Yosys::RTLIL::Wire* ref) { - this->name = ref->name; - this->parent_name = ref->module->name; + this->id = ref->hashidx_; } - Yosys::RTLIL::Wire* get_cpp_obj() + Yosys::RTLIL::Wire* get_cpp_obj() const { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->modules_[this->parent_name] == NULL) - return NULL; - return active_design->modules_[this->parent_name]->wires_[this->name]; + return Yosys::RTLIL::Wire::get_all_wires()->at(this->id); } }; std::ostream &operator<<(std::ostream &ostr, const Wire &wire) { - ostr << "Wire with name " << wire.name.c_str(); + if(wire.get_cpp_obj() != NULL) + ostr << "Wire with name " << wire.get_cpp_obj()->name.c_str(); + else + ostr << "deleted wire"; return ostr; } struct Module { - Yosys::RTLIL::IdString name; - unsigned int parent_hashid; + unsigned int id; Module(Yosys::RTLIL::Module* ref) { - this->name = ref->name; - this->parent_hashid = ref->design->hashidx_; + this->id = ref->hashidx_; } - Yosys::RTLIL::Module* get_cpp_obj() + Yosys::RTLIL::Module* get_cpp_obj() const { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->hashidx_ != this->parent_hashid) - printf("Somehow the active design changed!\n"); - return active_design->modules_[this->name]; + return Yosys::RTLIL::Module::get_all_modules()->at(this->id); } boost::python::list get_cells() @@ -135,7 +120,10 @@ namespace YOSYS_PYTHON { std::ostream &operator<<(std::ostream &ostr, const Module &module) { - ostr << "Module with name " << module.name.c_str(); + if(module.get_cpp_obj() != NULL) + ostr << "Module with name " << module.get_cpp_obj()->name.c_str(); + else + ostr << "deleted module"; return ostr; } @@ -150,21 +138,24 @@ namespace YOSYS_PYTHON { Design() { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design != NULL) - { - printf("design is not null and has id %u\n", active_design->hashidx_); - this->hashid = active_design->hashidx_; - } + Yosys::RTLIL::Design* new_design = new Yosys::RTLIL::Design(); + this->hashid = new_design->hashidx_; + } + + Yosys::RTLIL::Design* get_cpp_obj() + { + return Yosys::RTLIL::Design::get_all_designs()->at(hashid); } boost::python::list get_modules() { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); boost::python::list result; - if(active_design == NULL) + if(cpp_design == NULL) + { return result; - for(auto &mod_it : active_design->modules_) + } + for(auto &mod_it : cpp_design->modules_) { result.append(new Module(mod_it.second)); } @@ -178,6 +169,16 @@ namespace YOSYS_PYTHON { return ostr; } + unsigned int get_active_design_id() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design != NULL) + { + return active_design->hashidx_; + } + return 0; + } + BOOST_PYTHON_MODULE(libyosys) { using namespace boost::python; @@ -207,6 +208,7 @@ namespace YOSYS_PYTHON { def("yosys_setup",yosys_setup); def("run",run); + def("get_active_design_id",get_active_design_id); def("yosys_shutdown",yosys_shutdown); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a4fa2cf04..df6e0af62 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -358,6 +358,10 @@ RTLIL::Design::Design() refcount_modules_ = 0; selection_stack.push_back(RTLIL::Selection()); + +#ifdef WITH_PYTHON + RTLIL::Design::get_all_designs()->insert(std::pair(hashidx_, this)); +#endif } RTLIL::Design::~Design() @@ -368,8 +372,19 @@ RTLIL::Design::~Design() delete n; for (auto n : verilog_globals) delete n; +#ifdef WITH_PYTHON + RTLIL::Design::get_all_designs()->erase(hashidx_); +#endif } +#ifdef WITH_PYTHON +static std::map *all_designs = new std::map(); +std::map *RTLIL::Design::get_all_designs(void) +{ + return all_designs; +} +#endif + RTLIL::ObjRange RTLIL::Design::modules() { return RTLIL::ObjRange(&modules_, &refcount_modules_); @@ -625,6 +640,11 @@ RTLIL::Module::Module() design = nullptr; refcount_wires_ = 0; refcount_cells_ = 0; + +#ifdef WITH_PYTHON + std::cout << "inserting module with name " << this->name.c_str() << "\n"; + RTLIL::Module::get_all_modules()->insert(std::pair(hashidx_, this)); +#endif } RTLIL::Module::~Module() @@ -637,8 +657,19 @@ RTLIL::Module::~Module() delete it->second; for (auto it = processes.begin(); it != processes.end(); ++it) delete it->second; +#ifdef WITH_PYTHON + RTLIL::Module::get_all_modules()->erase(hashidx_); +#endif } +#ifdef WITH_PYTHON +static std::map *all_modules = new std::map(); +std::map *RTLIL::Module::get_all_modules(void) +{ + return all_modules; +} +#endif + RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, bool mayfail) { if (mayfail) @@ -2187,8 +2218,20 @@ RTLIL::Wire::Wire() port_input = false; port_output = false; upto = false; + +#ifdef WITH_PYTHON + RTLIL::Wire::get_all_wires()->insert(std::pair(hashidx_, this)); +#endif } +#ifdef WITH_PYTHON +static std::map *all_wires = new std::map(); +std::map *RTLIL::Wire::get_all_wires(void) +{ + return all_wires; +} +#endif + RTLIL::Memory::Memory() { static unsigned int hashidx_count = 123456789; @@ -2208,8 +2251,20 @@ RTLIL::Cell::Cell() : module(nullptr) // log("#memtrace# %p\n", this); memhasher(); + +#ifdef WITH_PYTHON + RTLIL::Cell::get_all_cells()->insert(std::pair(hashidx_, this)); +#endif } +#ifdef WITH_PYTHON +static std::map *all_cells = new std::map(); +std::map *RTLIL::Cell::get_all_cells(void) +{ + return all_cells; +} +#endif + bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const { return connections_.count(portname) != 0; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 54d0b8c22..232a8c13a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -874,6 +874,10 @@ struct RTLIL::Design } } +#ifdef WITH_PYTHON + static std::map *get_all_designs(void); +#endif + std::vector selected_modules() const; std::vector selected_whole_modules() const; std::vector selected_whole_modules_warn() const; @@ -1130,6 +1134,10 @@ public: RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = ""); + +#ifdef WITH_PYTHON + static std::map *get_all_modules(void); +#endif }; struct RTLIL::Wire : public RTLIL::AttrObject @@ -1152,6 +1160,10 @@ public: RTLIL::IdString name; int width, start_offset, port_id; bool port_input, port_output, upto; + +#ifdef WITH_PYTHON + static std::map *get_all_wires(void); +#endif }; struct RTLIL::Memory : public RTLIL::AttrObject @@ -1214,6 +1226,10 @@ public: } template void rewrite_sigspecs(T &functor); + +#ifdef WITH_PYTHON + static std::map *get_all_cells(void); +#endif }; struct RTLIL::CaseRule From da8083dbd07404fb765e0ffebed6f5477b6d99ad Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 9 Jul 2018 16:01:56 +0200 Subject: [PATCH 06/57] commands can now be run on arbitrary designs, not only on the active one --- kernel/python_wrappers.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index c778f3919..04aebb1b8 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -161,6 +161,13 @@ namespace YOSYS_PYTHON { } return result; } + + void run(std::string command) + { + Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); + if(cpp_design != NULL) + Yosys::run_pass(command, cpp_design); + } }; std::ostream &operator<<(std::ostream &ostr, const Design &design) @@ -184,8 +191,11 @@ namespace YOSYS_PYTHON { using namespace boost::python; class_("Design", init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def(init<>()) .def("get_modules", &Design::get_modules) + .def("run",&Design::run) ; class_("Module", no_init) From 55df7fff19cfaa42197effc31ac8de07f9090924 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 9 Jul 2018 16:02:10 +0200 Subject: [PATCH 07/57] removed debug output --- kernel/rtlil.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index df6e0af62..5cef90206 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -642,7 +642,6 @@ RTLIL::Module::Module() refcount_cells_ = 0; #ifdef WITH_PYTHON - std::cout << "inserting module with name " << this->name.c_str() << "\n"; RTLIL::Module::get_all_modules()->insert(std::pair(hashidx_, this)); #endif } From e7d3f3cd464fe323872285bed40e6f347683147b Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 10 Jul 2018 08:52:36 +0200 Subject: [PATCH 08/57] added destructors for wires and cells --- kernel/rtlil.cc | 14 ++++++++++++++ kernel/rtlil.h | 3 ++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5cef90206..6e8b51682 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2223,6 +2223,13 @@ RTLIL::Wire::Wire() #endif } +RTLIL::Wire::~Wire() +{ +#ifdef WITH_PYTHON + RTLIL::Wire::get_all_wires()->erase(hashidx_); +#endif +} + #ifdef WITH_PYTHON static std::map *all_wires = new std::map(); std::map *RTLIL::Wire::get_all_wires(void) @@ -2256,6 +2263,13 @@ RTLIL::Cell::Cell() : module(nullptr) #endif } +RTLIL::Cell::~Cell() +{ +#ifdef WITH_PYTHON + RTLIL::Cell::get_all_cells()->erase(hashidx_); +#endif +} + #ifdef WITH_PYTHON static std::map *all_cells = new std::map(); std::map *RTLIL::Cell::get_all_cells(void) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 232a8c13a..e71a5fceb 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1149,7 +1149,7 @@ protected: // use module->addWire() and module->remove() to create or destroy wires friend struct RTLIL::Module; Wire(); - ~Wire() { }; + ~Wire(); public: // do not simply copy wires @@ -1186,6 +1186,7 @@ protected: // use module->addCell() and module->remove() to create or destroy cells friend struct RTLIL::Module; Cell(); + ~Cell(); public: // do not simply copy cells From 0371519c3977fcf4ffc71315cb9e0aae3ee967a2 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 10 Jul 2018 12:51:02 +0200 Subject: [PATCH 09/57] Added Monitor class that can monitor all changes in a Design or in a Module --- kernel/python_wrappers.cc | 119 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 04aebb1b8..4ba2a1185 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -1,6 +1,10 @@ #ifdef WITH_PYTHON #include "yosys.h" +#include +#include +#include +#include #include namespace YOSYS_PYTHON { @@ -9,6 +13,7 @@ namespace YOSYS_PYTHON { struct Module; struct Cell; struct Wire; + struct Monitor; void yosys_setup() { @@ -116,6 +121,8 @@ namespace YOSYS_PYTHON { } return result; } + + void register_monitor(Monitor* const m); }; std::ostream &operator<<(std::ostream &ostr, const Module &module) @@ -168,8 +175,113 @@ namespace YOSYS_PYTHON { if(cpp_design != NULL) Yosys::run_pass(command, cpp_design); } + + void register_monitor(Monitor* const m); }; + struct Monitor : public Yosys::RTLIL::Monitor + { + + virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_add(new Module(module)); + } + + virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_del(new Module(module)); + } + + virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE + { + //log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE + { + //log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + { + //log("#TRACE# New connections in module %s:\n", log_id(module)); + //for (auto &sigsig : sigsig_vec) + // log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); + } + + virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_blackout(new Module(module)); + } + + //virtual void notify_connect(Cell*, const Yosys::RTLIL::IdString&, const Yosys::RTLIL::SigSpec&, Yosys::RTLIL::SigSpec&) { } + //virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } + //virtual void notify_connect(RTLIL::Module*, const std::vector&) { } + + virtual void py_notify_module_add(Module*){}; + virtual void py_notify_module_del(Module*){}; + virtual void py_notify_blackout(Module*){}; + + }; + + struct MonitorWrap : Monitor, boost::python::wrapper + { + void py_notify_module_add(Module* m) + { + if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) + py_notify_module_add(m); + else + Monitor::py_notify_module_add(m); + } + + void default_py_notify_module_add(Module* m) + { + this->Monitor::py_notify_module_add(m); + } + + void py_notify_module_del(Module* m) + { + if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) + py_notify_module_del(m); + else + Monitor::py_notify_module_del(m); + } + + void default_py_notify_module_del(Module* m) + { + this->Monitor::py_notify_module_del(m); + } + + void py_notify_blackout(Module* m) + { + if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) + py_notify_blackout(m); + else + Monitor::py_notify_blackout(m); + } + + void default_py_notify_blackout(Module* m) + { + this->Monitor::py_notify_blackout(m); + } + }; + + void Design::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Design* cpp_design = this->get_cpp_obj(); + if(cpp_design == NULL) + return; + cpp_design->monitors.insert(m); + } + + void Module::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Module* cpp_design = this->get_cpp_obj(); + if(cpp_design == NULL) + return; + cpp_design->monitors.insert(m); + } + std::ostream &operator<<(std::ostream &ostr, const Design &design) { ostr << "Design with id " << design.hashid; @@ -196,6 +308,7 @@ namespace YOSYS_PYTHON { .def(init<>()) .def("get_modules", &Design::get_modules) .def("run",&Design::run) + .def("register_monitor", &Design::register_monitor) ; class_("Module", no_init) @@ -203,6 +316,7 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("get_cells", &Module::get_cells) .def("get_wires", &Module::get_wires) + .def("register_monitor", &Module::register_monitor) ; class_("Cell", no_init) @@ -215,6 +329,11 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; + class_("Monitor") + .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) + .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) + .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + ; def("yosys_setup",yosys_setup); def("run",run); From b57dafce6819516d529cc0077b95cb3293a5dc06 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 1 Aug 2018 08:04:08 +0200 Subject: [PATCH 10/57] removed unused library and already present compiler flag --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 09cf18497..ca17c4476 100644 --- a/Makefile +++ b/Makefile @@ -19,7 +19,7 @@ ENABLE_PROTOBUF := 0 # python wrappers ENABLE_PYTHON := 1 -PYTHON_VERSION := 3.5 +PYTHON_VERSION := 3.6 # other configuration flags ENABLE_GPROF := 0 @@ -233,8 +233,8 @@ TARGETS += libyosys.so endif ifeq ($(ENABLE_PYTHON),1) -LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -fPIC -D WITH_PYTHON +LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) +CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON OBJS += kernel/python_wrappers.o endif From 57d2197703da12750fb508736ccfaf59b847ea22 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 1 Aug 2018 08:05:39 +0200 Subject: [PATCH 11/57] Cleaned up comments --- kernel/python_wrappers.cc | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 4ba2a1185..ba7be9106 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -194,19 +194,17 @@ namespace YOSYS_PYTHON { virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE { - //log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE { - //log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE { - //log("#TRACE# New connections in module %s:\n", log_id(module)); - //for (auto &sigsig : sigsig_vec) - // log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE @@ -214,10 +212,6 @@ namespace YOSYS_PYTHON { py_notify_blackout(new Module(module)); } - //virtual void notify_connect(Cell*, const Yosys::RTLIL::IdString&, const Yosys::RTLIL::SigSpec&, Yosys::RTLIL::SigSpec&) { } - //virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } - //virtual void notify_connect(RTLIL::Module*, const std::vector&) { } - virtual void py_notify_module_add(Module*){}; virtual void py_notify_module_del(Module*){}; virtual void py_notify_blackout(Module*){}; From 79d7e608cfcc7fe19647313521eed908f3784503 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 1 Aug 2018 10:08:23 +0200 Subject: [PATCH 12/57] Setup is called automatically when the module is loaded, shutdown when python exits --- kernel/python_wrappers.cc | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index ba7be9106..718e3f5c1 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -15,25 +15,11 @@ namespace YOSYS_PYTHON { struct Wire; struct Monitor; - void yosys_setup() - { - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; - - Yosys::yosys_setup(); - Yosys::yosys_banner(); - } - void run(std::string command) { Yosys::run_pass(command); } - void yosys_shutdown() - { - Yosys::yosys_shutdown(); - } - struct Cell { unsigned int id; @@ -292,10 +278,29 @@ namespace YOSYS_PYTHON { return 0; } + struct Initializer + { + Initializer() { + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + Yosys::yosys_setup(); + Yosys::yosys_banner(); + } + + Initializer(Initializer const &) {} + + ~Initializer() { + Yosys::yosys_shutdown(); + } + }; + BOOST_PYTHON_MODULE(libyosys) { using namespace boost::python; + class_("Initializer"); + scope().attr("_hidden") = new Initializer(); + class_("Design", init()) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) @@ -329,10 +334,8 @@ namespace YOSYS_PYTHON { .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) ; - def("yosys_setup",yosys_setup); def("run",run); def("get_active_design_id",get_active_design_id); - def("yosys_shutdown",yosys_shutdown); } } From 416946a16ad9ddbbf67747ba02a935f4f5d8dc40 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 1 Aug 2018 10:27:35 +0200 Subject: [PATCH 13/57] Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more --- kernel/python_wrappers.cc | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 718e3f5c1..1ba2c011a 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -23,15 +23,20 @@ namespace YOSYS_PYTHON { struct Cell { unsigned int id; + Yosys::RTLIL::Cell* ref_obj; Cell(Yosys::RTLIL::Cell* ref) { this->id = ref->hashidx_; + this->ref_obj = ref; } Yosys::RTLIL::Cell* get_cpp_obj() const { - return Yosys::RTLIL::Cell::get_all_cells()->at(this->id); + Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->id); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } }; @@ -47,15 +52,20 @@ namespace YOSYS_PYTHON { struct Wire { unsigned int id; + Yosys::RTLIL::Wire* ref_obj; Wire(Yosys::RTLIL::Wire* ref) { this->id = ref->hashidx_; + this->ref_obj = ref; } Yosys::RTLIL::Wire* get_cpp_obj() const { - return Yosys::RTLIL::Wire::get_all_wires()->at(this->id); + Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->id); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } }; @@ -71,15 +81,20 @@ namespace YOSYS_PYTHON { struct Module { unsigned int id; + Yosys::RTLIL::Module* ref_obj; Module(Yosys::RTLIL::Module* ref) { this->id = ref->hashidx_; + this->ref_obj = ref; } Yosys::RTLIL::Module* get_cpp_obj() const { - return Yosys::RTLIL::Module::get_all_modules()->at(this->id); + Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->id); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } boost::python::list get_cells() @@ -122,22 +137,28 @@ namespace YOSYS_PYTHON { struct Design { - unsigned int hashid; + unsigned int id; + Yosys::RTLIL::Design* ref_obj; Design(unsigned int hashid) { - this->hashid = hashid; + this->id = hashid; + this->ref_obj = Yosys::RTLIL::Design::get_all_designs()->at(this->id); } Design() { Yosys::RTLIL::Design* new_design = new Yosys::RTLIL::Design(); - this->hashid = new_design->hashidx_; + this->id = new_design->hashidx_; + this->ref_obj = new_design; } Yosys::RTLIL::Design* get_cpp_obj() { - return Yosys::RTLIL::Design::get_all_designs()->at(hashid); + Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->id); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } boost::python::list get_modules() @@ -264,7 +285,7 @@ namespace YOSYS_PYTHON { std::ostream &operator<<(std::ostream &ostr, const Design &design) { - ostr << "Design with id " << design.hashid; + ostr << "Design with id " << design.id; return ostr; } From bf7b73acfc2b5e46206e5688b8a6e8d9b0d60d8f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 13 Aug 2018 15:18:46 +0200 Subject: [PATCH 14/57] Added Wrappers for: -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h --- Makefile | 4 +- kernel/python_wrappers.cc | 3049 +++++++++++++++++++++++++++++++++++-- kernel/rtlil.cc | 32 +- kernel/rtlil.h | 14 +- 4 files changed, 2940 insertions(+), 159 deletions(-) diff --git a/Makefile b/Makefile index ca17c4476..691f43798 100644 --- a/Makefile +++ b/Makefile @@ -19,7 +19,7 @@ ENABLE_PROTOBUF := 0 # python wrappers ENABLE_PYTHON := 1 -PYTHON_VERSION := 3.6 +PYTHON_VERSION := 3.5 # other configuration flags ENABLE_GPROF := 0 @@ -233,7 +233,7 @@ TARGETS += libyosys.so endif ifeq ($(ENABLE_PYTHON),1) -LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) +LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON OBJS += kernel/python_wrappers.o endif diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 1ba2c011a..18b0010ae 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -6,92 +6,524 @@ #include #include #include +#include + +using namespace Yosys; namespace YOSYS_PYTHON { - struct Design; - struct Module; + struct IdString; + struct Const; + struct CaseRule; + struct SwitchRule; + struct SyncRule; + struct Process; + struct SigChunk; + struct SigBit; + struct SigSpec; struct Cell; struct Wire; + struct Memory; + struct Module; + struct Design; struct Monitor; + typedef Yosys::RTLIL::State State; void run(std::string command) { Yosys::run_pass(command); } + struct IdString + { + Yosys::RTLIL::IdString* ref_obj; + + IdString(Yosys::RTLIL::IdString* ref = new Yosys::RTLIL::IdString()) + { + this->ref_obj = new Yosys::RTLIL::IdString(*ref); + } + + ~IdString() + { + delete(this->ref_obj); + } + + IdString(Yosys::RTLIL::IdString ref) + { + this->ref_obj = new Yosys::RTLIL::IdString(ref); + } + + IdString(const std::string &str) + { + this->ref_obj = new Yosys::RTLIL::IdString(str); + } + + Yosys::RTLIL::IdString* get_cpp_obj() const + { + return ref_obj; + } + + //WRAPPED static inline int get_reference(int idx) + static inline int get_reference(int idx); + + //WRAPPED static inline void put_reference(int idx) + static inline void put_reference(int idx); + + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } + bool in_IdString(IdString *rhs); + + //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } + bool in_std_string(std::string rhs); + }; + + std::ostream &operator<<(std::ostream &ostr, const IdString &ref) + { + ostr << ref.ref_obj->str(); + return ostr; + } + struct Const + { + Yosys::RTLIL::Const* ref_obj; + + Const(Yosys::RTLIL::Const* ref = new Yosys::RTLIL::Const()) + { + this->ref_obj = new Yosys::RTLIL::Const(*ref); + } + + ~Const() + { + delete(this->ref_obj); + } + + Const(Yosys::RTLIL::Const ref) + { + this->ref_obj = new Yosys::RTLIL::Const(ref); + } + + Yosys::RTLIL::Const* get_cpp_obj() const + { + return ref_obj; + } + + //WRAPPED int as_int(bool is_signed = false) const; + int as_int(bool is_signed = false); + + //WRAPPED static Const from_string(std::string str); + static Const from_string(std::string str); + + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { + inline Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); + }; + + std::ostream &operator<<(std::ostream &ostr, const Const &ref) + { + ostr << ref.ref_obj->as_string(); + return ostr; + } + struct CaseRule + { + Yosys::RTLIL::CaseRule* ref_obj; + + CaseRule(Yosys::RTLIL::CaseRule* ref = new Yosys::RTLIL::CaseRule()) + { + this->ref_obj = ref->clone(); + } + + ~CaseRule() + { + delete(this->ref_obj); + } + + CaseRule(Yosys::RTLIL::CaseRule ref) + { + this->ref_obj = ref.clone(); + } + + Yosys::RTLIL::CaseRule* get_cpp_obj() const + { + return ref_obj; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const CaseRule &ref) + { + ostr << "CaseRule object at " << ref.ref_obj; + return ostr; + } + struct SwitchRule + { + Yosys::RTLIL::SwitchRule* ref_obj; + + SwitchRule(Yosys::RTLIL::SwitchRule* ref = new Yosys::RTLIL::SwitchRule()) + { + this->ref_obj = ref->clone(); + } + + ~SwitchRule() + { + delete(this->ref_obj); + } + + SwitchRule(Yosys::RTLIL::SwitchRule ref) + { + this->ref_obj = ref.clone(); + } + + Yosys::RTLIL::SwitchRule* get_cpp_obj() const + { + return ref_obj; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const SwitchRule &ref) + { + ostr << "SwitchRule object at " << ref.ref_obj; + return ostr; + } + struct SyncRule + { + Yosys::RTLIL::SyncRule* ref_obj; + + SyncRule(Yosys::RTLIL::SyncRule* ref = new Yosys::RTLIL::SyncRule()) + { + this->ref_obj = ref->clone(); + } + + ~SyncRule() + { + delete(this->ref_obj); + } + + SyncRule(Yosys::RTLIL::SyncRule ref) + { + this->ref_obj = ref.clone(); + } + + Yosys::RTLIL::SyncRule* get_cpp_obj() const + { + return ref_obj; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const SyncRule &ref) + { + ostr << "SyncRule object at " << ref.ref_obj; + return ostr; + } + struct Process + { + Yosys::RTLIL::Process* ref_obj; + + Process(Yosys::RTLIL::Process* ref = new Yosys::RTLIL::Process()) + { + this->ref_obj = ref->clone(); + } + + ~Process() + { + delete(this->ref_obj); + } + + Process(Yosys::RTLIL::Process ref) + { + this->ref_obj = ref.clone(); + } + + Yosys::RTLIL::Process* get_cpp_obj() const + { + return ref_obj; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const Process &ref) + { + ostr << "Process with name " << ref.ref_obj->name.c_str(); + return ostr; + } + struct SigChunk + { + Yosys::RTLIL::SigChunk* ref_obj; + + SigChunk(Yosys::RTLIL::SigChunk* ref = new Yosys::RTLIL::SigChunk()) + { + this->ref_obj = new Yosys::RTLIL::SigChunk(*ref); + } + + ~SigChunk() + { + delete(this->ref_obj); + } + + SigChunk(Yosys::RTLIL::SigChunk ref) + { + this->ref_obj = new Yosys::RTLIL::SigChunk(ref); + } + + Yosys::RTLIL::SigChunk* get_cpp_obj() const + { + return ref_obj; + } + + //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; + SigChunk extract(int offset, int length); + }; + + std::ostream &operator<<(std::ostream &ostr, const SigChunk &ref) + { + ostr << "SigChunk object at " << ref.ref_obj; + return ostr; + } + struct SigBit + { + Yosys::RTLIL::SigBit* ref_obj; + + SigBit(Yosys::RTLIL::SigBit* ref = new Yosys::RTLIL::SigBit()) + { + this->ref_obj = new Yosys::RTLIL::SigBit(*ref); + } + + ~SigBit() + { + delete(this->ref_obj); + } + + SigBit(Yosys::RTLIL::SigBit ref) + { + this->ref_obj = new Yosys::RTLIL::SigBit(ref); + } + + Yosys::RTLIL::SigBit* get_cpp_obj() const + { + return ref_obj; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const SigBit &ref) + { + ostr << "SigBit object at " << ref.ref_obj; + return ostr; + } + struct SigSpec + { + Yosys::RTLIL::SigSpec* ref_obj; + + SigSpec(Yosys::RTLIL::SigSpec* ref = new Yosys::RTLIL::SigSpec()) + { + this->ref_obj = new Yosys::RTLIL::SigSpec(*ref); + } + + ~SigSpec() + { + delete(this->ref_obj); + } + + SigSpec(Yosys::RTLIL::SigSpec ref) + { + this->ref_obj = new Yosys::RTLIL::SigSpec(ref); + } + + Yosys::RTLIL::SigSpec* get_cpp_obj() const + { + return ref_obj; + } + + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); + void replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with); + + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; + void replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other); + + //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); + void replace_int_SigSpec(int offset, SigSpec *with); + + //WRAPPED void remove(const RTLIL::SigSpec &pattern); + void remove_SigSpec(SigSpec *pattern); + + //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; + void remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); + + //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); + void remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); + + //WRAPPED void remove(const pool &pattern); + void remove_pool_SigBit(boost::python::list *pattern); + + //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; + void remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + + //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); + void remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + + //WRAPPED void remove(int offset, int length = 1); + void remove_int_int(int offset, int length = 1); + + //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; + SigSpec extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); + + //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; + SigSpec extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + + //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; + SigSpec extract_int_int(int offset, int length = 1); + + //WRAPPED void append(const RTLIL::SigSpec &signal); + void append(SigSpec *signal); + + //WRAPPED void append_bit(const RTLIL::SigBit &bit); + void append_bit(SigBit *bit); + + //WRAPPED void extend_u0(int width, bool is_signed = false); + void extend_u0(int width, bool is_signed = false); + + //WRAPPED RTLIL::SigSpec repeat(int num) const; + SigSpec repeat(int num); + + //WRAPPED int as_int(bool is_signed = false) const; + int as_int(bool is_signed = false); + + //WRAPPED bool match(std::string pattern) const; + bool match(std::string pattern); + + //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + static bool parse(SigSpec *sig, Module *module, std::string str); + + //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); + static bool parse_sel(SigSpec *sig, Design *design, Module *module, std::string str); + + //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + static bool parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str); + }; + + std::ostream &operator<<(std::ostream &ostr, const SigSpec &ref) + { + ostr << "SigSpec object at " << ref.ref_obj; + return ostr; + } struct Cell { - unsigned int id; + unsigned int hashidx_; Yosys::RTLIL::Cell* ref_obj; Cell(Yosys::RTLIL::Cell* ref) { - this->id = ref->hashidx_; + this->hashidx_ = ref->hashidx_; this->ref_obj = ref; } - + Yosys::RTLIL::Cell* get_cpp_obj() const { - Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->id); + Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->hashidx_); if(ret != NULL && ret == this->ref_obj) return ret; return NULL; } + + //WRAPPED bool hasPort(RTLIL::IdString portname) const; + bool hasPort(IdString *portname); + + //WRAPPED void unsetPort(RTLIL::IdString portname); + void unsetPort(IdString *portname); + + //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); + void setPort(IdString *portname, SigSpec *signal); + + //WRAPPED bool input(RTLIL::IdString portname) const; + bool input(IdString *portname); + + //WRAPPED bool output(RTLIL::IdString portname) const; + bool output(IdString *portname); + + //WRAPPED bool hasParam(RTLIL::IdString paramname) const; + bool hasParam(IdString *paramname); + + //WRAPPED void unsetParam(RTLIL::IdString paramname); + void unsetParam(IdString *paramname); + + //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); + void setParam(IdString *paramname, Const *value); + + //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); }; - std::ostream &operator<<(std::ostream &ostr, const Cell &cell) + std::ostream &operator<<(std::ostream &ostr, const Cell &ref) { - if(cell.get_cpp_obj() != NULL) - ostr << "Cell with name " << cell.get_cpp_obj()->name.c_str(); + if(ref.get_cpp_obj() != NULL) + ostr << "Cell with name " << ref.get_cpp_obj()->name.c_str(); else - ostr << "deleted cell"; + ostr << "deleted Cell"; return ostr; } - struct Wire { - unsigned int id; + unsigned int hashidx_; Yosys::RTLIL::Wire* ref_obj; Wire(Yosys::RTLIL::Wire* ref) { - this->id = ref->hashidx_; + this->hashidx_ = ref->hashidx_; this->ref_obj = ref; } - + Yosys::RTLIL::Wire* get_cpp_obj() const { - Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->id); + Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->hashidx_); if(ret != NULL && ret == this->ref_obj) return ret; return NULL; } }; - std::ostream &operator<<(std::ostream &ostr, const Wire &wire) + std::ostream &operator<<(std::ostream &ostr, const Wire &ref) { - if(wire.get_cpp_obj() != NULL) - ostr << "Wire with name " << wire.get_cpp_obj()->name.c_str(); + if(ref.get_cpp_obj() != NULL) + ostr << "Wire with name " << ref.get_cpp_obj()->name.c_str(); else - ostr << "deleted wire"; + ostr << "deleted Wire"; return ostr; } + struct Memory + { + unsigned int hashidx_; + Yosys::RTLIL::Memory* ref_obj; + Memory(Yosys::RTLIL::Memory* ref) + { + this->hashidx_ = ref->hashidx_; + this->ref_obj = ref; + } + + Yosys::RTLIL::Memory* get_cpp_obj() const + { + Yosys::RTLIL::Memory* ret = Yosys::RTLIL::Memory::get_all_memorys()->at(this->hashidx_); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const Memory &ref) + { + if(ref.get_cpp_obj() != NULL) + ostr << "Memory with name " << ref.get_cpp_obj()->name.c_str(); + else + ostr << "deleted Memory"; + return ostr; + } struct Module { - unsigned int id; + unsigned int hashidx_; Yosys::RTLIL::Module* ref_obj; - Module(Yosys::RTLIL::Module* ref) + Module(Yosys::RTLIL::Module* ref = new Yosys::RTLIL::Module()) { - this->id = ref->hashidx_; + this->hashidx_ = ref->hashidx_; this->ref_obj = ref; } Yosys::RTLIL::Module* get_cpp_obj() const { - Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->id); + Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->hashidx_); if(ret != NULL && ret == this->ref_obj) return ret; return NULL; @@ -99,63 +531,491 @@ namespace YOSYS_PYTHON { boost::python::list get_cells() { - Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + Yosys::RTLIL::Module* cpp_obj = get_cpp_obj(); boost::python::list result; - if(cpp_mod == NULL) - return result; - for(auto &cell_it : cpp_mod->cells_) + if(cpp_obj == NULL) { - result.append(new Cell(cell_it.second)); + return result; + } + for(auto &mod_it : cpp_obj->cells_) + { + result.append(new Cell(mod_it.second)); } return result; } boost::python::list get_wires() { - Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + Yosys::RTLIL::Module* cpp_obj = get_cpp_obj(); boost::python::list result; - if(cpp_mod == NULL) - return result; - for(auto &wire_it : cpp_mod->wires_) + if(cpp_obj == NULL) { - result.append(new Wire(wire_it.second)); + return result; + } + for(auto &mod_it : cpp_obj->wires_) + { + result.append(new Wire(mod_it.second)); } return result; } void register_monitor(Monitor* const m); + + //WRAPPED void connect(const RTLIL::SigSig &conn); + void connect_SigSig(PyObject *conn); + + //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + void connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs); + + //WRAPPED void new_connections(const std::vector &new_conn); + void new_connections(boost::python::list *new_conn); + + //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; + void cloneInto(Module *new_mod); + + //WRAPPED void remove(const pool &wires); + void remove_pool_Wire(boost::python::list *wires); + + //WRAPPED void remove(RTLIL::Cell *cell); + void remove_Cell(Cell *cell); + + //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); + void rename_Wire_IdString(Wire *wire, IdString *new_name); + + //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); + void rename_Cell_IdString(Cell *cell, IdString *new_name); + + //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + void rename_IdString_IdString(IdString *old_name, IdString *new_name); + + //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); + void swap_names_Wire_Wire(Wire *w1, Wire *w2); + + //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + void swap_names_Cell_Cell(Cell *c1, Cell *c2); + + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); + IdString uniquify_IdString(IdString *name); + + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); + IdString uniquify_IdString_int(IdString *name, int index); + + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + Wire addWire_IdString_int(IdString *name, int width = 1); + + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + Wire addWire_IdString_Wire(IdString *name, Wire *other); + + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + Cell addCell_IdString_IdString(IdString *name, IdString *type); + + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + Cell addCell_IdString_Cell(IdString *name, Cell *other); + + //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + Cell addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed = false, bool b_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); + Cell addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src = ""); + + //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); + Cell addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src = ""); + + //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + Cell addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + Cell addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + Cell addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + Cell addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + Cell addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + Cell addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + Cell addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + Cell addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Not(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Pos(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Neg(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec LogicNot(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + SigSpec Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + SigSpec Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = ""); + + //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + SigBit BufGate(IdString *name, SigBit *sig_a, std::string src = ""); + + //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + SigBit NotGate(IdString *name, SigBit *sig_a, std::string src = ""); + + //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); + SigBit MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src = ""); + + //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + SigBit Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = ""); + + //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + SigBit Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = ""); + + //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + SigBit Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = ""); + + //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + SigBit Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Anyconst(IdString *name, int width = 1, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Anyseq(IdString *name, int width = 1, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Allconst(IdString *name, int width = 1, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Allseq(IdString *name, int width = 1, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); + SigSpec Initstate(IdString *name, std::string src = ""); }; - std::ostream &operator<<(std::ostream &ostr, const Module &module) + std::ostream &operator<<(std::ostream &ostr, const Module &ref) { - if(module.get_cpp_obj() != NULL) - ostr << "Module with name " << module.get_cpp_obj()->name.c_str(); + if(ref.get_cpp_obj() != NULL) + ostr << "Module with name " << ref.get_cpp_obj()->name.c_str(); else - ostr << "deleted module"; + ostr << "deleted Module"; return ostr; } - struct Design { - unsigned int id; + unsigned int hashidx_; Yosys::RTLIL::Design* ref_obj; - Design(unsigned int hashid) + Design(Yosys::RTLIL::Design* ref = new Yosys::RTLIL::Design()) { - this->id = hashid; - this->ref_obj = Yosys::RTLIL::Design::get_all_designs()->at(this->id); + this->hashidx_ = ref->hashidx_; + this->ref_obj = ref; } - Design() + Yosys::RTLIL::Design* get_cpp_obj() const { - Yosys::RTLIL::Design* new_design = new Yosys::RTLIL::Design(); - this->id = new_design->hashidx_; - this->ref_obj = new_design; - } - - Yosys::RTLIL::Design* get_cpp_obj() - { - Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->id); + Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->hashidx_); if(ret != NULL && ret == this->ref_obj) return ret; return NULL; @@ -163,13 +1023,13 @@ namespace YOSYS_PYTHON { boost::python::list get_modules() { - Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); + Yosys::RTLIL::Design* cpp_obj = get_cpp_obj(); boost::python::list result; - if(cpp_design == NULL) + if(cpp_obj == NULL) { return result; } - for(auto &mod_it : cpp_design->modules_) + for(auto &mod_it : cpp_obj->modules_) { result.append(new Module(mod_it.second)); } @@ -181,91 +1041,443 @@ namespace YOSYS_PYTHON { Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); if(cpp_design != NULL) Yosys::run_pass(command, cpp_design); + } void register_monitor(Monitor* const m); + + //WRAPPED RTLIL::Module *module(RTLIL::IdString name); + Module module(IdString *name); + + //WRAPPED bool has(RTLIL::IdString id) const { + bool has(IdString *id); + + //WRAPPED void add(RTLIL::Module *module); + void add(Module *module); + + //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); + Module addModule(IdString *name); + + //WRAPPED void remove(RTLIL::Module *module); + void remove(Module *module); + + //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); + void rename(Module *module, IdString *new_name); + + //WRAPPED void scratchpad_unset(std::string varname); + void scratchpad_unset(std::string varname); + + //WRAPPED void scratchpad_set_int(std::string varname, int value); + void scratchpad_set_int(std::string varname, int value); + + //WRAPPED void scratchpad_set_bool(std::string varname, bool value); + void scratchpad_set_bool(std::string varname, bool value); + + //WRAPPED void scratchpad_set_string(std::string varname, std::string value); + void scratchpad_set_string(std::string varname, std::string value); + + //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; + int scratchpad_get_int(std::string varname, int default_value = 0); + + //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; + bool scratchpad_get_bool(std::string varname, bool default_value = false); + + //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()); + + //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; + bool selected_module_IdString(IdString *mod_name); + + //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; + bool selected_whole_module_IdString(IdString *mod_name); + + //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + bool selected_member(IdString *mod_name, IdString *memb_name); + + //WRAPPED bool selected_module(RTLIL::Module *mod) const; + bool selected_module_Module(Module *mod); + + //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; + bool selected_whole_module_Module(Module *mod); }; - struct Monitor : public Yosys::RTLIL::Monitor + std::ostream &operator<<(std::ostream &ostr, const Design &ref) { + if(ref.get_cpp_obj() != NULL) + ostr << "Design with identifier " << ref.hashidx_; + else + ostr << "deleted Design"; + return ostr; + } - virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_add(new Module(module)); - } - - virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_del(new Module(module)); - } - - virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE - { - //@TODO: Implement once necessary classes are wrapped - } - - virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE - { - //@TODO: Implement once necessary classes are wrapped - } - - virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE - { - //@TODO: Implement once necessary classes are wrapped - } - - virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_blackout(new Module(module)); - } - - virtual void py_notify_module_add(Module*){}; - virtual void py_notify_module_del(Module*){}; - virtual void py_notify_blackout(Module*){}; - - }; - - struct MonitorWrap : Monitor, boost::python::wrapper + //WRAPPED static inline std::string escape_id(std::string str) { + inline std::string escape_id(std::string str) { - void py_notify_module_add(Module* m) - { - if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) - py_notify_module_add(m); - else - Monitor::py_notify_module_add(m); - } + return Yosys::RTLIL::escape_id(str); + } - void default_py_notify_module_add(Module* m) - { - this->Monitor::py_notify_module_add(m); - } + //WRAPPED static inline std::string unescape_id(std::string str) { + inline std::string unescape_id_std_string(std::string str) + { + return Yosys::RTLIL::unescape_id(str); + } - void py_notify_module_del(Module* m) - { - if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) - py_notify_module_del(m); - else - Monitor::py_notify_module_del(m); - } + //WRAPPED static inline std::string unescape_id(RTLIL::IdString str) { + inline std::string unescape_id_IdString(IdString *str) + { + return Yosys::RTLIL::unescape_id(*str->get_cpp_obj()); + } - void default_py_notify_module_del(Module* m) - { - this->Monitor::py_notify_module_del(m); - } + //WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } - void py_notify_blackout(Module* m) - { - if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) - py_notify_blackout(m); - else - Monitor::py_notify_blackout(m); - } + //WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } - void default_py_notify_blackout(Module* m) - { - this->Monitor::py_notify_blackout(m); - } - }; + //WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_bool(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_bool(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_logic_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_logic_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_logic_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_logic_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_logic_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_logic_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_shl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_shl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_shr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_shr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_sshl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_sshl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_sshr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_sshr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_shift(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_shift(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_shiftx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_shiftx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_lt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_lt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_le(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_le(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_eq(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_eq(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_ne(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_ne(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_eqx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_eqx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_nex(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_nex(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_ge(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_ge(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_gt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_gt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_add(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_add(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_sub(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_sub(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_mul(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_mul(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_div(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_div(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_mod(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_mod(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_pow(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_pow(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_pos(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_pos(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_neg(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + struct Monitor : public Yosys::RTLIL::Monitor + { + + virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_add(new Module(module)); + } + + virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_del(new Module(module)); + } + + virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE + { + Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); + Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); + py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig)); + delete tmp_port; + delete tmp_old_sig; + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE + { + Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); + Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); + py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second))); + delete first; + delete second; + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + { + boost::python::list sigsig_list; + for(auto sigsig : sigsig_vec) + sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second))); + py_notify_connect_list(new Module(module), sigsig_list); + } + + virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_blackout(new Module(module)); + } + + virtual void py_notify_module_add(Module*){}; + virtual void py_notify_module_del(Module*){}; + virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){}; + virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; + virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; + virtual void py_notify_blackout(Module*){}; + }; + + struct MonitorWrap : Monitor, boost::python::wrapper + { + void py_notify_module_add(Module* m) + { + if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) + py_notify_module_add(m); + else + Monitor::py_notify_module_add(m); + } + + void default_py_notify_module_add(Module* m) + { + this->Monitor::py_notify_module_add(m); + } + + void py_notify_module_del(Module* m) + { + if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) + py_notify_module_del(m); + else + Monitor::py_notify_module_del(m); + } + + void default_py_notify_module_del(Module* m) + { + this->Monitor::py_notify_module_del(m); + } + + void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + { + if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) + py_notify_connect_cell(cell, port, old_sig, sig); + else + Monitor::py_notify_connect_cell(cell, port, old_sig, sig); + } + + void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + { + this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); + } + + void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + { + if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) + py_notify_connect_tuple(module, sigsig); + else + Monitor::py_notify_connect_tuple(module, sigsig); + } + + void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + { + this->Monitor::py_notify_connect_tuple(module, sigsig); + } + + void py_notify_connect_list(Module* module, boost::python::list sigsig_list) + { + if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) + py_notify_connect_list(module, sigsig_list); + else + Monitor::py_notify_connect_list(module, sigsig_list); + } + + void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list) + { + this->Monitor::py_notify_connect_list(module, sigsig_list); + } + + void py_notify_blackout(Module* m) + { + if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) + py_notify_blackout(m); + else + Monitor::py_notify_blackout(m); + } + + void default_py_notify_blackout(Module* m) + { + this->Monitor::py_notify_blackout(m); + } + }; + + void Module::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Module* cpp_module = this->get_cpp_obj(); + if(cpp_module == NULL) + return; + cpp_module->monitors.insert(m); + } void Design::register_monitor(Monitor* const m) { @@ -275,28 +1487,1239 @@ namespace YOSYS_PYTHON { cpp_design->monitors.insert(m); } - void Module::register_monitor(Monitor* const m) + //WRAPPED static inline int get_reference(int idx) + inline int IdString::get_reference(int idx) { - Yosys::RTLIL::Module* cpp_design = this->get_cpp_obj(); - if(cpp_design == NULL) - return; - cpp_design->monitors.insert(m); + return Yosys::RTLIL::IdString::get_reference(idx); } - std::ostream &operator<<(std::ostream &ostr, const Design &design) + //WRAPPED static inline void put_reference(int idx) + inline void IdString::put_reference(int idx) { - ostr << "Design with id " << design.id; - return ostr; + Yosys::RTLIL::IdString::put_reference(idx); } - unsigned int get_active_design_id() + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } + bool IdString::in_IdString(IdString *rhs) { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design != NULL) + return this->get_cpp_obj()->in(*rhs->get_cpp_obj()); + } + + //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } + bool IdString::in_std_string(std::string rhs) + { + return this->get_cpp_obj()->in(rhs); + } + + //WRAPPED int as_int(bool is_signed = false) const; + int Const::as_int(bool is_signed) + { + return this->get_cpp_obj()->as_int(is_signed); + } + + //WRAPPED static Const from_string(std::string str); + Const Const::from_string(std::string str) + { + return Const(Yosys::RTLIL::Const::from_string(str)); + } + + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { + inline Const Const::extract(int offset, int len, State padding) + { + return Const(this->get_cpp_obj()->extract(offset, len, padding)); + } + + //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; + SigChunk SigChunk::extract(int offset, int length) + { + return SigChunk(this->get_cpp_obj()->extract(offset, length)); + } + + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); + void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with) + { + this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj()); + } + + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; + void SigSpec::replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other) + { + this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj(), other->get_cpp_obj()); + } + + //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); + void SigSpec::replace_int_SigSpec(int offset, SigSpec *with) + { + this->get_cpp_obj()->replace(offset, *with->get_cpp_obj()); + } + + //WRAPPED void remove(const RTLIL::SigSpec &pattern); + void SigSpec::remove_SigSpec(SigSpec *pattern) + { + this->get_cpp_obj()->remove(*pattern->get_cpp_obj()); + } + + //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; + void SigSpec::remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) + { + this->get_cpp_obj()->remove(*pattern->get_cpp_obj(), other->get_cpp_obj()); + } + + //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); + void SigSpec::remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) + { + this->get_cpp_obj()->remove2(*pattern->get_cpp_obj(), other->get_cpp_obj()); + } + + //WRAPPED void remove(const pool &pattern); + void SigSpec::remove_pool_SigBit(boost::python::list *pattern) + { + pool pattern_; + for(int i = 0; i < len(*pattern); ++i) { - return active_design->hashidx_; } - return 0; + this->get_cpp_obj()->remove(pattern_); + } + + //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; + void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + { + pool pattern_; + for(int i = 0; i < len(*pattern); ++i) + { + } + this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj()); + } + + //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); + void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + { + pool pattern_; + for(int i = 0; i < len(*pattern); ++i) + { + } + this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj()); + } + + //WRAPPED void remove(int offset, int length = 1); + void SigSpec::remove_int_int(int offset, int length) + { + this->get_cpp_obj()->remove(offset, length); + } + + //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; + SigSpec SigSpec::extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) + { + return SigSpec(this->get_cpp_obj()->extract(*pattern->get_cpp_obj(), other->get_cpp_obj())); + } + + //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; + SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + { + pool pattern_; + for(int i = 0; i < len(*pattern); ++i) + { + } + return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj())); + } + + //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; + SigSpec SigSpec::extract_int_int(int offset, int length) + { + return SigSpec(this->get_cpp_obj()->extract(offset, length)); + } + + //WRAPPED void append(const RTLIL::SigSpec &signal); + void SigSpec::append(SigSpec *signal) + { + this->get_cpp_obj()->append(*signal->get_cpp_obj()); + } + + //WRAPPED void append_bit(const RTLIL::SigBit &bit); + void SigSpec::append_bit(SigBit *bit) + { + this->get_cpp_obj()->append_bit(*bit->get_cpp_obj()); + } + + //WRAPPED void extend_u0(int width, bool is_signed = false); + void SigSpec::extend_u0(int width, bool is_signed) + { + this->get_cpp_obj()->extend_u0(width, is_signed); + } + + //WRAPPED RTLIL::SigSpec repeat(int num) const; + SigSpec SigSpec::repeat(int num) + { + return SigSpec(this->get_cpp_obj()->repeat(num)); + } + + //WRAPPED int as_int(bool is_signed = false) const; + int SigSpec::as_int(bool is_signed) + { + return this->get_cpp_obj()->as_int(is_signed); + } + + //WRAPPED bool match(std::string pattern) const; + bool SigSpec::match(std::string pattern) + { + return this->get_cpp_obj()->match(pattern); + } + + //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + bool SigSpec::parse(SigSpec *sig, Module *module, std::string str) + { + return Yosys::RTLIL::SigSpec::parse(*sig->get_cpp_obj(), module->get_cpp_obj(), str); + } + + //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); + bool SigSpec::parse_sel(SigSpec *sig, Design *design, Module *module, std::string str) + { + return Yosys::RTLIL::SigSpec::parse_sel(*sig->get_cpp_obj(), design->get_cpp_obj(), module->get_cpp_obj(), str); + } + + //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + bool SigSpec::parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str) + { + return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); + } + + //WRAPPED bool hasPort(RTLIL::IdString portname) const; + bool Cell::hasPort(IdString *portname) + { + return this->get_cpp_obj()->hasPort(*portname->get_cpp_obj()); + } + + //WRAPPED void unsetPort(RTLIL::IdString portname); + void Cell::unsetPort(IdString *portname) + { + this->get_cpp_obj()->unsetPort(*portname->get_cpp_obj()); + } + + //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); + void Cell::setPort(IdString *portname, SigSpec *signal) + { + this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj()); + } + + //WRAPPED bool input(RTLIL::IdString portname) const; + bool Cell::input(IdString *portname) + { + return this->get_cpp_obj()->input(*portname->get_cpp_obj()); + } + + //WRAPPED bool output(RTLIL::IdString portname) const; + bool Cell::output(IdString *portname) + { + return this->get_cpp_obj()->output(*portname->get_cpp_obj()); + } + + //WRAPPED bool hasParam(RTLIL::IdString paramname) const; + bool Cell::hasParam(IdString *paramname) + { + return this->get_cpp_obj()->hasParam(*paramname->get_cpp_obj()); + } + + //WRAPPED void unsetParam(RTLIL::IdString paramname); + void Cell::unsetParam(IdString *paramname) + { + this->get_cpp_obj()->unsetParam(*paramname->get_cpp_obj()); + } + + //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); + void Cell::setParam(IdString *paramname, Const *value) + { + this->get_cpp_obj()->setParam(*paramname->get_cpp_obj(), *value->get_cpp_obj()); + } + + //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + void Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) + { + this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed); + } + + //WRAPPED void connect(const RTLIL::SigSig &conn); + void Module::connect_SigSig(PyObject* conn) + { + if(!PyTuple_Check(conn) or PyTuple_Size(conn) != 2) + throw std::logic_error("Tuple of two SigSpecs required"); + SigSpec conn_sp0 = boost::python::extract(PyTuple_GetItem(conn, 0)); + SigSpec conn_sp1 = boost::python::extract(PyTuple_GetItem(conn, 1)); + Yosys::RTLIL::SigSig conn_(conn_sp0.get_cpp_obj(), conn_sp1.get_cpp_obj()); + this->get_cpp_obj()->connect(conn_); + } + + //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + void Module::connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs) + { + this->get_cpp_obj()->connect(*lhs->get_cpp_obj(), *rhs->get_cpp_obj()); + } + + //WRAPPED void new_connections(const std::vector &new_conn); + void Module::new_connections(boost::python::list *new_conn) + { + std::vector new_conn_; + for(int i = 0; i < len(*new_conn); ++i) + { + } + this->get_cpp_obj()->new_connections(new_conn_); + } + + //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; + void Module::cloneInto(Module *new_mod) + { + this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj()); + } + + //WRAPPED void remove(const pool &wires); + void Module::remove_pool_Wire(boost::python::list *wires) + { + pool wires_; + for(int i = 0; i < len(*wires); ++i) + { + } + this->get_cpp_obj()->remove(wires_); + } + + //WRAPPED void remove(RTLIL::Cell *cell); + void Module::remove_Cell(Cell *cell) + { + this->get_cpp_obj()->remove(cell->get_cpp_obj()); + } + + //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); + void Module::rename_Wire_IdString(Wire *wire, IdString *new_name) + { + this->get_cpp_obj()->rename(wire->get_cpp_obj(), *new_name->get_cpp_obj()); + } + + //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); + void Module::rename_Cell_IdString(Cell *cell, IdString *new_name) + { + this->get_cpp_obj()->rename(cell->get_cpp_obj(), *new_name->get_cpp_obj()); + } + + //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + void Module::rename_IdString_IdString(IdString *old_name, IdString *new_name) + { + this->get_cpp_obj()->rename(*old_name->get_cpp_obj(), *new_name->get_cpp_obj()); + } + + //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); + void Module::swap_names_Wire_Wire(Wire *w1, Wire *w2) + { + this->get_cpp_obj()->swap_names(w1->get_cpp_obj(), w2->get_cpp_obj()); + } + + //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + void Module::swap_names_Cell_Cell(Cell *c1, Cell *c2) + { + this->get_cpp_obj()->swap_names(c1->get_cpp_obj(), c2->get_cpp_obj()); + } + + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); + IdString Module::uniquify_IdString(IdString *name) + { + return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj())); + } + + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); + IdString Module::uniquify_IdString_int(IdString *name, int index) + { + return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj(), index)); + } + + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + Wire Module::addWire_IdString_int(IdString *name, int width) + { + return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), width)); + } + + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + Wire Module::addWire_IdString_Wire(IdString *name, Wire *other) + { + return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), other->get_cpp_obj())); + } + + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + Cell Module::addCell_IdString_IdString(IdString *name, IdString *type) + { + return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), *type->get_cpp_obj())); + } + + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + Cell Module::addCell_IdString_Cell(IdString *name, Cell *other) + { + return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), other->get_cpp_obj())); + } + + //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addPos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addNeg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addShl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addShr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addSshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addSshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addShift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addShiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addEq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addNe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addEqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addNex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addGe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addGt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addAdd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addSub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addMul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addDiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addMod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + Cell Module::addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed, bool b_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addPow(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), a_signed, b_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addMux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addPmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); + Cell Module::addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src) + { + return Cell(this->get_cpp_obj()->addSlice(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *offset->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addConcat(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); + Cell Module::addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src) + { + return Cell(this->get_cpp_obj()->addLut(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *lut->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addTribuf(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addAssert(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addAssume(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addLive(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addFair(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addCover(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addEquiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell Module::addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addSr(*name->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_q->get_cpp_obj(), set_polarity, clr_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + Cell Module::addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) + { + return Cell(this->get_cpp_obj()->addFf(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + Cell Module::addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + Cell Module::addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addBufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addNotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addAndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addNandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addOrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addNorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addXorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addXnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addAndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addOrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addMuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addAoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addOai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addAoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addOai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + Cell Module::addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) + { + return Cell(this->get_cpp_obj()->addFfGate(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + Cell Module::addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + Cell Module::addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); + } + + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Not(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Pos(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Pos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Neg(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Neg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->And(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Or(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Xor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Xnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Shl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Shr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Sshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Sshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Shift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Shiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Lt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Le(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Eq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Ne(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Eqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Nex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Ge(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Gt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Add(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Sub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Mul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Div(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Mod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::LogicNot(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->LogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->LogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->LogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + SigSpec Module::Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) + { + return SigSpec(this->get_cpp_obj()->Mux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + SigSpec Module::Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) + { + return SigSpec(this->get_cpp_obj()->Pmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + SigBit Module::BufGate(IdString *name, SigBit *sig_a, std::string src) + { + return SigBit(this->get_cpp_obj()->BufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + SigBit Module::NotGate(IdString *name, SigBit *sig_a, std::string src) + { + return SigBit(this->get_cpp_obj()->NotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->AndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->NandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->OrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->NorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->XorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->XnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->AndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->OrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); + SigBit Module::MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src) + { + return SigBit(this->get_cpp_obj()->MuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + SigBit Module::Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) + { + return SigBit(this->get_cpp_obj()->Aoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + SigBit Module::Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) + { + return SigBit(this->get_cpp_obj()->Oai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + SigBit Module::Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) + { + return SigBit(this->get_cpp_obj()->Aoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + SigBit Module::Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) + { + return SigBit(this->get_cpp_obj()->Oai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Module::Anyconst(IdString *name, int width, std::string src) + { + return SigSpec(this->get_cpp_obj()->Anyconst(*name->get_cpp_obj(), width, src)); + } + + //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Module::Anyseq(IdString *name, int width, std::string src) + { + return SigSpec(this->get_cpp_obj()->Anyseq(*name->get_cpp_obj(), width, src)); + } + + //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Module::Allconst(IdString *name, int width, std::string src) + { + return SigSpec(this->get_cpp_obj()->Allconst(*name->get_cpp_obj(), width, src)); + } + + //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Module::Allseq(IdString *name, int width, std::string src) + { + return SigSpec(this->get_cpp_obj()->Allseq(*name->get_cpp_obj(), width, src)); + } + + //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); + SigSpec Module::Initstate(IdString *name, std::string src) + { + return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Module *module(RTLIL::IdString name); + Module Design::module(IdString *name) + { + return Module(this->get_cpp_obj()->module(*name->get_cpp_obj())); + } + + //WRAPPED bool has(RTLIL::IdString id) const { + bool Design::has(IdString *id) + { + return this->get_cpp_obj()->has(*id->get_cpp_obj()); + } + + //WRAPPED void add(RTLIL::Module *module); + void Design::add(Module *module) + { + this->get_cpp_obj()->add(module->get_cpp_obj()); + } + + //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); + Module Design::addModule(IdString *name) + { + return Module(this->get_cpp_obj()->addModule(*name->get_cpp_obj())); + } + + //WRAPPED void remove(RTLIL::Module *module); + void Design::remove(Module *module) + { + this->get_cpp_obj()->remove(module->get_cpp_obj()); + } + + //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); + void Design::rename(Module *module, IdString *new_name) + { + this->get_cpp_obj()->rename(module->get_cpp_obj(), *new_name->get_cpp_obj()); + } + + //WRAPPED void scratchpad_unset(std::string varname); + void Design::scratchpad_unset(std::string varname) + { + this->get_cpp_obj()->scratchpad_unset(varname); + } + + //WRAPPED void scratchpad_set_int(std::string varname, int value); + void Design::scratchpad_set_int(std::string varname, int value) + { + this->get_cpp_obj()->scratchpad_set_int(varname, value); + } + + //WRAPPED void scratchpad_set_bool(std::string varname, bool value); + void Design::scratchpad_set_bool(std::string varname, bool value) + { + this->get_cpp_obj()->scratchpad_set_bool(varname, value); + } + + //WRAPPED void scratchpad_set_string(std::string varname, std::string value); + void Design::scratchpad_set_string(std::string varname, std::string value) + { + this->get_cpp_obj()->scratchpad_set_string(varname, value); + } + + //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; + int Design::scratchpad_get_int(std::string varname, int default_value) + { + return this->get_cpp_obj()->scratchpad_get_int(varname, default_value); + } + + //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; + bool Design::scratchpad_get_bool(std::string varname, bool default_value) + { + return this->get_cpp_obj()->scratchpad_get_bool(varname, default_value); + } + + //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + std::string Design::scratchpad_get_string(std::string varname, std::string default_value) + { + return this->get_cpp_obj()->scratchpad_get_string(varname, default_value); + } + + //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; + bool Design::selected_module_IdString(IdString *mod_name) + { + return this->get_cpp_obj()->selected_module(*mod_name->get_cpp_obj()); + } + + //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; + bool Design::selected_whole_module_IdString(IdString *mod_name) + { + return this->get_cpp_obj()->selected_whole_module(*mod_name->get_cpp_obj()); + } + + //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + bool Design::selected_member(IdString *mod_name, IdString *memb_name) + { + return this->get_cpp_obj()->selected_member(*mod_name->get_cpp_obj(), *memb_name->get_cpp_obj()); + } + + //WRAPPED bool selected_module(RTLIL::Module *mod) const; + bool Design::selected_module_Module(Module *mod) + { + return this->get_cpp_obj()->selected_module(mod->get_cpp_obj()); + } + + //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; + bool Design::selected_whole_module_Module(Module *mod) + { + return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj()); } struct Initializer @@ -319,29 +2742,133 @@ namespace YOSYS_PYTHON { { using namespace boost::python; + enum_("State") + .value("S0",Yosys::RTLIL::S0) + .value("S1",Yosys::RTLIL::S1) + .value("Sx",Yosys::RTLIL::Sx) + .value("Sz",Yosys::RTLIL::Sz) + .value("Sa",Yosys::RTLIL::Sa) + .value("Sm",Yosys::RTLIL::Sm) + ; + + enum_("SyncType") + .value("ST0",Yosys::RTLIL::ST0) + .value("ST1",Yosys::RTLIL::ST1) + .value("STp",Yosys::RTLIL::STp) + .value("STn",Yosys::RTLIL::STn) + .value("STe",Yosys::RTLIL::STe) + .value("STa",Yosys::RTLIL::STa) + .value("STg",Yosys::RTLIL::STg) + .value("STi",Yosys::RTLIL::STi) + ; + + enum_("ConstFlags") + .value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE) + .value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING) + .value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED) + .value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL) + ; + + class_("Monitor") + .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) + .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) + .def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell) + .def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple) + .def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list) + .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + ; + class_("Initializer"); scope().attr("_hidden") = new Initializer(); - class_("Design", init()) + class_("IdString") + .def(init()) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def(init<>()) - .def("get_modules", &Design::get_modules) - .def("run",&Design::run) - .def("register_monitor", &Design::register_monitor) + .def("get_reference", &IdString::get_reference) + .def("put_reference", &IdString::put_reference) + .def("in_IdString", &IdString::in_IdString) + .def("in_std_string", &IdString::in_std_string) ; - class_("Module", no_init) + class_("Const") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_cells", &Module::get_cells) - .def("get_wires", &Module::get_wires) - .def("register_monitor", &Module::register_monitor) + .def("as_int", &Const::as_int) + .def("from_string", &Const::from_string) + .def("extract", &Const::extract) + ; + + class_("CaseRule") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("SwitchRule") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("SyncRule") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("Process") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("SigChunk") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("extract", &SigChunk::extract) + ; + + class_("SigBit") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("SigSpec") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec) + .def("replace_SigSpec_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec_SigSpec) + .def("replace_int_SigSpec", &SigSpec::replace_int_SigSpec) + .def("remove_SigSpec", &SigSpec::remove_SigSpec) + .def("remove_SigSpec_SigSpec", &SigSpec::remove_SigSpec_SigSpec) + .def("remove2_SigSpec_SigSpec", &SigSpec::remove2_SigSpec_SigSpec) + .def("remove_pool_SigBit", &SigSpec::remove_pool_SigBit) + .def("remove_pool_SigBit_SigSpec", &SigSpec::remove_pool_SigBit_SigSpec) + .def("remove2_pool_SigBit_SigSpec", &SigSpec::remove2_pool_SigBit_SigSpec) + .def("remove_int_int", &SigSpec::remove_int_int) + .def("extract_SigSpec_SigSpec", &SigSpec::extract_SigSpec_SigSpec) + .def("extract_pool_SigBit_SigSpec", &SigSpec::extract_pool_SigBit_SigSpec) + .def("extract_int_int", &SigSpec::extract_int_int) + .def("append", &SigSpec::append) + .def("append_bit", &SigSpec::append_bit) + .def("extend_u0", &SigSpec::extend_u0) + .def("repeat", &SigSpec::repeat) + .def("as_int", &SigSpec::as_int) + .def("match", &SigSpec::match) + .def("parse", &SigSpec::parse) + .def("parse_sel", &SigSpec::parse_sel) + .def("parse_rhs", &SigSpec::parse_rhs) ; class_("Cell", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hasPort", &Cell::hasPort) + .def("unsetPort", &Cell::unsetPort) + .def("setPort", &Cell::setPort) + .def("input", &Cell::input) + .def("output", &Cell::output) + .def("hasParam", &Cell::hasParam) + .def("unsetParam", &Cell::unsetParam) + .def("setParam", &Cell::setParam) + .def("fixup_parameters", &Cell::fixup_parameters) ; class_("Wire", no_init) @@ -349,14 +2876,230 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; - class_("Monitor") - .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) - .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) - .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + class_("Memory", no_init) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; + class_("Module") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_cells", &Module::get_cells) + .def("get_wires", &Module::get_wires) + .def("register_monitor", &Module::register_monitor) + .def("connect_SigSig", &Module::connect_SigSig) + .def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec) + .def("new_connections", &Module::new_connections) + .def("cloneInto", &Module::cloneInto) + .def("remove_pool_Wire", &Module::remove_pool_Wire) + .def("remove_Cell", &Module::remove_Cell) + .def("rename_Wire_IdString", &Module::rename_Wire_IdString) + .def("rename_Cell_IdString", &Module::rename_Cell_IdString) + .def("rename_IdString_IdString", &Module::rename_IdString_IdString) + .def("swap_names_Wire_Wire", &Module::swap_names_Wire_Wire) + .def("swap_names_Cell_Cell", &Module::swap_names_Cell_Cell) + .def("uniquify_IdString", &Module::uniquify_IdString) + .def("uniquify_IdString_int", &Module::uniquify_IdString_int) + .def("addWire_IdString_int", &Module::addWire_IdString_int) + .def("addWire_IdString_Wire", &Module::addWire_IdString_Wire) + .def("addCell_IdString_IdString", &Module::addCell_IdString_IdString) + .def("addCell_IdString_Cell", &Module::addCell_IdString_Cell) + .def("addNot", &Module::addNot) + .def("addPos", &Module::addPos) + .def("addNeg", &Module::addNeg) + .def("addAnd", &Module::addAnd) + .def("addOr", &Module::addOr) + .def("addXor", &Module::addXor) + .def("addXnor", &Module::addXnor) + .def("addReduceAnd", &Module::addReduceAnd) + .def("addReduceOr", &Module::addReduceOr) + .def("addReduceXor", &Module::addReduceXor) + .def("addReduceXnor", &Module::addReduceXnor) + .def("addReduceBool", &Module::addReduceBool) + .def("addShl", &Module::addShl) + .def("addShr", &Module::addShr) + .def("addSshl", &Module::addSshl) + .def("addSshr", &Module::addSshr) + .def("addShift", &Module::addShift) + .def("addShiftx", &Module::addShiftx) + .def("addLt", &Module::addLt) + .def("addLe", &Module::addLe) + .def("addEq", &Module::addEq) + .def("addNe", &Module::addNe) + .def("addEqx", &Module::addEqx) + .def("addNex", &Module::addNex) + .def("addGe", &Module::addGe) + .def("addGt", &Module::addGt) + .def("addAdd", &Module::addAdd) + .def("addSub", &Module::addSub) + .def("addMul", &Module::addMul) + .def("addDiv", &Module::addDiv) + .def("addMod", &Module::addMod) + .def("addPow", &Module::addPow) + .def("addLogicNot", &Module::addLogicNot) + .def("addLogicAnd", &Module::addLogicAnd) + .def("addLogicOr", &Module::addLogicOr) + .def("addMux", &Module::addMux) + .def("addPmux", &Module::addPmux) + .def("addSlice", &Module::addSlice) + .def("addConcat", &Module::addConcat) + .def("addLut", &Module::addLut) + .def("addTribuf", &Module::addTribuf) + .def("addAssert", &Module::addAssert) + .def("addAssume", &Module::addAssume) + .def("addLive", &Module::addLive) + .def("addFair", &Module::addFair) + .def("addCover", &Module::addCover) + .def("addEquiv", &Module::addEquiv) + .def("addSr", &Module::addSr) + .def("addFf", &Module::addFf) + .def("addDff", &Module::addDff) + .def("addDffe", &Module::addDffe) + .def("addDlatch", &Module::addDlatch) + .def("addBufGate", &Module::addBufGate) + .def("addNotGate", &Module::addNotGate) + .def("addAndGate", &Module::addAndGate) + .def("addNandGate", &Module::addNandGate) + .def("addOrGate", &Module::addOrGate) + .def("addNorGate", &Module::addNorGate) + .def("addXorGate", &Module::addXorGate) + .def("addXnorGate", &Module::addXnorGate) + .def("addAndnotGate", &Module::addAndnotGate) + .def("addOrnotGate", &Module::addOrnotGate) + .def("addMuxGate", &Module::addMuxGate) + .def("addAoi3Gate", &Module::addAoi3Gate) + .def("addOai3Gate", &Module::addOai3Gate) + .def("addAoi4Gate", &Module::addAoi4Gate) + .def("addOai4Gate", &Module::addOai4Gate) + .def("addFfGate", &Module::addFfGate) + .def("addDffGate", &Module::addDffGate) + .def("addDffeGate", &Module::addDffeGate) + .def("addDlatchGate", &Module::addDlatchGate) + .def("Not", &Module::Not) + .def("Pos", &Module::Pos) + .def("Neg", &Module::Neg) + .def("And", &Module::And) + .def("Or", &Module::Or) + .def("Xor", &Module::Xor) + .def("Xnor", &Module::Xnor) + .def("ReduceAnd", &Module::ReduceAnd) + .def("ReduceOr", &Module::ReduceOr) + .def("ReduceXor", &Module::ReduceXor) + .def("ReduceXnor", &Module::ReduceXnor) + .def("ReduceBool", &Module::ReduceBool) + .def("Shl", &Module::Shl) + .def("Shr", &Module::Shr) + .def("Sshl", &Module::Sshl) + .def("Sshr", &Module::Sshr) + .def("Shift", &Module::Shift) + .def("Shiftx", &Module::Shiftx) + .def("Lt", &Module::Lt) + .def("Le", &Module::Le) + .def("Eq", &Module::Eq) + .def("Ne", &Module::Ne) + .def("Eqx", &Module::Eqx) + .def("Nex", &Module::Nex) + .def("Ge", &Module::Ge) + .def("Gt", &Module::Gt) + .def("Add", &Module::Add) + .def("Sub", &Module::Sub) + .def("Mul", &Module::Mul) + .def("Div", &Module::Div) + .def("Mod", &Module::Mod) + .def("LogicNot", &Module::LogicNot) + .def("LogicAnd", &Module::LogicAnd) + .def("LogicOr", &Module::LogicOr) + .def("Mux", &Module::Mux) + .def("Pmux", &Module::Pmux) + .def("BufGate", &Module::BufGate) + .def("NotGate", &Module::NotGate) + .def("AndGate", &Module::AndGate) + .def("NandGate", &Module::NandGate) + .def("OrGate", &Module::OrGate) + .def("NorGate", &Module::NorGate) + .def("XorGate", &Module::XorGate) + .def("XnorGate", &Module::XnorGate) + .def("AndnotGate", &Module::AndnotGate) + .def("OrnotGate", &Module::OrnotGate) + .def("MuxGate", &Module::MuxGate) + .def("Aoi3Gate", &Module::Aoi3Gate) + .def("Oai3Gate", &Module::Oai3Gate) + .def("Aoi4Gate", &Module::Aoi4Gate) + .def("Oai4Gate", &Module::Oai4Gate) + .def("Anyconst", &Module::Anyconst) + .def("Anyseq", &Module::Anyseq) + .def("Allconst", &Module::Allconst) + .def("Allseq", &Module::Allseq) + .def("Initstate", &Module::Initstate) + ; + + class_("Design") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_modules", &Design::get_modules) + .def("run", &Design::run) + .def("register_monitor", &Design::register_monitor) + .def("module", &Design::module) + .def("has", &Design::has) + .def("add", &Design::add) + .def("addModule", &Design::addModule) + .def("remove", &Design::remove) + .def("rename", &Design::rename) + .def("scratchpad_unset", &Design::scratchpad_unset) + .def("scratchpad_set_int", &Design::scratchpad_set_int) + .def("scratchpad_set_bool", &Design::scratchpad_set_bool) + .def("scratchpad_set_string", &Design::scratchpad_set_string) + .def("scratchpad_get_int", &Design::scratchpad_get_int) + .def("scratchpad_get_bool", &Design::scratchpad_get_bool) + .def("scratchpad_get_string", &Design::scratchpad_get_string) + .def("selected_module_IdString", &Design::selected_module_IdString) + .def("selected_whole_module_IdString", &Design::selected_whole_module_IdString) + .def("selected_member", &Design::selected_member) + .def("selected_module_Module", &Design::selected_module_Module) + .def("selected_whole_module_Module", &Design::selected_whole_module_Module) + ; + + def("escape_id", escape_id); + def("unescape_id_std_string", unescape_id_std_string); + def("unescape_id_IdString", unescape_id_IdString); + def("const_not", const_not); + def("const_and", const_and); + def("const_or", const_or); + def("const_xor", const_xor); + def("const_xnor", const_xnor); + def("const_reduce_and", const_reduce_and); + def("const_reduce_or", const_reduce_or); + def("const_reduce_xor", const_reduce_xor); + def("const_reduce_xnor", const_reduce_xnor); + def("const_reduce_bool", const_reduce_bool); + def("const_logic_not", const_logic_not); + def("const_logic_and", const_logic_and); + def("const_logic_or", const_logic_or); + def("const_shl", const_shl); + def("const_shr", const_shr); + def("const_sshl", const_sshl); + def("const_sshr", const_sshr); + def("const_shift", const_shift); + def("const_shiftx", const_shiftx); + def("const_lt", const_lt); + def("const_le", const_le); + def("const_eq", const_eq); + def("const_ne", const_ne); + def("const_eqx", const_eqx); + def("const_nex", const_nex); + def("const_ge", const_ge); + def("const_gt", const_gt); + def("const_add", const_add); + def("const_sub", const_sub); + def("const_mul", const_mul); + def("const_div", const_div); + def("const_mod", const_mod); + def("const_pow", const_pow); + def("const_pos", const_pos); + def("const_neg", const_neg); + def("run",run); - def("get_active_design_id",get_active_design_id); + } } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6e8b51682..bcda931d2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -74,6 +74,13 @@ RTLIL::Const::Const(const std::vector &bits) this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0); } +RTLIL::Const::Const(const RTLIL::Const &c) +{ + flags = c.flags; + for (auto b : c.bits) + this->bits.push_back(b); +} + bool RTLIL::Const::operator <(const RTLIL::Const &other) const { if (bits.size() != other.bits.size()) @@ -2247,6 +2254,9 @@ RTLIL::Memory::Memory() width = 1; start_offset = 0; size = 0; +#ifdef WITH_PYTHON + RTLIL::Memory::get_all_memorys()->insert(std::pair(hashidx_, this)); +#endif } RTLIL::Cell::Cell() : module(nullptr) @@ -2534,6 +2544,14 @@ RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit) width = 1; } +RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data) +{ + wire = sigchunk.wire; + data = sigchunk.data; + width = sigchunk.width; + offset = sigchunk.offset; +} + RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const { RTLIL::SigChunk ret; @@ -3907,6 +3925,18 @@ RTLIL::Process *RTLIL::Process::clone() const return new_proc; } +RTLIL::Memory::~Memory() +{ +#ifdef WITH_PYTHON + RTLIL::Memory::get_all_memorys()->erase(hashidx_); +#endif +} +#ifdef WITH_PYTHON +static std::map *all_memorys = new std::map(); +std::map *RTLIL::Memory::get_all_memorys(void) +{ + return all_memorys; +} +#endif YOSYS_NAMESPACE_END - diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e71a5fceb..89413a166 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -463,6 +463,7 @@ struct RTLIL::Const Const(RTLIL::State bit, int width = 1); Const(const std::vector &bits) : bits(bits) { flags = CONST_FLAG_NONE; } Const(const std::vector &bits); + Const(const RTLIL::Const &c); bool operator <(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const; @@ -529,6 +530,7 @@ struct RTLIL::SigChunk SigChunk(int val, int width = 32); SigChunk(RTLIL::State bit, int width = 1); SigChunk(RTLIL::SigBit bit); + SigChunk(const RTLIL::SigChunk &sigchunk); RTLIL::SigChunk extract(int offset, int length) const; @@ -553,6 +555,7 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigChunk &chunk); SigBit(const RTLIL::SigChunk &chunk, int index); SigBit(const RTLIL::SigSpec &sig); + SigBit(const RTLIL::SigBit &sigbit); bool operator <(const RTLIL::SigBit &other) const; bool operator ==(const RTLIL::SigBit &other) const; @@ -874,13 +877,13 @@ struct RTLIL::Design } } -#ifdef WITH_PYTHON - static std::map *get_all_designs(void); -#endif std::vector selected_modules() const; std::vector selected_whole_modules() const; std::vector selected_whole_modules_warn() const; +#ifdef WITH_PYTHON + static std::map *get_all_designs(void); +#endif }; struct RTLIL::Module : public RTLIL::AttrObject @@ -1175,6 +1178,10 @@ struct RTLIL::Memory : public RTLIL::AttrObject RTLIL::IdString name; int width, start_offset, size; +#ifdef WITH_PYTHON + ~Memory(); + static std::map *get_all_memorys(void); +#endif }; struct RTLIL::Cell : public RTLIL::AttrObject @@ -1287,6 +1294,7 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; } +inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){if(wire) offset = sigbit.offset;} inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const { if (wire == other.wire) From d79a2808cf2446fa21d91a6141f6fbe2318c03ec Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 16 Aug 2018 16:00:11 +0200 Subject: [PATCH 15/57] Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script --- Makefile | 2 +- kernel/python_wrappers.cc | 66 ++++++++++++++++++++++++++++++++++++++- kernel/yosys.cc | 26 +++++++++++++++ kernel/yosys.h | 5 +++ passes/cmds/plugin.cc | 63 +++++++++++++++++++++++++++++++++++++ 5 files changed, 160 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 691f43798..6466bddf2 100644 --- a/Makefile +++ b/Makefile @@ -23,7 +23,7 @@ PYTHON_VERSION := 3.5 # other configuration flags ENABLE_GPROF := 0 -ENABLE_DEBUG := 0 +ENABLE_DEBUG := 1 ENABLE_NDEBUG := 0 LINK_CURSES := 0 LINK_TERMCAP := 0 diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 18b0010ae..197be0853 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -34,6 +34,11 @@ namespace YOSYS_PYTHON { Yosys::run_pass(command); } + void log(std::string text) + { + Yosys::log(text.c_str()); + } + struct IdString { Yosys::RTLIL::IdString* ref_obj; @@ -1388,7 +1393,7 @@ namespace YOSYS_PYTHON { virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; virtual void py_notify_blackout(Module*){}; - }; + }; struct MonitorWrap : Monitor, boost::python::wrapper { @@ -1471,6 +1476,59 @@ namespace YOSYS_PYTHON { } }; + struct PyPass : public Yosys::Pass + { + PyPass(std::string name, std::string short_help) : Yosys::Pass(name, short_help) { } + + virtual void execute(vector args, Yosys::RTLIL::Design* d) YS_OVERRIDE + { + boost::python::list py_args; + for(auto arg : args) + py_args.append(arg); + py_execute(py_args, new Design(d)); + } + + virtual void help() YS_OVERRIDE + { + py_help(); + } + + virtual void py_execute(boost::python::list args, Design* d){} + virtual void py_help(){} + }; + + struct PassWrap : PyPass, boost::python::wrapper + { + + PassWrap(std::string name, std::string short_help) : PyPass(name, short_help) { } + + void py_execute(boost::python::list args, Design* d) + { + if(boost::python::override py_execute = this->get_override("py_execute")) + py_execute(args, d); + else + PyPass::py_execute(args, d); + } + + void default_py_execute(boost::python::list args, Design* d) + { + this->PyPass::py_execute(args, d); + } + + void py_help() + { + if(boost::python::override py_help = this->get_override("py_help")) + py_help(); + else + PyPass::py_help(); + } + + void default_py_help() + { + this->PyPass::py_help(); + } + }; + void Module::register_monitor(Monitor* const m) { Yosys::RTLIL::Module* cpp_module = this->get_cpp_obj(); @@ -2778,6 +2836,11 @@ namespace YOSYS_PYTHON { .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) ; + class_("Pass", init()) + .def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute) + .def("py_help", &PyPass::py_help, &PassWrap::default_py_help) + ; + class_("Initializer"); scope().attr("_hidden") = new Initializer(); @@ -3099,6 +3162,7 @@ namespace YOSYS_PYTHON { def("const_neg", const_neg); def("run",run); + def("log",log); } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 750a154e6..8e16ba01d 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -469,21 +469,40 @@ int GetSize(RTLIL::Wire *wire) return wire->width; } +bool already_setup = false; + void yosys_setup() { + if(already_setup) + return; + already_setup = true; // if there are already IdString objects then we have a global initialization order bug IdString empty_id; log_assert(empty_id.index_ == 0); IdString::get_reference(empty_id.index_); + #ifdef WITH_PYTHON + Py_Initialize(); + PyRun_SimpleString("import sys"); + PyRun_SimpleString("sys.path.append(\"./\")"); + //PyRun_SimpleString("import libyosys"); + //PyRun_SimpleString("sys.path.append(\"./plugins\")"); + //PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); + #endif + Pass::init_register(); yosys_design = new RTLIL::Design; yosys_celltypes.setup(); log_push(); } +bool already_shutdown = false; + void yosys_shutdown() { + if(already_shutdown) + return; + already_shutdown = true; log_pop(); delete yosys_design; @@ -511,9 +530,16 @@ void yosys_shutdown() dlclose(it.second); loaded_plugins.clear(); +#ifdef WITH_PYTHON + loaded_python_plugins.clear(); +#endif loaded_plugin_aliases.clear(); #endif +#ifdef WITH_PYTHON + Py_Finalize(); +#endif + IdString empty_id; IdString::put_reference(empty_id.index_); } diff --git a/kernel/yosys.h b/kernel/yosys.h index 14cbcd610..4380a5b69 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -66,6 +66,8 @@ #include #include +#include + #ifndef _YOSYS_ # error It looks like you are trying to build Yosys without the config defines set. \ When building Yosys with a custom make system, make sure you set all the \ @@ -317,6 +319,9 @@ extern std::vector pushed_designs; // from passes/cmds/pluginc.cc extern std::map loaded_plugins; +#ifdef WITH_PYTHON +extern std::map loaded_python_plugins; +#endif extern std::map loaded_plugin_aliases; void load_plugin(std::string filename, std::vector aliases); diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 828c671de..b5d22a84a 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -23,9 +23,17 @@ # include #endif +#ifdef WITH_PYTHON +# include +# include +#endif + YOSYS_NAMESPACE_BEGIN std::map loaded_plugins; +#ifdef WITH_PYTHON +std::map loaded_python_plugins; +#endif std::map loaded_plugin_aliases; #ifdef YOSYS_ENABLE_PLUGINS @@ -37,6 +45,48 @@ void load_plugin(std::string filename, std::vector aliases) filename = "./" + filename; if (!loaded_plugins.count(filename)) { + + #ifdef WITH_PYTHON + if(boost::algorithm::ends_with(filename, ".py")) + { + int last_slash = filename.find('/'); + filename = filename.substr(last_slash+1, filename.size()); + filename = filename.substr(0,filename.size()-3); + PyObject *filename_p = PyUnicode_FromString(filename.c_str());//filename.c_str()); + if(filename_p == NULL) + { + log_cmd_error("Issues converting `%s' to Python\n", filename.c_str()); + return; + } + PyObject *module_p = PyImport_Import(filename_p); + if(module_p == NULL) + { + log_cmd_error("Can't load python module `%s'\n", filename.c_str()); + return; + }/* + PyObject *dict_p = PyModule_GetDict(module_p); + if(dict_p == NULL) + { + log_cmd_error("Can't load dictionary from module `%s'\n", filename.c_str()); + return; + } + PyObject *func_p = PyDict_GetItemString(dict_p, "test"); + if(module_p == NULL) + { + log_cmd_error("Module `%s' does not contain test function\n", filename.c_str()); + return; + } + PyObject *args_p = PyTuple_New(0); + PyObject *result_p = PyObject_CallObject(func_p, args_p); + if(result_p == NULL) + printf("Calling test failed\n"); + printf("Loaded Python module\n"); + */ + loaded_python_plugins[orig_filename] = module_p; + Pass::init_register(); + } else { + #endif + void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL); if (hdl == NULL && orig_filename.find('/') == std::string::npos) hdl = dlopen((proc_share_dirname() + "plugins/" + orig_filename + ".so").c_str(), RTLD_LAZY|RTLD_LOCAL); @@ -44,6 +94,10 @@ void load_plugin(std::string filename, std::vector aliases) log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); loaded_plugins[orig_filename] = hdl; Pass::init_register(); + + #ifdef WITH_PYTHON + } + #endif } for (auto &alias : aliases) @@ -107,7 +161,11 @@ struct PluginPass : public Pass { if (list_mode) { log("\n"); +#ifdef WITH_PYTHON + if (loaded_plugins.empty() and loaded_python_plugins.empty()) +#else if (loaded_plugins.empty()) +#endif log("No plugins loaded.\n"); else log("Loaded plugins:\n"); @@ -115,6 +173,11 @@ struct PluginPass : public Pass { for (auto &it : loaded_plugins) log(" %s\n", it.first.c_str()); +#ifdef WITH_PYTHON + for (auto &it : loaded_python_plugins) + log(" %s\n", it.first.c_str()); +#endif + if (!loaded_plugin_aliases.empty()) { log("\n"); int max_alias_len = 1; From 5864db3c2bf353d4ee124d35aa2f911c4249edbc Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 14:44:03 +0200 Subject: [PATCH 16/57] Fixed issue when using a python plugin in the yosys shell --- kernel/python_wrappers.cc | 11 +++++++---- kernel/yosys.cc | 16 ++++++++++++++++ kernel/yosys.h | 5 +++++ 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 197be0853..af1f80929 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -2783,10 +2783,13 @@ namespace YOSYS_PYTHON { struct Initializer { Initializer() { - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; - Yosys::yosys_setup(); - Yosys::yosys_banner(); + if(!Yosys::yosys_already_setup()) + { + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + Yosys::yosys_setup(); + Yosys::yosys_banner(); + } } Initializer(Initializer const &) {} diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 8e16ba01d..8380fe75d 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -55,6 +55,16 @@ # include #endif +#ifdef WITH_PYTHON +#if PY_MAJOR_VERSION >= 3 +# define INIT_MODULE PyInit_libyosys + extern "C" PyObject* INIT_MODULE(); +#else +# define INIT_MODULE initlibyosys + extern "C" void INIT_MODULE(); +#endif +#endif + #include #include @@ -482,6 +492,7 @@ void yosys_setup() IdString::get_reference(empty_id.index_); #ifdef WITH_PYTHON + PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); Py_Initialize(); PyRun_SimpleString("import sys"); PyRun_SimpleString("sys.path.append(\"./\")"); @@ -496,6 +507,11 @@ void yosys_setup() log_push(); } +bool yosys_already_setup() +{ + return already_setup; +} + bool already_shutdown = false; void yosys_shutdown() diff --git a/kernel/yosys.h b/kernel/yosys.h index 4380a5b69..6ed0f8b20 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -278,6 +278,11 @@ namespace hashlib { } void yosys_setup(); + +#ifdef WITH_PYTHON +bool yosys_already_setup(); +#endif + void yosys_shutdown(); #ifdef YOSYS_ENABLE_TCL From 6d18837d62436b297b34c20d5a005ef0b6a75da2 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 15:11:06 +0200 Subject: [PATCH 17/57] Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path --- kernel/yosys.cc | 5 +---- passes/cmds/plugin.cc | 24 ++++-------------------- 2 files changed, 5 insertions(+), 24 deletions(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 8380fe75d..e36c68752 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -495,10 +495,7 @@ void yosys_setup() PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); Py_Initialize(); PyRun_SimpleString("import sys"); - PyRun_SimpleString("sys.path.append(\"./\")"); - //PyRun_SimpleString("import libyosys"); - //PyRun_SimpleString("sys.path.append(\"./plugins\")"); - //PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); + PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); #endif Pass::init_register(); diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index b5d22a84a..940092301 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -49,10 +49,12 @@ void load_plugin(std::string filename, std::vector aliases) #ifdef WITH_PYTHON if(boost::algorithm::ends_with(filename, ".py")) { - int last_slash = filename.find('/'); + int last_slash = filename.find_last_of('/'); + std::string path = filename.substr(0, last_slash); filename = filename.substr(last_slash+1, filename.size()); filename = filename.substr(0,filename.size()-3); - PyObject *filename_p = PyUnicode_FromString(filename.c_str());//filename.c_str()); + PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); + PyObject *filename_p = PyUnicode_FromString(filename.c_str()); if(filename_p == NULL) { log_cmd_error("Issues converting `%s' to Python\n", filename.c_str()); @@ -63,25 +65,7 @@ void load_plugin(std::string filename, std::vector aliases) { log_cmd_error("Can't load python module `%s'\n", filename.c_str()); return; - }/* - PyObject *dict_p = PyModule_GetDict(module_p); - if(dict_p == NULL) - { - log_cmd_error("Can't load dictionary from module `%s'\n", filename.c_str()); - return; } - PyObject *func_p = PyDict_GetItemString(dict_p, "test"); - if(module_p == NULL) - { - log_cmd_error("Module `%s' does not contain test function\n", filename.c_str()); - return; - } - PyObject *args_p = PyTuple_New(0); - PyObject *result_p = PyObject_CallObject(func_p, args_p); - if(result_p == NULL) - printf("Calling test failed\n"); - printf("Loaded Python module\n"); - */ loaded_python_plugins[orig_filename] = module_p; Pass::init_register(); } else { From d41c68ee5ad908db1dd75552816789e493d011bf Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 15:27:50 +0200 Subject: [PATCH 18/57] The share directory cannot be searched when used as a Python library, only in shell mode --- kernel/driver.cc | 8 ++++++++ kernel/yosys.cc | 1 - 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 178641101..255fe45c4 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -110,6 +110,10 @@ int main(int argc, char **argv) log_error_stderr = true; yosys_banner(); yosys_setup(); +#ifdef WITH_PYTHON + PyRun_SimpleString(("sys.path.append(\""+proc_self_dirname()+"\")").c_str()); + PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); +#endif if (argc == 2) { @@ -462,6 +466,10 @@ int main(int argc, char **argv) #endif yosys_setup(); +#ifdef WITH_PYTHON + PyRun_SimpleString(("sys.path.append(\""+proc_self_dirname()+"\")").c_str()); + PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); +#endif log_error_atexit = yosys_atexit; for (auto &fn : plugin_filenames) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index e36c68752..a6d09c077 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -495,7 +495,6 @@ void yosys_setup() PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); Py_Initialize(); PyRun_SimpleString("import sys"); - PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); #endif Pass::init_register(); From d87c7df27f8268ab849d3f9d84c4b000f83b44e2 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 15:28:09 +0200 Subject: [PATCH 19/57] Two passes are not allowed to have the same filename --- passes/cmds/plugin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 940092301..1a39140d4 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -44,7 +44,7 @@ void load_plugin(std::string filename, std::vector aliases) if (filename.find('/') == std::string::npos) filename = "./" + filename; - if (!loaded_plugins.count(filename)) { + if (!loaded_plugins.count(filename) && !loaded_python_plugins.count(filename)) { #ifdef WITH_PYTHON if(boost::algorithm::ends_with(filename, ".py")) From 95d65971f3f114adb8b62a9d29bc0829467e3d81 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 16:04:43 +0200 Subject: [PATCH 20/57] added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile --- kernel/python_wrappers.cc | 6 +++--- kernel/rtlil.cc | 10 ++++------ kernel/rtlil.h | 1 + kernel/yosys.h | 2 ++ passes/cmds/plugin.cc | 4 ++++ 5 files changed, 14 insertions(+), 9 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index af1f80929..2c27ea47f 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -2783,13 +2783,13 @@ namespace YOSYS_PYTHON { struct Initializer { Initializer() { - if(!Yosys::yosys_already_setup()) - { + if(!Yosys::yosys_already_setup()) + { Yosys::log_streams.push_back(&std::cout); Yosys::log_error_stderr = true; Yosys::yosys_setup(); Yosys::yosys_banner(); - } + } } Initializer(Initializer const &) {} diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index bcda931d2..93b138071 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3925,14 +3925,12 @@ RTLIL::Process *RTLIL::Process::clone() const return new_proc; } -RTLIL::Memory::~Memory() -{ -#ifdef WITH_PYTHON - RTLIL::Memory::get_all_memorys()->erase(hashidx_); -#endif -} #ifdef WITH_PYTHON +RTLIL::Memory::~Memory() +{ + RTLIL::Memory::get_all_memorys()->erase(hashidx_); +} static std::map *all_memorys = new std::map(); std::map *RTLIL::Memory::get_all_memorys(void) { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 89413a166..0e5159be2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1175,6 +1175,7 @@ struct RTLIL::Memory : public RTLIL::AttrObject unsigned int hash() const { return hashidx_; } Memory(); + ~Memory(); RTLIL::IdString name; int width, start_offset, size; diff --git a/kernel/yosys.h b/kernel/yosys.h index 6ed0f8b20..9f5f056a5 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -66,7 +66,9 @@ #include #include +#ifdef WITH_PYTHON #include +#endif #ifndef _YOSYS_ # error It looks like you are trying to build Yosys without the config defines set. \ diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 1a39140d4..a889397e2 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -44,7 +44,11 @@ void load_plugin(std::string filename, std::vector aliases) if (filename.find('/') == std::string::npos) filename = "./" + filename; + #ifdef WITH_PYTHON if (!loaded_plugins.count(filename) && !loaded_python_plugins.count(filename)) { + #else + if (!loaded_plugins.count(filename)) { + #endif #ifdef WITH_PYTHON if(boost::algorithm::ends_with(filename, ".py")) From 29efc9d0b1b003113e1faf1e76ce32cffb0ff95a Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 11:07:59 +0200 Subject: [PATCH 21/57] Deleted duplicate Destructor --- kernel/rtlil.h | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0e5159be2..89413a166 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1175,7 +1175,6 @@ struct RTLIL::Memory : public RTLIL::AttrObject unsigned int hash() const { return hashidx_; } Memory(); - ~Memory(); RTLIL::IdString name; int width, start_offset, size; From 334bfce4c4df994a8a0bdbf0f50b29df996e3cb0 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 13:15:08 +0200 Subject: [PATCH 22/57] Added previousely missed functions --- kernel/python_wrappers.cc | 446 +++++++++++++++++++++++++++++++++++++- 1 file changed, 445 insertions(+), 1 deletion(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 2c27ea47f..5e964dcac 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -36,7 +36,7 @@ namespace YOSYS_PYTHON { void log(std::string text) { - Yosys::log(text.c_str()); + Yosys::log("%s",text.c_str()); } struct IdString @@ -74,11 +74,23 @@ namespace YOSYS_PYTHON { //WRAPPED static inline void put_reference(int idx) static inline void put_reference(int idx); + //WRAPPED std::string str() const { + std::string str(); + + //WRAPPED bool empty() const { + bool empty(); + + //WRAPPED void clear() { + void clear(); + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } bool in_IdString(IdString *rhs); //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } bool in_std_string(std::string rhs); + + //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } + bool in_pool_IdString(boost::python::list *rhs); }; std::ostream &operator<<(std::ostream &ostr, const IdString &ref) @@ -110,12 +122,36 @@ namespace YOSYS_PYTHON { return ref_obj; } + //WRAPPED bool as_bool() const; + bool as_bool(); + //WRAPPED int as_int(bool is_signed = false) const; int as_int(bool is_signed = false); + //WRAPPED std::string as_string() const; + std::string as_string(); + //WRAPPED static Const from_string(std::string str); static Const from_string(std::string str); + //WRAPPED std::string decode_string() const; + std::string decode_string(); + + //WRAPPED inline int size() const { return bits.size(); } + inline int size(); + + //WRAPPED bool is_fully_zero() const; + bool is_fully_zero(); + + //WRAPPED bool is_fully_ones() const; + bool is_fully_ones(); + + //WRAPPED bool is_fully_def() const; + bool is_fully_def(); + + //WRAPPED bool is_fully_undef() const; + bool is_fully_undef(); + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { inline Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); }; @@ -148,6 +184,9 @@ namespace YOSYS_PYTHON { { return ref_obj; } + + //WRAPPED RTLIL::CaseRule *clone() const; + CaseRule clone(); }; std::ostream &operator<<(std::ostream &ostr, const CaseRule &ref) @@ -178,6 +217,9 @@ namespace YOSYS_PYTHON { { return ref_obj; } + + //WRAPPED RTLIL::SwitchRule *clone() const; + SwitchRule clone(); }; std::ostream &operator<<(std::ostream &ostr, const SwitchRule &ref) @@ -208,6 +250,9 @@ namespace YOSYS_PYTHON { { return ref_obj; } + + //WRAPPED RTLIL::SyncRule *clone() const; + SyncRule clone(); }; std::ostream &operator<<(std::ostream &ostr, const SyncRule &ref) @@ -238,6 +283,9 @@ namespace YOSYS_PYTHON { { return ref_obj; } + + //WRAPPED RTLIL::Process *clone() const; + Process clone(); }; std::ostream &operator<<(std::ostream &ostr, const Process &ref) @@ -332,6 +380,12 @@ namespace YOSYS_PYTHON { return ref_obj; } + //WRAPPED inline int size() const { return width_; } + inline int size(); + + //WRAPPED inline bool empty() const { return width_ == 0; } + inline bool empty(); + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); void replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with); @@ -383,9 +437,57 @@ namespace YOSYS_PYTHON { //WRAPPED RTLIL::SigSpec repeat(int num) const; SigSpec repeat(int num); + //WRAPPED bool is_wire() const; + bool is_wire(); + + //WRAPPED bool is_chunk() const; + bool is_chunk(); + + //WRAPPED inline bool is_bit() const { return width_ == 1; } + inline bool is_bit(); + + //WRAPPED bool is_fully_const() const; + bool is_fully_const(); + + //WRAPPED bool is_fully_zero() const; + bool is_fully_zero(); + + //WRAPPED bool is_fully_ones() const; + bool is_fully_ones(); + + //WRAPPED bool is_fully_def() const; + bool is_fully_def(); + + //WRAPPED bool is_fully_undef() const; + bool is_fully_undef(); + + //WRAPPED bool has_const() const; + bool has_const(); + + //WRAPPED bool has_marked_bits() const; + bool has_marked_bits(); + + //WRAPPED bool as_bool() const; + bool as_bool(); + //WRAPPED int as_int(bool is_signed = false) const; int as_int(bool is_signed = false); + //WRAPPED std::string as_string() const; + std::string as_string(); + + //WRAPPED RTLIL::Const as_const() const; + Const as_const(); + + //WRAPPED RTLIL::Wire *as_wire() const; + Wire as_wire(); + + //WRAPPED RTLIL::SigChunk as_chunk() const; + SigChunk as_chunk(); + + //WRAPPED RTLIL::SigBit as_bit() const; + SigBit as_bit(); + //WRAPPED bool match(std::string pattern) const; bool match(std::string pattern); @@ -397,6 +499,9 @@ namespace YOSYS_PYTHON { //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str); + + //WRAPPED void check() const; + void check(); }; std::ostream &operator<<(std::ostream &ostr, const SigSpec &ref) @@ -432,6 +537,9 @@ namespace YOSYS_PYTHON { //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); void setPort(IdString *portname, SigSpec *signal); + //WRAPPED bool known() const; + bool known(); + //WRAPPED bool input(RTLIL::IdString portname) const; bool input(IdString *portname); @@ -449,6 +557,9 @@ namespace YOSYS_PYTHON { //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + + //WRAPPED bool has_keep_attr() const { + bool has_keep_attr(); }; std::ostream &operator<<(std::ostream &ostr, const Cell &ref) @@ -578,6 +689,24 @@ namespace YOSYS_PYTHON { //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; void cloneInto(Module *new_mod); + //WRAPPED bool has_memories() const; + bool has_memories(); + + //WRAPPED bool has_processes() const; + bool has_processes(); + + //WRAPPED bool has_memories_warn() const; + bool has_memories_warn(); + + //WRAPPED bool has_processes_warn() const; + bool has_processes_warn(); + + //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } + Wire wire(IdString *id); + + //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } + Cell cell(IdString *id); + //WRAPPED void remove(const pool &wires); void remove_pool_Wire(boost::python::list *wires); @@ -1104,6 +1233,9 @@ namespace YOSYS_PYTHON { //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; bool selected_whole_module_Module(Module *mod); + + //WRAPPED bool full_selection() const { + bool full_selection(); }; std::ostream &operator<<(std::ostream &ostr, const Design &ref) @@ -1557,6 +1689,24 @@ namespace YOSYS_PYTHON { Yosys::RTLIL::IdString::put_reference(idx); } + //WRAPPED std::string str() const { + std::string IdString::str() + { + return this->get_cpp_obj()->str(); + } + + //WRAPPED bool empty() const { + bool IdString::empty() + { + return this->get_cpp_obj()->empty(); + } + + //WRAPPED void clear() { + void IdString::clear() + { + this->get_cpp_obj()->clear(); + } + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } bool IdString::in_IdString(IdString *rhs) { @@ -1569,30 +1719,124 @@ namespace YOSYS_PYTHON { return this->get_cpp_obj()->in(rhs); } + //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } + bool IdString::in_pool_IdString(boost::python::list *rhs) + { + pool rhs_; + for(int i = 0; i < len(*rhs); ++i) + { + } + return this->get_cpp_obj()->in(rhs_); + } + + //WRAPPED bool as_bool() const; + bool Const::as_bool() + { + return this->get_cpp_obj()->as_bool(); + } + //WRAPPED int as_int(bool is_signed = false) const; int Const::as_int(bool is_signed) { return this->get_cpp_obj()->as_int(is_signed); } + //WRAPPED std::string as_string() const; + std::string Const::as_string() + { + return this->get_cpp_obj()->as_string(); + } + //WRAPPED static Const from_string(std::string str); Const Const::from_string(std::string str) { return Const(Yosys::RTLIL::Const::from_string(str)); } + //WRAPPED std::string decode_string() const; + std::string Const::decode_string() + { + return this->get_cpp_obj()->decode_string(); + } + + //WRAPPED inline int size() const { return bits.size(); } + inline int Const::size() + { + return this->get_cpp_obj()->size(); + } + + //WRAPPED bool is_fully_zero() const; + bool Const::is_fully_zero() + { + return this->get_cpp_obj()->is_fully_zero(); + } + + //WRAPPED bool is_fully_ones() const; + bool Const::is_fully_ones() + { + return this->get_cpp_obj()->is_fully_ones(); + } + + //WRAPPED bool is_fully_def() const; + bool Const::is_fully_def() + { + return this->get_cpp_obj()->is_fully_def(); + } + + //WRAPPED bool is_fully_undef() const; + bool Const::is_fully_undef() + { + return this->get_cpp_obj()->is_fully_undef(); + } + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { inline Const Const::extract(int offset, int len, State padding) { return Const(this->get_cpp_obj()->extract(offset, len, padding)); } + //WRAPPED RTLIL::CaseRule *clone() const; + CaseRule CaseRule::clone() + { + return CaseRule(this->get_cpp_obj()->clone()); + } + + //WRAPPED RTLIL::SwitchRule *clone() const; + SwitchRule SwitchRule::clone() + { + return SwitchRule(this->get_cpp_obj()->clone()); + } + + //WRAPPED RTLIL::SyncRule *clone() const; + SyncRule SyncRule::clone() + { + return SyncRule(this->get_cpp_obj()->clone()); + } + + //WRAPPED RTLIL::Process *clone() const; + Process Process::clone() + { + return Process(this->get_cpp_obj()->clone()); + } + //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; SigChunk SigChunk::extract(int offset, int length) { return SigChunk(this->get_cpp_obj()->extract(offset, length)); } + //WRAPPED inline int size() const { return width_; } + inline int SigSpec::size() + { + return this->get_cpp_obj()->size(); + } + + //WRAPPED inline bool empty() const { return width_ == 0; } + inline bool SigSpec::empty() + { + return this->get_cpp_obj()->empty(); + } + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with) { @@ -1711,12 +1955,108 @@ namespace YOSYS_PYTHON { return SigSpec(this->get_cpp_obj()->repeat(num)); } + //WRAPPED bool is_wire() const; + bool SigSpec::is_wire() + { + return this->get_cpp_obj()->is_wire(); + } + + //WRAPPED bool is_chunk() const; + bool SigSpec::is_chunk() + { + return this->get_cpp_obj()->is_chunk(); + } + + //WRAPPED inline bool is_bit() const { return width_ == 1; } + inline bool SigSpec::is_bit() + { + return this->get_cpp_obj()->is_bit(); + } + + //WRAPPED bool is_fully_const() const; + bool SigSpec::is_fully_const() + { + return this->get_cpp_obj()->is_fully_const(); + } + + //WRAPPED bool is_fully_zero() const; + bool SigSpec::is_fully_zero() + { + return this->get_cpp_obj()->is_fully_zero(); + } + + //WRAPPED bool is_fully_ones() const; + bool SigSpec::is_fully_ones() + { + return this->get_cpp_obj()->is_fully_ones(); + } + + //WRAPPED bool is_fully_def() const; + bool SigSpec::is_fully_def() + { + return this->get_cpp_obj()->is_fully_def(); + } + + //WRAPPED bool is_fully_undef() const; + bool SigSpec::is_fully_undef() + { + return this->get_cpp_obj()->is_fully_undef(); + } + + //WRAPPED bool has_const() const; + bool SigSpec::has_const() + { + return this->get_cpp_obj()->has_const(); + } + + //WRAPPED bool has_marked_bits() const; + bool SigSpec::has_marked_bits() + { + return this->get_cpp_obj()->has_marked_bits(); + } + + //WRAPPED bool as_bool() const; + bool SigSpec::as_bool() + { + return this->get_cpp_obj()->as_bool(); + } + //WRAPPED int as_int(bool is_signed = false) const; int SigSpec::as_int(bool is_signed) { return this->get_cpp_obj()->as_int(is_signed); } + //WRAPPED std::string as_string() const; + std::string SigSpec::as_string() + { + return this->get_cpp_obj()->as_string(); + } + + //WRAPPED RTLIL::Const as_const() const; + Const SigSpec::as_const() + { + return Const(this->get_cpp_obj()->as_const()); + } + + //WRAPPED RTLIL::Wire *as_wire() const; + Wire SigSpec::as_wire() + { + return Wire(this->get_cpp_obj()->as_wire()); + } + + //WRAPPED RTLIL::SigChunk as_chunk() const; + SigChunk SigSpec::as_chunk() + { + return SigChunk(this->get_cpp_obj()->as_chunk()); + } + + //WRAPPED RTLIL::SigBit as_bit() const; + SigBit SigSpec::as_bit() + { + return SigBit(this->get_cpp_obj()->as_bit()); + } + //WRAPPED bool match(std::string pattern) const; bool SigSpec::match(std::string pattern) { @@ -1741,6 +2081,12 @@ namespace YOSYS_PYTHON { return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); } + //WRAPPED void check() const; + void SigSpec::check() + { + this->get_cpp_obj()->check(); + } + //WRAPPED bool hasPort(RTLIL::IdString portname) const; bool Cell::hasPort(IdString *portname) { @@ -1759,6 +2105,12 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj()); } + //WRAPPED bool known() const; + bool Cell::known() + { + return this->get_cpp_obj()->known(); + } + //WRAPPED bool input(RTLIL::IdString portname) const; bool Cell::input(IdString *portname) { @@ -1795,6 +2147,12 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed); } + //WRAPPED bool has_keep_attr() const { + bool Cell::has_keep_attr() + { + return this->get_cpp_obj()->has_keep_attr(); + } + //WRAPPED void connect(const RTLIL::SigSig &conn); void Module::connect_SigSig(PyObject* conn) { @@ -1828,6 +2186,42 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj()); } + //WRAPPED bool has_memories() const; + bool Module::has_memories() + { + return this->get_cpp_obj()->has_memories(); + } + + //WRAPPED bool has_processes() const; + bool Module::has_processes() + { + return this->get_cpp_obj()->has_processes(); + } + + //WRAPPED bool has_memories_warn() const; + bool Module::has_memories_warn() + { + return this->get_cpp_obj()->has_memories_warn(); + } + + //WRAPPED bool has_processes_warn() const; + bool Module::has_processes_warn() + { + return this->get_cpp_obj()->has_processes_warn(); + } + + //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } + Wire Module::wire(IdString *id) + { + return Wire(this->get_cpp_obj()->wire(*id->get_cpp_obj())); + } + + //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } + Cell Module::cell(IdString *id) + { + return Cell(this->get_cpp_obj()->cell(*id->get_cpp_obj())); + } + //WRAPPED void remove(const pool &wires); void Module::remove_pool_Wire(boost::python::list *wires) { @@ -2780,6 +3174,12 @@ namespace YOSYS_PYTHON { return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj()); } + //WRAPPED bool full_selection() const { + bool Design::full_selection() + { + return this->get_cpp_obj()->full_selection(); + } + struct Initializer { Initializer() { @@ -2853,36 +3253,52 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("get_reference", &IdString::get_reference) .def("put_reference", &IdString::put_reference) + .def("str", &IdString::str) + .def("empty", &IdString::empty) + .def("clear", &IdString::clear) .def("in_IdString", &IdString::in_IdString) .def("in_std_string", &IdString::in_std_string) + .def("in_pool_IdString", &IdString::in_pool_IdString) ; class_("Const") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("as_bool", &Const::as_bool) .def("as_int", &Const::as_int) + .def("as_string", &Const::as_string) .def("from_string", &Const::from_string) + .def("decode_string", &Const::decode_string) + .def("size", &Const::size) + .def("is_fully_zero", &Const::is_fully_zero) + .def("is_fully_ones", &Const::is_fully_ones) + .def("is_fully_def", &Const::is_fully_def) + .def("is_fully_undef", &Const::is_fully_undef) .def("extract", &Const::extract) ; class_("CaseRule") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("clone", &CaseRule::clone) ; class_("SwitchRule") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("clone", &SwitchRule::clone) ; class_("SyncRule") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("clone", &SyncRule::clone) ; class_("Process") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("clone", &Process::clone) ; class_("SigChunk") @@ -2899,6 +3315,8 @@ namespace YOSYS_PYTHON { class_("SigSpec") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("size", &SigSpec::size) + .def("empty", &SigSpec::empty) .def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec) .def("replace_SigSpec_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec_SigSpec) .def("replace_int_SigSpec", &SigSpec::replace_int_SigSpec) @@ -2916,11 +3334,28 @@ namespace YOSYS_PYTHON { .def("append_bit", &SigSpec::append_bit) .def("extend_u0", &SigSpec::extend_u0) .def("repeat", &SigSpec::repeat) + .def("is_wire", &SigSpec::is_wire) + .def("is_chunk", &SigSpec::is_chunk) + .def("is_bit", &SigSpec::is_bit) + .def("is_fully_const", &SigSpec::is_fully_const) + .def("is_fully_zero", &SigSpec::is_fully_zero) + .def("is_fully_ones", &SigSpec::is_fully_ones) + .def("is_fully_def", &SigSpec::is_fully_def) + .def("is_fully_undef", &SigSpec::is_fully_undef) + .def("has_const", &SigSpec::has_const) + .def("has_marked_bits", &SigSpec::has_marked_bits) + .def("as_bool", &SigSpec::as_bool) .def("as_int", &SigSpec::as_int) + .def("as_string", &SigSpec::as_string) + .def("as_const", &SigSpec::as_const) + .def("as_wire", &SigSpec::as_wire) + .def("as_chunk", &SigSpec::as_chunk) + .def("as_bit", &SigSpec::as_bit) .def("match", &SigSpec::match) .def("parse", &SigSpec::parse) .def("parse_sel", &SigSpec::parse_sel) .def("parse_rhs", &SigSpec::parse_rhs) + .def("check", &SigSpec::check) ; class_("Cell", no_init) @@ -2929,12 +3364,14 @@ namespace YOSYS_PYTHON { .def("hasPort", &Cell::hasPort) .def("unsetPort", &Cell::unsetPort) .def("setPort", &Cell::setPort) + .def("known", &Cell::known) .def("input", &Cell::input) .def("output", &Cell::output) .def("hasParam", &Cell::hasParam) .def("unsetParam", &Cell::unsetParam) .def("setParam", &Cell::setParam) .def("fixup_parameters", &Cell::fixup_parameters) + .def("has_keep_attr", &Cell::has_keep_attr) ; class_("Wire", no_init) @@ -2957,6 +3394,12 @@ namespace YOSYS_PYTHON { .def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec) .def("new_connections", &Module::new_connections) .def("cloneInto", &Module::cloneInto) + .def("has_memories", &Module::has_memories) + .def("has_processes", &Module::has_processes) + .def("has_memories_warn", &Module::has_memories_warn) + .def("has_processes_warn", &Module::has_processes_warn) + .def("wire", &Module::wire) + .def("cell", &Module::cell) .def("remove_pool_Wire", &Module::remove_pool_Wire) .def("remove_Cell", &Module::remove_Cell) .def("rename_Wire_IdString", &Module::rename_Wire_IdString) @@ -3123,6 +3566,7 @@ namespace YOSYS_PYTHON { .def("selected_member", &Design::selected_member) .def("selected_module_Module", &Design::selected_module_Module) .def("selected_whole_module_Module", &Design::selected_whole_module_Module) + .def("full_selection", &Design::full_selection) ; def("escape_id", escape_id); From 4acb29db0c5b9c8374865640772592a49f51ec5e Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 14:49:35 +0200 Subject: [PATCH 23/57] added operators <, == and != --- kernel/python_wrappers.cc | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 5e964dcac..015a303f8 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -91,6 +91,12 @@ namespace YOSYS_PYTHON { //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } bool in_pool_IdString(boost::python::list *rhs); + + bool operator<(IdString rhs) { return get_cpp_obj() ("Const") @@ -3275,6 +3308,9 @@ namespace YOSYS_PYTHON { .def("is_fully_def", &Const::is_fully_def) .def("is_fully_undef", &Const::is_fully_undef) .def("extract", &Const::extract) + .def(self < self) + .def(self == self) + .def(self != self) ; class_("CaseRule") @@ -3305,11 +3341,17 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("extract", &SigChunk::extract) + .def(self < self) + .def(self == self) + .def(self != self) ; class_("SigBit") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def(self < self) + .def(self == self) + .def(self != self) ; class_("SigSpec") @@ -3356,6 +3398,9 @@ namespace YOSYS_PYTHON { .def("parse_sel", &SigSpec::parse_sel) .def("parse_rhs", &SigSpec::parse_rhs) .def("check", &SigSpec::check) + .def(self < self) + .def(self == self) + .def(self != self) ; class_("Cell", no_init) From 038caab4e0de7e8c3b0dde8c77a716fbdb86cf1f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 15:25:43 +0200 Subject: [PATCH 24/57] Wrapped functions that use unsigned int or type_t as types --- kernel/python_wrappers.cc | 134 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 127 insertions(+), 7 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 015a303f8..3d9094313 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -69,20 +69,29 @@ namespace YOSYS_PYTHON { } //WRAPPED static inline int get_reference(int idx) - static inline int get_reference(int idx); + static int get_reference(int idx); //WRAPPED static inline void put_reference(int idx) - static inline void put_reference(int idx); + static void put_reference(int idx); //WRAPPED std::string str() const { std::string str(); + //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { + std::string substr(size_t pos = 0, size_t len = std::string::npos); + + //WRAPPED size_t size() const { + size_t size(); + //WRAPPED bool empty() const { bool empty(); //WRAPPED void clear() { void clear(); + //WRAPPED unsigned int hash() const { + unsigned int hash(); + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } bool in_IdString(IdString *rhs); @@ -144,7 +153,7 @@ namespace YOSYS_PYTHON { std::string decode_string(); //WRAPPED inline int size() const { return bits.size(); } - inline int size(); + int size(); //WRAPPED bool is_fully_zero() const; bool is_fully_zero(); @@ -159,7 +168,10 @@ namespace YOSYS_PYTHON { bool is_fully_undef(); //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { - inline Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); + Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); + + //WRAPPED inline unsigned int hash() const { + unsigned int hash(); bool operator<(Const rhs) { return get_cpp_obj() get_cpp_obj()->str(); } + //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { + std::string IdString::substr(size_t pos, size_t len) + { + return this->get_cpp_obj()->substr(pos, len); + } + + //WRAPPED size_t size() const { + size_t IdString::size() + { + return this->get_cpp_obj()->size(); + } + //WRAPPED bool empty() const { bool IdString::empty() { @@ -1737,6 +1785,12 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->clear(); } + //WRAPPED unsigned int hash() const { + unsigned int IdString::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } bool IdString::in_IdString(IdString *rhs) { @@ -1825,6 +1879,12 @@ namespace YOSYS_PYTHON { return Const(this->get_cpp_obj()->extract(offset, len, padding)); } + //WRAPPED inline unsigned int hash() const { + inline unsigned int Const::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED RTLIL::CaseRule *clone() const; CaseRule CaseRule::clone() { @@ -1855,6 +1915,18 @@ namespace YOSYS_PYTHON { return SigChunk(this->get_cpp_obj()->extract(offset, length)); } + //WRAPPED unsigned int hash() const; + unsigned int SigBit::hash() + { + return this->get_cpp_obj()->hash(); + } + + //WRAPPED size_t get_hash() const { + size_t SigSpec::get_hash() + { + return this->get_cpp_obj()->get_hash(); + } + //WRAPPED inline int size() const { return width_; } inline int SigSpec::size() { @@ -2111,12 +2183,24 @@ namespace YOSYS_PYTHON { return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); } + //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; + unsigned int SigSpec::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED void check() const; void SigSpec::check() { this->get_cpp_obj()->check(); } + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Cell::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED bool hasPort(RTLIL::IdString portname) const; bool Cell::hasPort(IdString *portname) { @@ -2183,6 +2267,24 @@ namespace YOSYS_PYTHON { return this->get_cpp_obj()->has_keep_attr(); } + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Wire::hash() + { + return this->get_cpp_obj()->hash(); + } + + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Memory::hash() + { + return this->get_cpp_obj()->hash(); + } + + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Module::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED void connect(const RTLIL::SigSig &conn); void Module::connect_SigSig(PyObject* conn) { @@ -3096,6 +3198,12 @@ namespace YOSYS_PYTHON { return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src)); } + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Design::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED RTLIL::Module *module(RTLIL::IdString name); Module Design::module(IdString *name) { @@ -3284,8 +3392,11 @@ namespace YOSYS_PYTHON { .def("get_reference", &IdString::get_reference) .def("put_reference", &IdString::put_reference) .def("str", &IdString::str) + .def("substr", &IdString::substr) + .def("size", &IdString::size) .def("empty", &IdString::empty) .def("clear", &IdString::clear) + .def("hash", &IdString::hash) .def("in_IdString", &IdString::in_IdString) .def("in_std_string", &IdString::in_std_string) .def("in_pool_IdString", &IdString::in_pool_IdString) @@ -3308,6 +3419,7 @@ namespace YOSYS_PYTHON { .def("is_fully_def", &Const::is_fully_def) .def("is_fully_undef", &Const::is_fully_undef) .def("extract", &Const::extract) + .def("hash", &Const::hash) .def(self < self) .def(self == self) .def(self != self) @@ -3349,6 +3461,7 @@ namespace YOSYS_PYTHON { class_("SigBit") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hash", &SigBit::hash) .def(self < self) .def(self == self) .def(self != self) @@ -3357,6 +3470,7 @@ namespace YOSYS_PYTHON { class_("SigSpec") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_hash", &SigSpec::get_hash) .def("size", &SigSpec::size) .def("empty", &SigSpec::empty) .def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec) @@ -3397,6 +3511,7 @@ namespace YOSYS_PYTHON { .def("parse", &SigSpec::parse) .def("parse_sel", &SigSpec::parse_sel) .def("parse_rhs", &SigSpec::parse_rhs) + .def("hash", &SigSpec::hash) .def("check", &SigSpec::check) .def(self < self) .def(self == self) @@ -3406,6 +3521,7 @@ namespace YOSYS_PYTHON { class_("Cell", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hash", &Cell::hash) .def("hasPort", &Cell::hasPort) .def("unsetPort", &Cell::unsetPort) .def("setPort", &Cell::setPort) @@ -3422,11 +3538,13 @@ namespace YOSYS_PYTHON { class_("Wire", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hash", &Wire::hash) ; class_("Memory", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hash", &Memory::hash) ; class_("Module") @@ -3435,6 +3553,7 @@ namespace YOSYS_PYTHON { .def("get_cells", &Module::get_cells) .def("get_wires", &Module::get_wires) .def("register_monitor", &Module::register_monitor) + .def("hash", &Module::hash) .def("connect_SigSig", &Module::connect_SigSig) .def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec) .def("new_connections", &Module::new_connections) @@ -3593,6 +3712,7 @@ namespace YOSYS_PYTHON { .def("get_modules", &Design::get_modules) .def("run", &Design::run) .def("register_monitor", &Design::register_monitor) + .def("hash", &Design::hash) .def("module", &Design::module) .def("has", &Design::has) .def("add", &Design::add) From 60608a86bbeddbb8e2fe736adb931d757ed92bda Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 22 Aug 2018 11:59:22 +0200 Subject: [PATCH 25/57] Fixed Identation --- kernel/python_wrappers.cc | 333 +++++++++++++++++++------------------- 1 file changed, 166 insertions(+), 167 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 3d9094313..5ca4e6e6a 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -1541,148 +1541,148 @@ namespace YOSYS_PYTHON { return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - struct Monitor : public Yosys::RTLIL::Monitor - { + struct Monitor : public Yosys::RTLIL::Monitor + { - virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_add(new Module(module)); - } + virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_add(new Module(module)); + } - virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_del(new Module(module)); - } + virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_del(new Module(module)); + } - virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE - { - Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); - Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); - py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig)); - delete tmp_port; - delete tmp_old_sig; - } + virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE + { + Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); + Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); + py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig)); + delete tmp_port; + delete tmp_old_sig; + } - virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE - { - Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); - Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); - py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second))); - delete first; - delete second; - } + virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE + { + Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); + Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); + py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second))); + delete first; + delete second; + } - virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE - { - boost::python::list sigsig_list; - for(auto sigsig : sigsig_vec) - sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second))); - py_notify_connect_list(new Module(module), sigsig_list); - } + virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + { + boost::python::list sigsig_list; + for(auto sigsig : sigsig_vec) + sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second))); + py_notify_connect_list(new Module(module), sigsig_list); + } - virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_blackout(new Module(module)); - } + virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_blackout(new Module(module)); + } - virtual void py_notify_module_add(Module*){}; - virtual void py_notify_module_del(Module*){}; - virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){}; - virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; - virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; - virtual void py_notify_blackout(Module*){}; - }; + virtual void py_notify_module_add(Module*){}; + virtual void py_notify_module_del(Module*){}; + virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){}; + virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; + virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; + virtual void py_notify_blackout(Module*){}; + }; - struct MonitorWrap : Monitor, boost::python::wrapper - { - void py_notify_module_add(Module* m) - { - if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) - py_notify_module_add(m); - else - Monitor::py_notify_module_add(m); - } + struct MonitorWrap : Monitor, boost::python::wrapper + { + void py_notify_module_add(Module* m) + { + if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) + py_notify_module_add(m); + else + Monitor::py_notify_module_add(m); + } - void default_py_notify_module_add(Module* m) - { - this->Monitor::py_notify_module_add(m); - } + void default_py_notify_module_add(Module* m) + { + this->Monitor::py_notify_module_add(m); + } - void py_notify_module_del(Module* m) - { - if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) - py_notify_module_del(m); - else - Monitor::py_notify_module_del(m); - } + void py_notify_module_del(Module* m) + { + if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) + py_notify_module_del(m); + else + Monitor::py_notify_module_del(m); + } - void default_py_notify_module_del(Module* m) - { - this->Monitor::py_notify_module_del(m); - } + void default_py_notify_module_del(Module* m) + { + this->Monitor::py_notify_module_del(m); + } - void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) - { - if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) - py_notify_connect_cell(cell, port, old_sig, sig); - else - Monitor::py_notify_connect_cell(cell, port, old_sig, sig); - } + void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + { + if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) + py_notify_connect_cell(cell, port, old_sig, sig); + else + Monitor::py_notify_connect_cell(cell, port, old_sig, sig); + } - void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) - { - this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); - } + void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + { + this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); + } - void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) - { - if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) - py_notify_connect_tuple(module, sigsig); - else - Monitor::py_notify_connect_tuple(module, sigsig); - } + void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + { + if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) + py_notify_connect_tuple(module, sigsig); + else + Monitor::py_notify_connect_tuple(module, sigsig); + } - void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) - { - this->Monitor::py_notify_connect_tuple(module, sigsig); - } + void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + { + this->Monitor::py_notify_connect_tuple(module, sigsig); + } - void py_notify_connect_list(Module* module, boost::python::list sigsig_list) - { - if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) - py_notify_connect_list(module, sigsig_list); - else - Monitor::py_notify_connect_list(module, sigsig_list); - } + void py_notify_connect_list(Module* module, boost::python::list sigsig_list) + { + if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) + py_notify_connect_list(module, sigsig_list); + else + Monitor::py_notify_connect_list(module, sigsig_list); + } - void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list) - { - this->Monitor::py_notify_connect_list(module, sigsig_list); - } + void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list) + { + this->Monitor::py_notify_connect_list(module, sigsig_list); + } - void py_notify_blackout(Module* m) - { - if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) - py_notify_blackout(m); - else - Monitor::py_notify_blackout(m); - } + void py_notify_blackout(Module* m) + { + if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) + py_notify_blackout(m); + else + Monitor::py_notify_blackout(m); + } - void default_py_notify_blackout(Module* m) - { - this->Monitor::py_notify_blackout(m); - } - }; + void default_py_notify_blackout(Module* m) + { + this->Monitor::py_notify_blackout(m); + } + }; - struct PyPass : public Yosys::Pass - { + struct PyPass : public Yosys::Pass + { PyPass(std::string name, std::string short_help) : Yosys::Pass(name, short_help) { } virtual void execute(vector args, Yosys::RTLIL::Design* d) YS_OVERRIDE { boost::python::list py_args; - for(auto arg : args) - py_args.append(arg); + for(auto arg : args) + py_args.append(arg); py_execute(py_args, new Design(d)); } @@ -1693,19 +1693,19 @@ namespace YOSYS_PYTHON { virtual void py_execute(boost::python::list args, Design* d){} virtual void py_help(){} - }; + }; - struct PassWrap : PyPass, boost::python::wrapper - { + struct PassWrap : PyPass, boost::python::wrapper + { PassWrap(std::string name, std::string short_help) : PyPass(name, short_help) { } void py_execute(boost::python::list args, Design* d) { - if(boost::python::override py_execute = this->get_override("py_execute")) - py_execute(args, d); - else - PyPass::py_execute(args, d); + if(boost::python::override py_execute = this->get_override("py_execute")) + py_execute(args, d); + else + PyPass::py_execute(args, d); } void default_py_execute(boost::python::list args, Design* d) @@ -1715,17 +1715,17 @@ namespace YOSYS_PYTHON { void py_help() { - if(boost::python::override py_help = this->get_override("py_help")) - py_help(); - else - PyPass::py_help(); + if(boost::python::override py_help = this->get_override("py_help")) + py_help(); + else + PyPass::py_help(); } void default_py_help() { this->PyPass::py_help(); } - }; + }; void Module::register_monitor(Monitor* const m) { @@ -3321,13 +3321,13 @@ namespace YOSYS_PYTHON { struct Initializer { Initializer() { - if(!Yosys::yosys_already_setup()) - { + if(!Yosys::yosys_already_setup()) + { Yosys::log_streams.push_back(&std::cout); Yosys::log_error_stderr = true; Yosys::yosys_setup(); Yosys::yosys_banner(); - } + } } Initializer(Initializer const &) {} @@ -3341,46 +3341,46 @@ namespace YOSYS_PYTHON { { using namespace boost::python; - enum_("State") - .value("S0",Yosys::RTLIL::S0) - .value("S1",Yosys::RTLIL::S1) - .value("Sx",Yosys::RTLIL::Sx) - .value("Sz",Yosys::RTLIL::Sz) - .value("Sa",Yosys::RTLIL::Sa) - .value("Sm",Yosys::RTLIL::Sm) - ; + enum_("State") + .value("S0",Yosys::RTLIL::S0) + .value("S1",Yosys::RTLIL::S1) + .value("Sx",Yosys::RTLIL::Sx) + .value("Sz",Yosys::RTLIL::Sz) + .value("Sa",Yosys::RTLIL::Sa) + .value("Sm",Yosys::RTLIL::Sm) + ; - enum_("SyncType") - .value("ST0",Yosys::RTLIL::ST0) - .value("ST1",Yosys::RTLIL::ST1) - .value("STp",Yosys::RTLIL::STp) - .value("STn",Yosys::RTLIL::STn) - .value("STe",Yosys::RTLIL::STe) - .value("STa",Yosys::RTLIL::STa) - .value("STg",Yosys::RTLIL::STg) - .value("STi",Yosys::RTLIL::STi) - ; + enum_("SyncType") + .value("ST0",Yosys::RTLIL::ST0) + .value("ST1",Yosys::RTLIL::ST1) + .value("STp",Yosys::RTLIL::STp) + .value("STn",Yosys::RTLIL::STn) + .value("STe",Yosys::RTLIL::STe) + .value("STa",Yosys::RTLIL::STa) + .value("STg",Yosys::RTLIL::STg) + .value("STi",Yosys::RTLIL::STi) + ; - enum_("ConstFlags") - .value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE) - .value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING) - .value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED) - .value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL) - ; + enum_("ConstFlags") + .value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE) + .value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING) + .value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED) + .value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL) + ; class_("Monitor") - .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) - .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) - .def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell) - .def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple) - .def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list) - .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) - ; + .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) + .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) + .def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell) + .def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple) + .def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list) + .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + ; class_("Pass", init()) - .def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute) - .def("py_help", &PyPass::py_help, &PassWrap::default_py_help) - ; + .def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute) + .def("py_help", &PyPass::py_help, &PassWrap::default_py_help) + ; class_("Initializer"); scope().attr("_hidden") = new Initializer(); @@ -3772,7 +3772,6 @@ namespace YOSYS_PYTHON { def("const_pow", const_pow); def("const_pos", const_pos); def("const_neg", const_neg); - def("run",run); def("log",log); From 0ecfffa69c753b3d86d4d0e63311ed5b5cf2ab61 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 22 Aug 2018 14:42:42 +0200 Subject: [PATCH 26/57] Do not pass heap object to Python. This way they should be completely managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function --- kernel/python_wrappers.cc | 660 +++++++++++++++++++------------------- 1 file changed, 337 insertions(+), 323 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 5ca4e6e6a..d50c83a57 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -39,6 +39,7 @@ namespace YOSYS_PYTHON { Yosys::log("%s",text.c_str()); } + //WRAPPED from kernel/rtlil struct IdString { Yosys::RTLIL::IdString* ref_obj; @@ -113,6 +114,7 @@ namespace YOSYS_PYTHON { ostr << ref.ref_obj->str(); return ostr; } + //WRAPPED from kernel/rtlil struct Const { Yosys::RTLIL::Const* ref_obj; @@ -185,6 +187,7 @@ namespace YOSYS_PYTHON { ostr << ref.ref_obj->as_string(); return ostr; } + //WRAPPED from kernel/rtlil struct CaseRule { Yosys::RTLIL::CaseRule* ref_obj; @@ -218,6 +221,7 @@ namespace YOSYS_PYTHON { ostr << "CaseRule object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct SwitchRule { Yosys::RTLIL::SwitchRule* ref_obj; @@ -251,6 +255,7 @@ namespace YOSYS_PYTHON { ostr << "SwitchRule object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct SyncRule { Yosys::RTLIL::SyncRule* ref_obj; @@ -284,6 +289,7 @@ namespace YOSYS_PYTHON { ostr << "SyncRule object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct Process { Yosys::RTLIL::Process* ref_obj; @@ -317,6 +323,7 @@ namespace YOSYS_PYTHON { ostr << "Process with name " << ref.ref_obj->name.c_str(); return ostr; } + //WRAPPED from kernel/rtlil struct SigChunk { Yosys::RTLIL::SigChunk* ref_obj; @@ -356,6 +363,7 @@ namespace YOSYS_PYTHON { ostr << "SigChunk object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct SigBit { Yosys::RTLIL::SigBit* ref_obj; @@ -395,6 +403,7 @@ namespace YOSYS_PYTHON { ostr << "SigBit object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct SigSpec { Yosys::RTLIL::SigSpec* ref_obj; @@ -560,6 +569,7 @@ namespace YOSYS_PYTHON { ostr << "SigSpec object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct Cell { unsigned int hashidx_; @@ -624,6 +634,7 @@ namespace YOSYS_PYTHON { ostr << "deleted Cell"; return ostr; } + //WRAPPED from kernel/rtlil struct Wire { unsigned int hashidx_; @@ -655,6 +666,7 @@ namespace YOSYS_PYTHON { ostr << "deleted Wire"; return ostr; } + //WRAPPED from kernel/rtlil struct Memory { unsigned int hashidx_; @@ -686,6 +698,7 @@ namespace YOSYS_PYTHON { ostr << "deleted Memory"; return ostr; } + //WRAPPED from kernel/rtlil struct Module { unsigned int hashidx_; @@ -715,7 +728,7 @@ namespace YOSYS_PYTHON { } for(auto &mod_it : cpp_obj->cells_) { - result.append(new Cell(mod_it.second)); + result.append(Cell(mod_it.second)); } return result; } @@ -730,7 +743,7 @@ namespace YOSYS_PYTHON { } for(auto &mod_it : cpp_obj->wires_) { - result.append(new Wire(mod_it.second)); + result.append(Wire(mod_it.second)); } return result; } @@ -1199,6 +1212,7 @@ namespace YOSYS_PYTHON { ostr << "deleted Module"; return ostr; } + //WRAPPED from kernel/rtlil struct Design { unsigned int hashidx_; @@ -1228,7 +1242,7 @@ namespace YOSYS_PYTHON { } for(auto &mod_it : cpp_obj->modules_) { - result.append(new Module(mod_it.second)); + result.append(Module(mod_it.second)); } return result; } @@ -1313,229 +1327,229 @@ namespace YOSYS_PYTHON { return ostr; } - //WRAPPED static inline std::string escape_id(std::string str) { + //WRAPPED static inline std::string escape_id(std::string str) { FROM FILE kernel/rtlil.h inline std::string escape_id(std::string str) { return Yosys::RTLIL::escape_id(str); } - //WRAPPED static inline std::string unescape_id(std::string str) { + //WRAPPED static inline std::string unescape_id(std::string str) { FROM FILE kernel/rtlil.h inline std::string unescape_id_std_string(std::string str) { return Yosys::RTLIL::unescape_id(str); } - //WRAPPED static inline std::string unescape_id(RTLIL::IdString str) { + //WRAPPED static inline std::string unescape_id(RTLIL::IdString str) { FROM FILE kernel/rtlil.h inline std::string unescape_id_IdString(IdString *str) { return Yosys::RTLIL::unescape_id(*str->get_cpp_obj()); } - //WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_bool(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_bool(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_logic_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_logic_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_logic_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_logic_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_logic_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_logic_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_shl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_shl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_shr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_shr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_sshl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_sshl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_sshr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_sshr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_shift(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_shift(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_shiftx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_shiftx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_lt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_lt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_le(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_le(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_eq(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_eq(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_ne(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_ne(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_eqx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_eqx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_nex(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_nex(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_ge(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_ge(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_gt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_gt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_add(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_add(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_sub(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_sub(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_mul(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_mul(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_div(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_div(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_mod(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_mod(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_pow(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_pow(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_pos(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_pos(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_neg(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); @@ -1546,19 +1560,19 @@ namespace YOSYS_PYTHON { virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE { - py_notify_module_add(new Module(module)); + py_notify_module_add(Module(module)); } virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE { - py_notify_module_del(new Module(module)); + py_notify_module_del(Module(module)); } virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE { Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); - py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig)); + py_notify_connect_cell(Cell(cell), IdString(tmp_port), SigSpec(tmp_old_sig), SigSpec(&sig)); delete tmp_port; delete tmp_old_sig; } @@ -1567,7 +1581,7 @@ namespace YOSYS_PYTHON { { Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); - py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second))); + py_notify_connect_tuple(Module(module), boost::python::make_tuple(SigSpec(first), SigSpec(second))); delete first; delete second; } @@ -1576,26 +1590,26 @@ namespace YOSYS_PYTHON { { boost::python::list sigsig_list; for(auto sigsig : sigsig_vec) - sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second))); - py_notify_connect_list(new Module(module), sigsig_list); + sigsig_list.append(boost::python::make_tuple(SigSpec(&sigsig.first), SigSpec(&sigsig.second))); + py_notify_connect_list(Module(module), sigsig_list); } virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE { - py_notify_blackout(new Module(module)); + py_notify_blackout(Module(module)); } - virtual void py_notify_module_add(Module*){}; - virtual void py_notify_module_del(Module*){}; - virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){}; - virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; - virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; - virtual void py_notify_blackout(Module*){}; + virtual void py_notify_module_add(Module){}; + virtual void py_notify_module_del(Module){}; + virtual void py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig){}; + virtual void py_notify_connect_tuple(Module module, boost::python::tuple sigsig){}; + virtual void py_notify_connect_list(Module module, boost::python::list sigsig_list){}; + virtual void py_notify_blackout(Module){}; }; struct MonitorWrap : Monitor, boost::python::wrapper { - void py_notify_module_add(Module* m) + void py_notify_module_add(Module m) { if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) py_notify_module_add(m); @@ -1603,12 +1617,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_module_add(m); } - void default_py_notify_module_add(Module* m) + void default_py_notify_module_add(Module m) { this->Monitor::py_notify_module_add(m); } - void py_notify_module_del(Module* m) + void py_notify_module_del(Module m) { if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) py_notify_module_del(m); @@ -1616,12 +1630,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_module_del(m); } - void default_py_notify_module_del(Module* m) + void default_py_notify_module_del(Module m) { this->Monitor::py_notify_module_del(m); } - void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + void py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig) { if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) py_notify_connect_cell(cell, port, old_sig, sig); @@ -1629,12 +1643,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_connect_cell(cell, port, old_sig, sig); } - void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + void default_py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig) { this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); } - void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + void py_notify_connect_tuple(Module module, boost::python::tuple sigsig) { if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) py_notify_connect_tuple(module, sigsig); @@ -1642,12 +1656,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_connect_tuple(module, sigsig); } - void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + void default_py_notify_connect_tuple(Module module, boost::python::tuple sigsig) { this->Monitor::py_notify_connect_tuple(module, sigsig); } - void py_notify_connect_list(Module* module, boost::python::list sigsig_list) + void py_notify_connect_list(Module module, boost::python::list sigsig_list) { if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) py_notify_connect_list(module, sigsig_list); @@ -1655,12 +1669,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_connect_list(module, sigsig_list); } - void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list) + void default_py_notify_connect_list(Module module, boost::python::list sigsig_list) { this->Monitor::py_notify_connect_list(module, sigsig_list); } - void py_notify_blackout(Module* m) + void py_notify_blackout(Module m) { if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) py_notify_blackout(m); @@ -1668,7 +1682,7 @@ namespace YOSYS_PYTHON { Monitor::py_notify_blackout(m); } - void default_py_notify_blackout(Module* m) + void default_py_notify_blackout(Module m) { this->Monitor::py_notify_blackout(m); } @@ -1743,67 +1757,67 @@ namespace YOSYS_PYTHON { cpp_design->monitors.insert(m); } - //WRAPPED static inline int get_reference(int idx) + //WRAPPED static inline int get_reference(int idx) FROM FILE kernel/rtlil.h inline int IdString::get_reference(int idx) { return Yosys::RTLIL::IdString::get_reference(idx); } - //WRAPPED static inline void put_reference(int idx) + //WRAPPED static inline void put_reference(int idx) FROM FILE kernel/rtlil.h inline void IdString::put_reference(int idx) { Yosys::RTLIL::IdString::put_reference(idx); } - //WRAPPED std::string str() const { + //WRAPPED std::string str() const { FROM FILE kernel/rtlil.h std::string IdString::str() { return this->get_cpp_obj()->str(); } - //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { + //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { FROM FILE kernel/rtlil.h std::string IdString::substr(size_t pos, size_t len) { return this->get_cpp_obj()->substr(pos, len); } - //WRAPPED size_t size() const { + //WRAPPED size_t size() const { FROM FILE kernel/rtlil.h size_t IdString::size() { return this->get_cpp_obj()->size(); } - //WRAPPED bool empty() const { + //WRAPPED bool empty() const { FROM FILE kernel/rtlil.h bool IdString::empty() { return this->get_cpp_obj()->empty(); } - //WRAPPED void clear() { + //WRAPPED void clear() { FROM FILE kernel/rtlil.h void IdString::clear() { this->get_cpp_obj()->clear(); } - //WRAPPED unsigned int hash() const { + //WRAPPED unsigned int hash() const { FROM FILE kernel/rtlil.h unsigned int IdString::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED bool in(IdString rhs) const { return *this == rhs; } + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } FROM FILE kernel/rtlil.h bool IdString::in_IdString(IdString *rhs) { return this->get_cpp_obj()->in(*rhs->get_cpp_obj()); } - //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } + //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } FROM FILE kernel/rtlil.h bool IdString::in_std_string(std::string rhs) { return this->get_cpp_obj()->in(rhs); } - //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } + //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } FROM FILE kernel/rtlil.h bool IdString::in_pool_IdString(boost::python::list *rhs) { pool rhs_; @@ -1813,169 +1827,169 @@ namespace YOSYS_PYTHON { return this->get_cpp_obj()->in(rhs_); } - //WRAPPED bool as_bool() const; + //WRAPPED bool as_bool() const; FROM FILE kernel/rtlil.h bool Const::as_bool() { return this->get_cpp_obj()->as_bool(); } - //WRAPPED int as_int(bool is_signed = false) const; + //WRAPPED int as_int(bool is_signed = false) const; FROM FILE kernel/rtlil.h int Const::as_int(bool is_signed) { return this->get_cpp_obj()->as_int(is_signed); } - //WRAPPED std::string as_string() const; + //WRAPPED std::string as_string() const; FROM FILE kernel/rtlil.h std::string Const::as_string() { return this->get_cpp_obj()->as_string(); } - //WRAPPED static Const from_string(std::string str); + //WRAPPED static Const from_string(std::string str); FROM FILE kernel/rtlil.h Const Const::from_string(std::string str) { return Const(Yosys::RTLIL::Const::from_string(str)); } - //WRAPPED std::string decode_string() const; + //WRAPPED std::string decode_string() const; FROM FILE kernel/rtlil.h std::string Const::decode_string() { return this->get_cpp_obj()->decode_string(); } - //WRAPPED inline int size() const { return bits.size(); } + //WRAPPED inline int size() const { return bits.size(); } FROM FILE kernel/rtlil.h inline int Const::size() { return this->get_cpp_obj()->size(); } - //WRAPPED bool is_fully_zero() const; + //WRAPPED bool is_fully_zero() const; FROM FILE kernel/rtlil.h bool Const::is_fully_zero() { return this->get_cpp_obj()->is_fully_zero(); } - //WRAPPED bool is_fully_ones() const; + //WRAPPED bool is_fully_ones() const; FROM FILE kernel/rtlil.h bool Const::is_fully_ones() { return this->get_cpp_obj()->is_fully_ones(); } - //WRAPPED bool is_fully_def() const; + //WRAPPED bool is_fully_def() const; FROM FILE kernel/rtlil.h bool Const::is_fully_def() { return this->get_cpp_obj()->is_fully_def(); } - //WRAPPED bool is_fully_undef() const; + //WRAPPED bool is_fully_undef() const; FROM FILE kernel/rtlil.h bool Const::is_fully_undef() { return this->get_cpp_obj()->is_fully_undef(); } - //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { FROM FILE kernel/rtlil.h inline Const Const::extract(int offset, int len, State padding) { return Const(this->get_cpp_obj()->extract(offset, len, padding)); } - //WRAPPED inline unsigned int hash() const { + //WRAPPED inline unsigned int hash() const { FROM FILE kernel/rtlil.h inline unsigned int Const::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED RTLIL::CaseRule *clone() const; + //WRAPPED RTLIL::CaseRule *clone() const; FROM FILE kernel/rtlil.h CaseRule CaseRule::clone() { return CaseRule(this->get_cpp_obj()->clone()); } - //WRAPPED RTLIL::SwitchRule *clone() const; + //WRAPPED RTLIL::SwitchRule *clone() const; FROM FILE kernel/rtlil.h SwitchRule SwitchRule::clone() { return SwitchRule(this->get_cpp_obj()->clone()); } - //WRAPPED RTLIL::SyncRule *clone() const; + //WRAPPED RTLIL::SyncRule *clone() const; FROM FILE kernel/rtlil.h SyncRule SyncRule::clone() { return SyncRule(this->get_cpp_obj()->clone()); } - //WRAPPED RTLIL::Process *clone() const; + //WRAPPED RTLIL::Process *clone() const; FROM FILE kernel/rtlil.h Process Process::clone() { return Process(this->get_cpp_obj()->clone()); } - //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; + //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; FROM FILE kernel/rtlil.h SigChunk SigChunk::extract(int offset, int length) { return SigChunk(this->get_cpp_obj()->extract(offset, length)); } - //WRAPPED unsigned int hash() const; + //WRAPPED unsigned int hash() const; FROM FILE kernel/rtlil.h unsigned int SigBit::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED size_t get_hash() const { + //WRAPPED size_t get_hash() const { FROM FILE kernel/rtlil.h size_t SigSpec::get_hash() { return this->get_cpp_obj()->get_hash(); } - //WRAPPED inline int size() const { return width_; } + //WRAPPED inline int size() const { return width_; } FROM FILE kernel/rtlil.h inline int SigSpec::size() { return this->get_cpp_obj()->size(); } - //WRAPPED inline bool empty() const { return width_ == 0; } + //WRAPPED inline bool empty() const { return width_ == 0; } FROM FILE kernel/rtlil.h inline bool SigSpec::empty() { return this->get_cpp_obj()->empty(); } - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); FROM FILE kernel/rtlil.h void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with) { this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj()); } - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h void SigSpec::replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other) { this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj(), other->get_cpp_obj()); } - //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); + //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); FROM FILE kernel/rtlil.h void SigSpec::replace_int_SigSpec(int offset, SigSpec *with) { this->get_cpp_obj()->replace(offset, *with->get_cpp_obj()); } - //WRAPPED void remove(const RTLIL::SigSpec &pattern); + //WRAPPED void remove(const RTLIL::SigSpec &pattern); FROM FILE kernel/rtlil.h void SigSpec::remove_SigSpec(SigSpec *pattern) { this->get_cpp_obj()->remove(*pattern->get_cpp_obj()); } - //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; + //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h void SigSpec::remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) { this->get_cpp_obj()->remove(*pattern->get_cpp_obj(), other->get_cpp_obj()); } - //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); + //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h void SigSpec::remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) { this->get_cpp_obj()->remove2(*pattern->get_cpp_obj(), other->get_cpp_obj()); } - //WRAPPED void remove(const pool &pattern); + //WRAPPED void remove(const pool &pattern); FROM FILE kernel/rtlil.h void SigSpec::remove_pool_SigBit(boost::python::list *pattern) { pool pattern_; @@ -1985,7 +1999,7 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->remove(pattern_); } - //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; + //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) { pool pattern_; @@ -1995,7 +2009,7 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj()); } - //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); + //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) { pool pattern_; @@ -2005,19 +2019,19 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj()); } - //WRAPPED void remove(int offset, int length = 1); + //WRAPPED void remove(int offset, int length = 1); FROM FILE kernel/rtlil.h void SigSpec::remove_int_int(int offset, int length) { this->get_cpp_obj()->remove(offset, length); } - //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; + //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h SigSpec SigSpec::extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) { return SigSpec(this->get_cpp_obj()->extract(*pattern->get_cpp_obj(), other->get_cpp_obj())); } - //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; + //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) { pool pattern_; @@ -2027,265 +2041,265 @@ namespace YOSYS_PYTHON { return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj())); } - //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; + //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; FROM FILE kernel/rtlil.h SigSpec SigSpec::extract_int_int(int offset, int length) { return SigSpec(this->get_cpp_obj()->extract(offset, length)); } - //WRAPPED void append(const RTLIL::SigSpec &signal); + //WRAPPED void append(const RTLIL::SigSpec &signal); FROM FILE kernel/rtlil.h void SigSpec::append(SigSpec *signal) { this->get_cpp_obj()->append(*signal->get_cpp_obj()); } - //WRAPPED void append_bit(const RTLIL::SigBit &bit); + //WRAPPED void append_bit(const RTLIL::SigBit &bit); FROM FILE kernel/rtlil.h void SigSpec::append_bit(SigBit *bit) { this->get_cpp_obj()->append_bit(*bit->get_cpp_obj()); } - //WRAPPED void extend_u0(int width, bool is_signed = false); + //WRAPPED void extend_u0(int width, bool is_signed = false); FROM FILE kernel/rtlil.h void SigSpec::extend_u0(int width, bool is_signed) { this->get_cpp_obj()->extend_u0(width, is_signed); } - //WRAPPED RTLIL::SigSpec repeat(int num) const; + //WRAPPED RTLIL::SigSpec repeat(int num) const; FROM FILE kernel/rtlil.h SigSpec SigSpec::repeat(int num) { return SigSpec(this->get_cpp_obj()->repeat(num)); } - //WRAPPED bool is_wire() const; + //WRAPPED bool is_wire() const; FROM FILE kernel/rtlil.h bool SigSpec::is_wire() { return this->get_cpp_obj()->is_wire(); } - //WRAPPED bool is_chunk() const; + //WRAPPED bool is_chunk() const; FROM FILE kernel/rtlil.h bool SigSpec::is_chunk() { return this->get_cpp_obj()->is_chunk(); } - //WRAPPED inline bool is_bit() const { return width_ == 1; } + //WRAPPED inline bool is_bit() const { return width_ == 1; } FROM FILE kernel/rtlil.h inline bool SigSpec::is_bit() { return this->get_cpp_obj()->is_bit(); } - //WRAPPED bool is_fully_const() const; + //WRAPPED bool is_fully_const() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_const() { return this->get_cpp_obj()->is_fully_const(); } - //WRAPPED bool is_fully_zero() const; + //WRAPPED bool is_fully_zero() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_zero() { return this->get_cpp_obj()->is_fully_zero(); } - //WRAPPED bool is_fully_ones() const; + //WRAPPED bool is_fully_ones() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_ones() { return this->get_cpp_obj()->is_fully_ones(); } - //WRAPPED bool is_fully_def() const; + //WRAPPED bool is_fully_def() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_def() { return this->get_cpp_obj()->is_fully_def(); } - //WRAPPED bool is_fully_undef() const; + //WRAPPED bool is_fully_undef() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_undef() { return this->get_cpp_obj()->is_fully_undef(); } - //WRAPPED bool has_const() const; + //WRAPPED bool has_const() const; FROM FILE kernel/rtlil.h bool SigSpec::has_const() { return this->get_cpp_obj()->has_const(); } - //WRAPPED bool has_marked_bits() const; + //WRAPPED bool has_marked_bits() const; FROM FILE kernel/rtlil.h bool SigSpec::has_marked_bits() { return this->get_cpp_obj()->has_marked_bits(); } - //WRAPPED bool as_bool() const; + //WRAPPED bool as_bool() const; FROM FILE kernel/rtlil.h bool SigSpec::as_bool() { return this->get_cpp_obj()->as_bool(); } - //WRAPPED int as_int(bool is_signed = false) const; + //WRAPPED int as_int(bool is_signed = false) const; FROM FILE kernel/rtlil.h int SigSpec::as_int(bool is_signed) { return this->get_cpp_obj()->as_int(is_signed); } - //WRAPPED std::string as_string() const; + //WRAPPED std::string as_string() const; FROM FILE kernel/rtlil.h std::string SigSpec::as_string() { return this->get_cpp_obj()->as_string(); } - //WRAPPED RTLIL::Const as_const() const; + //WRAPPED RTLIL::Const as_const() const; FROM FILE kernel/rtlil.h Const SigSpec::as_const() { return Const(this->get_cpp_obj()->as_const()); } - //WRAPPED RTLIL::Wire *as_wire() const; + //WRAPPED RTLIL::Wire *as_wire() const; FROM FILE kernel/rtlil.h Wire SigSpec::as_wire() { return Wire(this->get_cpp_obj()->as_wire()); } - //WRAPPED RTLIL::SigChunk as_chunk() const; + //WRAPPED RTLIL::SigChunk as_chunk() const; FROM FILE kernel/rtlil.h SigChunk SigSpec::as_chunk() { return SigChunk(this->get_cpp_obj()->as_chunk()); } - //WRAPPED RTLIL::SigBit as_bit() const; + //WRAPPED RTLIL::SigBit as_bit() const; FROM FILE kernel/rtlil.h SigBit SigSpec::as_bit() { return SigBit(this->get_cpp_obj()->as_bit()); } - //WRAPPED bool match(std::string pattern) const; + //WRAPPED bool match(std::string pattern) const; FROM FILE kernel/rtlil.h bool SigSpec::match(std::string pattern) { return this->get_cpp_obj()->match(pattern); } - //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h bool SigSpec::parse(SigSpec *sig, Module *module, std::string str) { return Yosys::RTLIL::SigSpec::parse(*sig->get_cpp_obj(), module->get_cpp_obj(), str); } - //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); + //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h bool SigSpec::parse_sel(SigSpec *sig, Design *design, Module *module, std::string str) { return Yosys::RTLIL::SigSpec::parse_sel(*sig->get_cpp_obj(), design->get_cpp_obj(), module->get_cpp_obj(), str); } - //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h bool SigSpec::parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str) { return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); } - //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; + //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; FROM FILE kernel/rtlil.h unsigned int SigSpec::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED void check() const; + //WRAPPED void check() const; FROM FILE kernel/rtlil.h void SigSpec::check() { this->get_cpp_obj()->check(); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Cell::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED bool hasPort(RTLIL::IdString portname) const; + //WRAPPED bool hasPort(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h bool Cell::hasPort(IdString *portname) { return this->get_cpp_obj()->hasPort(*portname->get_cpp_obj()); } - //WRAPPED void unsetPort(RTLIL::IdString portname); + //WRAPPED void unsetPort(RTLIL::IdString portname); FROM FILE kernel/rtlil.h void Cell::unsetPort(IdString *portname) { this->get_cpp_obj()->unsetPort(*portname->get_cpp_obj()); } - //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); + //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); FROM FILE kernel/rtlil.h void Cell::setPort(IdString *portname, SigSpec *signal) { this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj()); } - //WRAPPED bool known() const; + //WRAPPED bool known() const; FROM FILE kernel/rtlil.h bool Cell::known() { return this->get_cpp_obj()->known(); } - //WRAPPED bool input(RTLIL::IdString portname) const; + //WRAPPED bool input(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h bool Cell::input(IdString *portname) { return this->get_cpp_obj()->input(*portname->get_cpp_obj()); } - //WRAPPED bool output(RTLIL::IdString portname) const; + //WRAPPED bool output(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h bool Cell::output(IdString *portname) { return this->get_cpp_obj()->output(*portname->get_cpp_obj()); } - //WRAPPED bool hasParam(RTLIL::IdString paramname) const; + //WRAPPED bool hasParam(RTLIL::IdString paramname) const; FROM FILE kernel/rtlil.h bool Cell::hasParam(IdString *paramname) { return this->get_cpp_obj()->hasParam(*paramname->get_cpp_obj()); } - //WRAPPED void unsetParam(RTLIL::IdString paramname); + //WRAPPED void unsetParam(RTLIL::IdString paramname); FROM FILE kernel/rtlil.h void Cell::unsetParam(IdString *paramname) { this->get_cpp_obj()->unsetParam(*paramname->get_cpp_obj()); } - //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); + //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); FROM FILE kernel/rtlil.h void Cell::setParam(IdString *paramname, Const *value) { this->get_cpp_obj()->setParam(*paramname->get_cpp_obj(), *value->get_cpp_obj()); } - //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); FROM FILE kernel/rtlil.h void Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed); } - //WRAPPED bool has_keep_attr() const { + //WRAPPED bool has_keep_attr() const { FROM FILE kernel/rtlil.h bool Cell::has_keep_attr() { return this->get_cpp_obj()->has_keep_attr(); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Wire::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Memory::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Module::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED void connect(const RTLIL::SigSig &conn); + //WRAPPED void connect(const RTLIL::SigSig &conn); FROM FILE kernel/rtlil.h void Module::connect_SigSig(PyObject* conn) { if(!PyTuple_Check(conn) or PyTuple_Size(conn) != 2) @@ -2296,13 +2310,13 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->connect(conn_); } - //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); FROM FILE kernel/rtlil.h void Module::connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs) { this->get_cpp_obj()->connect(*lhs->get_cpp_obj(), *rhs->get_cpp_obj()); } - //WRAPPED void new_connections(const std::vector &new_conn); + //WRAPPED void new_connections(const std::vector &new_conn); FROM FILE kernel/rtlil.h void Module::new_connections(boost::python::list *new_conn) { std::vector new_conn_; @@ -2312,49 +2326,49 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->new_connections(new_conn_); } - //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; + //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; FROM FILE kernel/rtlil.h void Module::cloneInto(Module *new_mod) { this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj()); } - //WRAPPED bool has_memories() const; + //WRAPPED bool has_memories() const; FROM FILE kernel/rtlil.h bool Module::has_memories() { return this->get_cpp_obj()->has_memories(); } - //WRAPPED bool has_processes() const; + //WRAPPED bool has_processes() const; FROM FILE kernel/rtlil.h bool Module::has_processes() { return this->get_cpp_obj()->has_processes(); } - //WRAPPED bool has_memories_warn() const; + //WRAPPED bool has_memories_warn() const; FROM FILE kernel/rtlil.h bool Module::has_memories_warn() { return this->get_cpp_obj()->has_memories_warn(); } - //WRAPPED bool has_processes_warn() const; + //WRAPPED bool has_processes_warn() const; FROM FILE kernel/rtlil.h bool Module::has_processes_warn() { return this->get_cpp_obj()->has_processes_warn(); } - //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } + //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } FROM FILE kernel/rtlil.h Wire Module::wire(IdString *id) { return Wire(this->get_cpp_obj()->wire(*id->get_cpp_obj())); } - //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } + //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } FROM FILE kernel/rtlil.h Cell Module::cell(IdString *id) { return Cell(this->get_cpp_obj()->cell(*id->get_cpp_obj())); } - //WRAPPED void remove(const pool &wires); + //WRAPPED void remove(const pool &wires); FROM FILE kernel/rtlil.h void Module::remove_pool_Wire(boost::python::list *wires) { pool wires_; @@ -2364,955 +2378,955 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->remove(wires_); } - //WRAPPED void remove(RTLIL::Cell *cell); + //WRAPPED void remove(RTLIL::Cell *cell); FROM FILE kernel/rtlil.h void Module::remove_Cell(Cell *cell) { this->get_cpp_obj()->remove(cell->get_cpp_obj()); } - //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); + //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h void Module::rename_Wire_IdString(Wire *wire, IdString *new_name) { this->get_cpp_obj()->rename(wire->get_cpp_obj(), *new_name->get_cpp_obj()); } - //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); + //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h void Module::rename_Cell_IdString(Cell *cell, IdString *new_name) { this->get_cpp_obj()->rename(cell->get_cpp_obj(), *new_name->get_cpp_obj()); } - //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h void Module::rename_IdString_IdString(IdString *old_name, IdString *new_name) { this->get_cpp_obj()->rename(*old_name->get_cpp_obj(), *new_name->get_cpp_obj()); } - //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); + //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); FROM FILE kernel/rtlil.h void Module::swap_names_Wire_Wire(Wire *w1, Wire *w2) { this->get_cpp_obj()->swap_names(w1->get_cpp_obj(), w2->get_cpp_obj()); } - //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); FROM FILE kernel/rtlil.h void Module::swap_names_Cell_Cell(Cell *c1, Cell *c2) { this->get_cpp_obj()->swap_names(c1->get_cpp_obj(), c2->get_cpp_obj()); } - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); FROM FILE kernel/rtlil.h IdString Module::uniquify_IdString(IdString *name) { return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj())); } - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); FROM FILE kernel/rtlil.h IdString Module::uniquify_IdString_int(IdString *name, int index) { return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj(), index)); } - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); FROM FILE kernel/rtlil.h Wire Module::addWire_IdString_int(IdString *name, int width) { return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), width)); } - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); FROM FILE kernel/rtlil.h Wire Module::addWire_IdString_Wire(IdString *name, Wire *other) { return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), other->get_cpp_obj())); } - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); FROM FILE kernel/rtlil.h Cell Module::addCell_IdString_IdString(IdString *name, IdString *type) { return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), *type->get_cpp_obj())); } - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); FROM FILE kernel/rtlil.h Cell Module::addCell_IdString_Cell(IdString *name, Cell *other) { return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), other->get_cpp_obj())); } - //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addPos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addNeg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addShl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addShr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addSshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addSshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addShift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addShiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addEq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addNe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addEqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addNex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addGe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addGt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addAdd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addSub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addMul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addDiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addMod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed, bool b_signed, std::string src) { return Cell(this->get_cpp_obj()->addPow(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), a_signed, b_signed, src)); } - //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addMux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addPmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src) { return Cell(this->get_cpp_obj()->addSlice(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *offset->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addConcat(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src) { return Cell(this->get_cpp_obj()->addLut(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *lut->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addTribuf(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addAssert(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addAssume(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addLive(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addFair(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addCover(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addEquiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity, bool clr_polarity, std::string src) { return Cell(this->get_cpp_obj()->addSr(*name->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_q->get_cpp_obj(), set_polarity, clr_polarity, src)); } - //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) { return Cell(this->get_cpp_obj()->addFf(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); } - //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); } - //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); } - //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addBufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addNotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addAndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addNandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addOrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addNorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addXorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addXnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addAndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addOrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addMuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addAoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addOai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addAoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addOai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) { return Cell(this->get_cpp_obj()->addFfGate(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); } - //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); } - //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); } - //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Not(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Pos(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Pos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Neg(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Neg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->And(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Or(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Xor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Xnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Shl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Shr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Sshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Sshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Shift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Shiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Lt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Le(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Eq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Ne(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Eqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Nex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Ge(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Gt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Add(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Sub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Mul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Div(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Mod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::LogicNot(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->LogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->LogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->LogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) { return SigSpec(this->get_cpp_obj()->Mux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) { return SigSpec(this->get_cpp_obj()->Pmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::BufGate(IdString *name, SigBit *sig_a, std::string src) { return SigBit(this->get_cpp_obj()->BufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::NotGate(IdString *name, SigBit *sig_a, std::string src) { return SigBit(this->get_cpp_obj()->NotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->AndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->NandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->OrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->NorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->XorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->XnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->AndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->OrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); + //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src) { return SigBit(this->get_cpp_obj()->MuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) { return SigBit(this->get_cpp_obj()->Aoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) { return SigBit(this->get_cpp_obj()->Oai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) { return SigBit(this->get_cpp_obj()->Aoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) { return SigBit(this->get_cpp_obj()->Oai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Anyconst(IdString *name, int width, std::string src) { return SigSpec(this->get_cpp_obj()->Anyconst(*name->get_cpp_obj(), width, src)); } - //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Anyseq(IdString *name, int width, std::string src) { return SigSpec(this->get_cpp_obj()->Anyseq(*name->get_cpp_obj(), width, src)); } - //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Allconst(IdString *name, int width, std::string src) { return SigSpec(this->get_cpp_obj()->Allconst(*name->get_cpp_obj(), width, src)); } - //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Allseq(IdString *name, int width, std::string src) { return SigSpec(this->get_cpp_obj()->Allseq(*name->get_cpp_obj(), width, src)); } - //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Initstate(IdString *name, std::string src) { return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src)); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Design::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED RTLIL::Module *module(RTLIL::IdString name); + //WRAPPED RTLIL::Module *module(RTLIL::IdString name); FROM FILE kernel/rtlil.h Module Design::module(IdString *name) { return Module(this->get_cpp_obj()->module(*name->get_cpp_obj())); } - //WRAPPED bool has(RTLIL::IdString id) const { + //WRAPPED bool has(RTLIL::IdString id) const { FROM FILE kernel/rtlil.h bool Design::has(IdString *id) { return this->get_cpp_obj()->has(*id->get_cpp_obj()); } - //WRAPPED void add(RTLIL::Module *module); + //WRAPPED void add(RTLIL::Module *module); FROM FILE kernel/rtlil.h void Design::add(Module *module) { this->get_cpp_obj()->add(module->get_cpp_obj()); } - //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); + //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); FROM FILE kernel/rtlil.h Module Design::addModule(IdString *name) { return Module(this->get_cpp_obj()->addModule(*name->get_cpp_obj())); } - //WRAPPED void remove(RTLIL::Module *module); + //WRAPPED void remove(RTLIL::Module *module); FROM FILE kernel/rtlil.h void Design::remove(Module *module) { this->get_cpp_obj()->remove(module->get_cpp_obj()); } - //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); + //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h void Design::rename(Module *module, IdString *new_name) { this->get_cpp_obj()->rename(module->get_cpp_obj(), *new_name->get_cpp_obj()); } - //WRAPPED void scratchpad_unset(std::string varname); + //WRAPPED void scratchpad_unset(std::string varname); FROM FILE kernel/rtlil.h void Design::scratchpad_unset(std::string varname) { this->get_cpp_obj()->scratchpad_unset(varname); } - //WRAPPED void scratchpad_set_int(std::string varname, int value); + //WRAPPED void scratchpad_set_int(std::string varname, int value); FROM FILE kernel/rtlil.h void Design::scratchpad_set_int(std::string varname, int value) { this->get_cpp_obj()->scratchpad_set_int(varname, value); } - //WRAPPED void scratchpad_set_bool(std::string varname, bool value); + //WRAPPED void scratchpad_set_bool(std::string varname, bool value); FROM FILE kernel/rtlil.h void Design::scratchpad_set_bool(std::string varname, bool value) { this->get_cpp_obj()->scratchpad_set_bool(varname, value); } - //WRAPPED void scratchpad_set_string(std::string varname, std::string value); + //WRAPPED void scratchpad_set_string(std::string varname, std::string value); FROM FILE kernel/rtlil.h void Design::scratchpad_set_string(std::string varname, std::string value) { this->get_cpp_obj()->scratchpad_set_string(varname, value); } - //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; + //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; FROM FILE kernel/rtlil.h int Design::scratchpad_get_int(std::string varname, int default_value) { return this->get_cpp_obj()->scratchpad_get_int(varname, default_value); } - //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; + //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; FROM FILE kernel/rtlil.h bool Design::scratchpad_get_bool(std::string varname, bool default_value) { return this->get_cpp_obj()->scratchpad_get_bool(varname, default_value); } - //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; FROM FILE kernel/rtlil.h std::string Design::scratchpad_get_string(std::string varname, std::string default_value) { return this->get_cpp_obj()->scratchpad_get_string(varname, default_value); } - //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; + //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; FROM FILE kernel/rtlil.h bool Design::selected_module_IdString(IdString *mod_name) { return this->get_cpp_obj()->selected_module(*mod_name->get_cpp_obj()); } - //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; + //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; FROM FILE kernel/rtlil.h bool Design::selected_whole_module_IdString(IdString *mod_name) { return this->get_cpp_obj()->selected_whole_module(*mod_name->get_cpp_obj()); } - //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; FROM FILE kernel/rtlil.h bool Design::selected_member(IdString *mod_name, IdString *memb_name) { return this->get_cpp_obj()->selected_member(*mod_name->get_cpp_obj(), *memb_name->get_cpp_obj()); } - //WRAPPED bool selected_module(RTLIL::Module *mod) const; + //WRAPPED bool selected_module(RTLIL::Module *mod) const; FROM FILE kernel/rtlil.h bool Design::selected_module_Module(Module *mod) { return this->get_cpp_obj()->selected_module(mod->get_cpp_obj()); } - //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; + //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; FROM FILE kernel/rtlil.h bool Design::selected_whole_module_Module(Module *mod) { return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj()); } - //WRAPPED bool full_selection() const { + //WRAPPED bool full_selection() const { FROM FILE kernel/rtlil.h bool Design::full_selection() { return this->get_cpp_obj()->full_selection(); From ba18e0f81aa8beeb3f6c82b5584d4c3e227c612b Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 23 Aug 2018 13:57:37 +0200 Subject: [PATCH 27/57] Fixed segfault / multiple free issue with lists --- kernel/python_wrappers.cc | 64 +++++++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 26 deletions(-) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index d50c83a57..be95ef23d 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -100,7 +100,7 @@ namespace YOSYS_PYTHON { bool in_std_string(std::string rhs); //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } - bool in_pool_IdString(boost::python::list *rhs); + bool in_pool_IdString(boost::python::list rhs); bool operator<(IdString rhs) { return get_cpp_obj() &pattern); - void remove_pool_SigBit(boost::python::list *pattern); + void remove_pool_SigBit(boost::python::list pattern); //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; - void remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + void remove_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); - void remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + void remove2_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); //WRAPPED void remove(int offset, int length = 1); void remove_int_int(int offset, int length = 1); @@ -471,7 +471,7 @@ namespace YOSYS_PYTHON { SigSpec extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; - SigSpec extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + SigSpec extract_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; SigSpec extract_int_int(int offset, int length = 1); @@ -760,7 +760,7 @@ namespace YOSYS_PYTHON { void connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs); //WRAPPED void new_connections(const std::vector &new_conn); - void new_connections(boost::python::list *new_conn); + void new_connections(boost::python::list new_conn); //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; void cloneInto(Module *new_mod); @@ -784,7 +784,7 @@ namespace YOSYS_PYTHON { Cell cell(IdString *id); //WRAPPED void remove(const pool &wires); - void remove_pool_Wire(boost::python::list *wires); + void remove_pool_Wire(boost::python::list wires); //WRAPPED void remove(RTLIL::Cell *cell); void remove_Cell(Cell *cell); @@ -1573,8 +1573,6 @@ namespace YOSYS_PYTHON { Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); py_notify_connect_cell(Cell(cell), IdString(tmp_port), SigSpec(tmp_old_sig), SigSpec(&sig)); - delete tmp_port; - delete tmp_old_sig; } virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE @@ -1582,15 +1580,13 @@ namespace YOSYS_PYTHON { Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); py_notify_connect_tuple(Module(module), boost::python::make_tuple(SigSpec(first), SigSpec(second))); - delete first; - delete second; } virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE { boost::python::list sigsig_list; for(auto sigsig : sigsig_vec) - sigsig_list.append(boost::python::make_tuple(SigSpec(&sigsig.first), SigSpec(&sigsig.second))); + sigsig_list.append(boost::python::make_tuple(*(new SigSpec(&sigsig.first)), *(new SigSpec(&sigsig.second)))); py_notify_connect_list(Module(module), sigsig_list); } @@ -1818,11 +1814,13 @@ namespace YOSYS_PYTHON { } //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } FROM FILE kernel/rtlil.h - bool IdString::in_pool_IdString(boost::python::list *rhs) + bool IdString::in_pool_IdString(boost::python::list rhs) { pool rhs_; - for(int i = 0; i < len(*rhs); ++i) + while(len(rhs) > 0) { + IdString tmp = boost::python::extract(rhs.pop()); + rhs_.insert(*tmp.get_cpp_obj()); } return this->get_cpp_obj()->in(rhs_); } @@ -1990,31 +1988,37 @@ namespace YOSYS_PYTHON { } //WRAPPED void remove(const pool &pattern); FROM FILE kernel/rtlil.h - void SigSpec::remove_pool_SigBit(boost::python::list *pattern) + void SigSpec::remove_pool_SigBit(boost::python::list pattern) { pool pattern_; - for(int i = 0; i < len(*pattern); ++i) + while(len(pattern) > 0) { + SigBit tmp = boost::python::extract(pattern.pop()); + pattern_.insert(*tmp.get_cpp_obj()); } this->get_cpp_obj()->remove(pattern_); } //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h - void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) { pool pattern_; - for(int i = 0; i < len(*pattern); ++i) + while(len(pattern) > 0) { + SigBit tmp = boost::python::extract(pattern.pop()); + pattern_.insert(*tmp.get_cpp_obj()); } this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj()); } //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h - void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) { pool pattern_; - for(int i = 0; i < len(*pattern); ++i) + while(len(pattern) > 0) { + SigBit tmp = boost::python::extract(pattern.pop()); + pattern_.insert(*tmp.get_cpp_obj()); } this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj()); } @@ -2032,11 +2036,13 @@ namespace YOSYS_PYTHON { } //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) { pool pattern_; - for(int i = 0; i < len(*pattern); ++i) + while(len(pattern) > 0) { + SigBit tmp = boost::python::extract(pattern.pop()); + pattern_.insert(*tmp.get_cpp_obj()); } return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj())); } @@ -2317,11 +2323,15 @@ namespace YOSYS_PYTHON { } //WRAPPED void new_connections(const std::vector &new_conn); FROM FILE kernel/rtlil.h - void Module::new_connections(boost::python::list *new_conn) + void Module::new_connections(boost::python::list new_conn) { std::vector new_conn_; - for(int i = 0; i < len(*new_conn); ++i) + while(len(new_conn) > 0) { + boost::python::tuple tmp1 = boost::python::extract(new_conn.pop()); + SigSpec tmp2 = boost::python::extract(tmp1[0]); + SigSpec tmp3 = boost::python::extract(tmp1[1]); + new_conn_.push_back(Yosys::RTLIL::SigSig(*tmp2.get_cpp_obj(), *tmp3.get_cpp_obj())); } this->get_cpp_obj()->new_connections(new_conn_); } @@ -2369,11 +2379,13 @@ namespace YOSYS_PYTHON { } //WRAPPED void remove(const pool &wires); FROM FILE kernel/rtlil.h - void Module::remove_pool_Wire(boost::python::list *wires) + void Module::remove_pool_Wire(boost::python::list wires) { pool wires_; - for(int i = 0; i < len(*wires); ++i) + while(len(wires) > 0) { + Wire tmp = boost::python::extract(wires.pop()); + wires_.insert(tmp.get_cpp_obj()); } this->get_cpp_obj()->remove(wires_); } From 586d7df7e266b439c81f01266f8daf24be532b55 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 23 Aug 2018 14:39:44 +0200 Subject: [PATCH 28/57] added default yosys license text --- kernel/python_wrappers.cc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index be95ef23d..da438e4c6 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -1,3 +1,22 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + #ifdef WITH_PYTHON #include "yosys.h" From 604734b484f17b87f434506acc0d627cee39c0c2 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 23 Aug 2018 14:48:20 +0200 Subject: [PATCH 29/57] added functions whose definitions are split over multiple lines --- kernel/python_wrappers.cc | 60 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index da438e4c6..7e4525a9a 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -994,9 +994,18 @@ namespace YOSYS_PYTHON { //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); Cell addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addDffsr(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); + Cell addAdff(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, Const *arst_value, bool clk_polarity = true, bool arst_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); Cell addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addDlatchsr(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); Cell addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); @@ -1051,9 +1060,18 @@ namespace YOSYS_PYTHON { //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); Cell addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addDffsrGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); + Cell addAdffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); Cell addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addDlatchsrGate(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); SigSpec Not(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); @@ -2787,12 +2805,30 @@ namespace YOSYS_PYTHON { return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); } + //WRAPPED RTLIL::Cell* addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addDffsr(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffsr(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, set_polarity, clr_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addAdff(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, Const *arst_value, bool clk_polarity, bool arst_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addAdff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_arst->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), *arst_value->get_cpp_obj(), clk_polarity, arst_polarity, src)); + } + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); } + //WRAPPED RTLIL::Cell* addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addDlatchsr(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDlatchsr(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, set_polarity, clr_polarity, src)); + } + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) { @@ -2901,12 +2937,30 @@ namespace YOSYS_PYTHON { return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); } + //WRAPPED RTLIL::Cell* addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addDffsrGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffsrGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, set_polarity, clr_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addAdffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, bool arst_value, bool clk_polarity, bool arst_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addAdffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_arst->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), arst_value, clk_polarity, arst_polarity, src)); + } + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); } + //WRAPPED RTLIL::Cell* addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addDlatchsrGate(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDlatchsrGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, set_polarity, clr_polarity, src)); + } + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { @@ -3673,7 +3727,10 @@ namespace YOSYS_PYTHON { .def("addFf", &Module::addFf) .def("addDff", &Module::addDff) .def("addDffe", &Module::addDffe) + .def("addDffsr", &Module::addDffsr) + .def("addAdff", &Module::addAdff) .def("addDlatch", &Module::addDlatch) + .def("addDlatchsr", &Module::addDlatchsr) .def("addBufGate", &Module::addBufGate) .def("addNotGate", &Module::addNotGate) .def("addAndGate", &Module::addAndGate) @@ -3692,7 +3749,10 @@ namespace YOSYS_PYTHON { .def("addFfGate", &Module::addFfGate) .def("addDffGate", &Module::addDffGate) .def("addDffeGate", &Module::addDffeGate) + .def("addDffsrGate", &Module::addDffsrGate) + .def("addAdffGate", &Module::addAdffGate) .def("addDlatchGate", &Module::addDlatchGate) + .def("addDlatchsrGate", &Module::addDlatchsrGate) .def("Not", &Module::Not) .def("Pos", &Module::Pos) .def("Neg", &Module::Neg) From 6f8abc11435abae7d3632a891bfa216da4c27acc Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 19 Sep 2018 10:32:34 +0200 Subject: [PATCH 30/57] Exposed generator script to make-process --- Makefile | 22 +- kernel/cost.h | 4 +- kernel/python_wrappers.cc | 3886 ------------------------------------- 3 files changed, 19 insertions(+), 3893 deletions(-) delete mode 100644 kernel/python_wrappers.cc diff --git a/Makefile b/Makefile index 6466bddf2..e1d66e566 100644 --- a/Makefile +++ b/Makefile @@ -23,7 +23,7 @@ PYTHON_VERSION := 3.5 # other configuration flags ENABLE_GPROF := 0 -ENABLE_DEBUG := 1 +ENABLE_DEBUG := 0 ENABLE_NDEBUG := 0 LINK_CURSES := 0 LINK_TERMCAP := 0 @@ -65,8 +65,8 @@ all: top-all YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST))) VPATH := $(YOSYS_SRC) -CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -D_YOSYS_ -fPIC -I$(PREFIX)/include -LDFLAGS := $(LDFLAGS) -L$(LIBDIR) +CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -D_YOSYS_ -fPIC -I$(PREFIX)/include -ferror-limit=0 +LDFLAGS := $(LDFLAGS) -L$(LIBDIR) -ferror-limit=0 LDLIBS := $(LDLIBS) -lstdc++ -lm PLUGIN_LDFLAGS := @@ -235,7 +235,10 @@ endif ifeq ($(ENABLE_PYTHON),1) LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON -OBJS += kernel/python_wrappers.o +PY_WRAPPER_FILE = kernel/python_wrappers +OBJS += $(PY_WRAPPER_FILE).o +PY_GEN_SCRIPT= py_wrap_generator +PY_WRAP_INCLUDES := $(shell python$(PYTHON_VERSION) -c "import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).print_includes()") endif ifeq ($(ENABLE_READLINE),1) @@ -474,6 +477,14 @@ libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) $(Q) mkdir -p $(dir $@) $(P) $(CXX) -o $@ -c $(CPPFLAGS) $(CXXFLAGS) $< +%.pyh: %.h + $(Q) mkdir -p $(dir $@) + $(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(LD) -x c++ -o $@ -E -P $(CPPFLAGS) $(CXXFLAGS) -Qunused-arguments - + +$(PY_WRAPPER_FILE).cc: $(PY_GEN_SCRIPT).py $(PY_WRAP_INCLUDES) + $(Q) mkdir -p $(dir $@) + $(P) python$(PYTHON_VERSION) -c "import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).gen_wrappers(\"$(PY_WRAPPER_FILE).cc\")" + %.o: %.cpp $(Q) mkdir -p $(dir $@) $(P) $(CXX) -o $@ -c $(CPPFLAGS) $(CXXFLAGS) $< @@ -610,8 +621,9 @@ manual: $(TARGETS) $(EXTRA_TARGETS) clean: rm -rf share + rm -rf kernel/*.pyh if test -d manual; then cd manual && sh clean.sh; fi - rm -f $(OBJS) $(GENFILES) $(TARGETS) $(EXTRA_TARGETS) $(EXTRA_OBJS) + rm -f $(OBJS) $(GENFILES) $(TARGETS) $(EXTRA_TARGETS) $(EXTRA_OBJS) $(PY_WRAP_INCLUDES) $(PY_WRAPPER_FILE).cc rm -f kernel/version_*.o kernel/version_*.cc abc/abc-[0-9a-f]* abc/libabc-[0-9a-f]*.a rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log diff --git a/kernel/cost.h b/kernel/cost.h index e795b571b..41a09eb63 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache = nullptr); -int get_cell_cost(RTLIL::IdString type, const dict ¶meters = dict(), +inline int get_cell_cost(RTLIL::IdString type, const dict ¶meters = dict(), RTLIL::Design *design = nullptr, dict *mod_cost_cache = nullptr) { static dict gate_cost = { @@ -76,7 +76,7 @@ int get_cell_cost(RTLIL::IdString type, const dict *mod_cost_cache) +inline int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache) { return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache); } diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc deleted file mode 100644 index 7e4525a9a..000000000 --- a/kernel/python_wrappers.cc +++ /dev/null @@ -1,3886 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifdef WITH_PYTHON - -#include "yosys.h" -#include -#include -#include -#include -#include -#include - -using namespace Yosys; - -namespace YOSYS_PYTHON { - - struct IdString; - struct Const; - struct CaseRule; - struct SwitchRule; - struct SyncRule; - struct Process; - struct SigChunk; - struct SigBit; - struct SigSpec; - struct Cell; - struct Wire; - struct Memory; - struct Module; - struct Design; - struct Monitor; - typedef Yosys::RTLIL::State State; - - void run(std::string command) - { - Yosys::run_pass(command); - } - - void log(std::string text) - { - Yosys::log("%s",text.c_str()); - } - - //WRAPPED from kernel/rtlil - struct IdString - { - Yosys::RTLIL::IdString* ref_obj; - - IdString(Yosys::RTLIL::IdString* ref = new Yosys::RTLIL::IdString()) - { - this->ref_obj = new Yosys::RTLIL::IdString(*ref); - } - - ~IdString() - { - delete(this->ref_obj); - } - - IdString(Yosys::RTLIL::IdString ref) - { - this->ref_obj = new Yosys::RTLIL::IdString(ref); - } - - IdString(const std::string &str) - { - this->ref_obj = new Yosys::RTLIL::IdString(str); - } - - Yosys::RTLIL::IdString* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED static inline int get_reference(int idx) - static int get_reference(int idx); - - //WRAPPED static inline void put_reference(int idx) - static void put_reference(int idx); - - //WRAPPED std::string str() const { - std::string str(); - - //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { - std::string substr(size_t pos = 0, size_t len = std::string::npos); - - //WRAPPED size_t size() const { - size_t size(); - - //WRAPPED bool empty() const { - bool empty(); - - //WRAPPED void clear() { - void clear(); - - //WRAPPED unsigned int hash() const { - unsigned int hash(); - - //WRAPPED bool in(IdString rhs) const { return *this == rhs; } - bool in_IdString(IdString *rhs); - - //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } - bool in_std_string(std::string rhs); - - //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } - bool in_pool_IdString(boost::python::list rhs); - - bool operator<(IdString rhs) { return get_cpp_obj() str(); - return ostr; - } - //WRAPPED from kernel/rtlil - struct Const - { - Yosys::RTLIL::Const* ref_obj; - - Const(Yosys::RTLIL::Const* ref = new Yosys::RTLIL::Const()) - { - this->ref_obj = new Yosys::RTLIL::Const(*ref); - } - - ~Const() - { - delete(this->ref_obj); - } - - Const(Yosys::RTLIL::Const ref) - { - this->ref_obj = new Yosys::RTLIL::Const(ref); - } - - Yosys::RTLIL::Const* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED bool as_bool() const; - bool as_bool(); - - //WRAPPED int as_int(bool is_signed = false) const; - int as_int(bool is_signed = false); - - //WRAPPED std::string as_string() const; - std::string as_string(); - - //WRAPPED static Const from_string(std::string str); - static Const from_string(std::string str); - - //WRAPPED std::string decode_string() const; - std::string decode_string(); - - //WRAPPED inline int size() const { return bits.size(); } - int size(); - - //WRAPPED bool is_fully_zero() const; - bool is_fully_zero(); - - //WRAPPED bool is_fully_ones() const; - bool is_fully_ones(); - - //WRAPPED bool is_fully_def() const; - bool is_fully_def(); - - //WRAPPED bool is_fully_undef() const; - bool is_fully_undef(); - - //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { - Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); - - //WRAPPED inline unsigned int hash() const { - unsigned int hash(); - - bool operator<(Const rhs) { return get_cpp_obj() as_string(); - return ostr; - } - //WRAPPED from kernel/rtlil - struct CaseRule - { - Yosys::RTLIL::CaseRule* ref_obj; - - CaseRule(Yosys::RTLIL::CaseRule* ref = new Yosys::RTLIL::CaseRule()) - { - this->ref_obj = ref->clone(); - } - - ~CaseRule() - { - delete(this->ref_obj); - } - - CaseRule(Yosys::RTLIL::CaseRule ref) - { - this->ref_obj = ref.clone(); - } - - Yosys::RTLIL::CaseRule* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::CaseRule *clone() const; - CaseRule clone(); - }; - - std::ostream &operator<<(std::ostream &ostr, const CaseRule &ref) - { - ostr << "CaseRule object at " << ref.ref_obj; - return ostr; - } - //WRAPPED from kernel/rtlil - struct SwitchRule - { - Yosys::RTLIL::SwitchRule* ref_obj; - - SwitchRule(Yosys::RTLIL::SwitchRule* ref = new Yosys::RTLIL::SwitchRule()) - { - this->ref_obj = ref->clone(); - } - - ~SwitchRule() - { - delete(this->ref_obj); - } - - SwitchRule(Yosys::RTLIL::SwitchRule ref) - { - this->ref_obj = ref.clone(); - } - - Yosys::RTLIL::SwitchRule* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::SwitchRule *clone() const; - SwitchRule clone(); - }; - - std::ostream &operator<<(std::ostream &ostr, const SwitchRule &ref) - { - ostr << "SwitchRule object at " << ref.ref_obj; - return ostr; - } - //WRAPPED from kernel/rtlil - struct SyncRule - { - Yosys::RTLIL::SyncRule* ref_obj; - - SyncRule(Yosys::RTLIL::SyncRule* ref = new Yosys::RTLIL::SyncRule()) - { - this->ref_obj = ref->clone(); - } - - ~SyncRule() - { - delete(this->ref_obj); - } - - SyncRule(Yosys::RTLIL::SyncRule ref) - { - this->ref_obj = ref.clone(); - } - - Yosys::RTLIL::SyncRule* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::SyncRule *clone() const; - SyncRule clone(); - }; - - std::ostream &operator<<(std::ostream &ostr, const SyncRule &ref) - { - ostr << "SyncRule object at " << ref.ref_obj; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Process - { - Yosys::RTLIL::Process* ref_obj; - - Process(Yosys::RTLIL::Process* ref = new Yosys::RTLIL::Process()) - { - this->ref_obj = ref->clone(); - } - - ~Process() - { - delete(this->ref_obj); - } - - Process(Yosys::RTLIL::Process ref) - { - this->ref_obj = ref.clone(); - } - - Yosys::RTLIL::Process* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::Process *clone() const; - Process clone(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Process &ref) - { - ostr << "Process with name " << ref.ref_obj->name.c_str(); - return ostr; - } - //WRAPPED from kernel/rtlil - struct SigChunk - { - Yosys::RTLIL::SigChunk* ref_obj; - - SigChunk(Yosys::RTLIL::SigChunk* ref = new Yosys::RTLIL::SigChunk()) - { - this->ref_obj = new Yosys::RTLIL::SigChunk(*ref); - } - - ~SigChunk() - { - delete(this->ref_obj); - } - - SigChunk(Yosys::RTLIL::SigChunk ref) - { - this->ref_obj = new Yosys::RTLIL::SigChunk(ref); - } - - Yosys::RTLIL::SigChunk* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; - SigChunk extract(int offset, int length); - - bool operator<(SigChunk rhs) { return get_cpp_obj() ref_obj = new Yosys::RTLIL::SigBit(*ref); - } - - ~SigBit() - { - delete(this->ref_obj); - } - - SigBit(Yosys::RTLIL::SigBit ref) - { - this->ref_obj = new Yosys::RTLIL::SigBit(ref); - } - - Yosys::RTLIL::SigBit* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED unsigned int hash() const; - unsigned int hash(); - - bool operator<(SigBit rhs) { return get_cpp_obj() ref_obj = new Yosys::RTLIL::SigSpec(*ref); - } - - ~SigSpec() - { - delete(this->ref_obj); - } - - SigSpec(Yosys::RTLIL::SigSpec ref) - { - this->ref_obj = new Yosys::RTLIL::SigSpec(ref); - } - - Yosys::RTLIL::SigSpec* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED size_t get_hash() const { - size_t get_hash(); - - //WRAPPED inline int size() const { return width_; } - int size(); - - //WRAPPED inline bool empty() const { return width_ == 0; } - bool empty(); - - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); - void replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with); - - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; - void replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other); - - //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); - void replace_int_SigSpec(int offset, SigSpec *with); - - //WRAPPED void remove(const RTLIL::SigSpec &pattern); - void remove_SigSpec(SigSpec *pattern); - - //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; - void remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); - - //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); - void remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); - - //WRAPPED void remove(const pool &pattern); - void remove_pool_SigBit(boost::python::list pattern); - - //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; - void remove_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); - - //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); - void remove2_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); - - //WRAPPED void remove(int offset, int length = 1); - void remove_int_int(int offset, int length = 1); - - //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; - SigSpec extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); - - //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; - SigSpec extract_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); - - //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; - SigSpec extract_int_int(int offset, int length = 1); - - //WRAPPED void append(const RTLIL::SigSpec &signal); - void append(SigSpec *signal); - - //WRAPPED void append_bit(const RTLIL::SigBit &bit); - void append_bit(SigBit *bit); - - //WRAPPED void extend_u0(int width, bool is_signed = false); - void extend_u0(int width, bool is_signed = false); - - //WRAPPED RTLIL::SigSpec repeat(int num) const; - SigSpec repeat(int num); - - //WRAPPED bool is_wire() const; - bool is_wire(); - - //WRAPPED bool is_chunk() const; - bool is_chunk(); - - //WRAPPED inline bool is_bit() const { return width_ == 1; } - bool is_bit(); - - //WRAPPED bool is_fully_const() const; - bool is_fully_const(); - - //WRAPPED bool is_fully_zero() const; - bool is_fully_zero(); - - //WRAPPED bool is_fully_ones() const; - bool is_fully_ones(); - - //WRAPPED bool is_fully_def() const; - bool is_fully_def(); - - //WRAPPED bool is_fully_undef() const; - bool is_fully_undef(); - - //WRAPPED bool has_const() const; - bool has_const(); - - //WRAPPED bool has_marked_bits() const; - bool has_marked_bits(); - - //WRAPPED bool as_bool() const; - bool as_bool(); - - //WRAPPED int as_int(bool is_signed = false) const; - int as_int(bool is_signed = false); - - //WRAPPED std::string as_string() const; - std::string as_string(); - - //WRAPPED RTLIL::Const as_const() const; - Const as_const(); - - //WRAPPED RTLIL::Wire *as_wire() const; - Wire as_wire(); - - //WRAPPED RTLIL::SigChunk as_chunk() const; - SigChunk as_chunk(); - - //WRAPPED RTLIL::SigBit as_bit() const; - SigBit as_bit(); - - //WRAPPED bool match(std::string pattern) const; - bool match(std::string pattern); - - //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); - static bool parse(SigSpec *sig, Module *module, std::string str); - - //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); - static bool parse_sel(SigSpec *sig, Design *design, Module *module, std::string str); - - //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); - static bool parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str); - - //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; - unsigned int hash(); - - //WRAPPED void check() const; - void check(); - - bool operator<(SigSpec rhs) { return get_cpp_obj() hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Cell* get_cpp_obj() const - { - Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - - //WRAPPED bool hasPort(RTLIL::IdString portname) const; - bool hasPort(IdString *portname); - - //WRAPPED void unsetPort(RTLIL::IdString portname); - void unsetPort(IdString *portname); - - //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); - void setPort(IdString *portname, SigSpec *signal); - - //WRAPPED bool known() const; - bool known(); - - //WRAPPED bool input(RTLIL::IdString portname) const; - bool input(IdString *portname); - - //WRAPPED bool output(RTLIL::IdString portname) const; - bool output(IdString *portname); - - //WRAPPED bool hasParam(RTLIL::IdString paramname) const; - bool hasParam(IdString *paramname); - - //WRAPPED void unsetParam(RTLIL::IdString paramname); - void unsetParam(IdString *paramname); - - //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); - void setParam(IdString *paramname, Const *value); - - //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); - void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); - - //WRAPPED bool has_keep_attr() const { - bool has_keep_attr(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Cell &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Cell with name " << ref.get_cpp_obj()->name.c_str(); - else - ostr << "deleted Cell"; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Wire - { - unsigned int hashidx_; - Yosys::RTLIL::Wire* ref_obj; - - Wire(Yosys::RTLIL::Wire* ref) - { - this->hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Wire* get_cpp_obj() const - { - Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Wire &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Wire with name " << ref.get_cpp_obj()->name.c_str(); - else - ostr << "deleted Wire"; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Memory - { - unsigned int hashidx_; - Yosys::RTLIL::Memory* ref_obj; - - Memory(Yosys::RTLIL::Memory* ref) - { - this->hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Memory* get_cpp_obj() const - { - Yosys::RTLIL::Memory* ret = Yosys::RTLIL::Memory::get_all_memorys()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Memory &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Memory with name " << ref.get_cpp_obj()->name.c_str(); - else - ostr << "deleted Memory"; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Module - { - unsigned int hashidx_; - Yosys::RTLIL::Module* ref_obj; - - Module(Yosys::RTLIL::Module* ref = new Yosys::RTLIL::Module()) - { - this->hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Module* get_cpp_obj() const - { - Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - boost::python::list get_cells() - { - Yosys::RTLIL::Module* cpp_obj = get_cpp_obj(); - boost::python::list result; - if(cpp_obj == NULL) - { - return result; - } - for(auto &mod_it : cpp_obj->cells_) - { - result.append(Cell(mod_it.second)); - } - return result; - } - - boost::python::list get_wires() - { - Yosys::RTLIL::Module* cpp_obj = get_cpp_obj(); - boost::python::list result; - if(cpp_obj == NULL) - { - return result; - } - for(auto &mod_it : cpp_obj->wires_) - { - result.append(Wire(mod_it.second)); - } - return result; - } - - void register_monitor(Monitor* const m); - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - - //WRAPPED void connect(const RTLIL::SigSig &conn); - void connect_SigSig(PyObject *conn); - - //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); - void connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs); - - //WRAPPED void new_connections(const std::vector &new_conn); - void new_connections(boost::python::list new_conn); - - //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; - void cloneInto(Module *new_mod); - - //WRAPPED bool has_memories() const; - bool has_memories(); - - //WRAPPED bool has_processes() const; - bool has_processes(); - - //WRAPPED bool has_memories_warn() const; - bool has_memories_warn(); - - //WRAPPED bool has_processes_warn() const; - bool has_processes_warn(); - - //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } - Wire wire(IdString *id); - - //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } - Cell cell(IdString *id); - - //WRAPPED void remove(const pool &wires); - void remove_pool_Wire(boost::python::list wires); - - //WRAPPED void remove(RTLIL::Cell *cell); - void remove_Cell(Cell *cell); - - //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); - void rename_Wire_IdString(Wire *wire, IdString *new_name); - - //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); - void rename_Cell_IdString(Cell *cell, IdString *new_name); - - //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); - void rename_IdString_IdString(IdString *old_name, IdString *new_name); - - //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); - void swap_names_Wire_Wire(Wire *w1, Wire *w2); - - //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); - void swap_names_Cell_Cell(Cell *c1, Cell *c2); - - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); - IdString uniquify_IdString(IdString *name); - - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); - IdString uniquify_IdString_int(IdString *name, int index); - - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); - Wire addWire_IdString_int(IdString *name, int width = 1); - - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); - Wire addWire_IdString_Wire(IdString *name, Wire *other); - - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); - Cell addCell_IdString_IdString(IdString *name, IdString *type); - - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); - Cell addCell_IdString_Cell(IdString *name, Cell *other); - - //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); - Cell addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed = false, bool b_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); - Cell addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src = ""); - - //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); - Cell addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src = ""); - - //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); - Cell addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); - Cell addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); - Cell addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addDffsr(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); - Cell addAdff(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, Const *arst_value, bool clk_polarity = true, bool arst_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); - Cell addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addDlatchsr(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); - Cell addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); - Cell addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); - Cell addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addDffsrGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); - Cell addAdffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); - Cell addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addDlatchsrGate(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec Not(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec Pos(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec Neg(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec LogicNot(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); - SigSpec Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); - SigSpec Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = ""); - - //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); - SigBit BufGate(IdString *name, SigBit *sig_a, std::string src = ""); - - //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); - SigBit NotGate(IdString *name, SigBit *sig_a, std::string src = ""); - - //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); - SigBit MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src = ""); - - //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); - SigBit Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = ""); - - //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); - SigBit Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = ""); - - //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); - SigBit Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = ""); - - //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); - SigBit Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); - SigSpec Anyconst(IdString *name, int width = 1, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); - SigSpec Anyseq(IdString *name, int width = 1, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); - SigSpec Allconst(IdString *name, int width = 1, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); - SigSpec Allseq(IdString *name, int width = 1, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); - SigSpec Initstate(IdString *name, std::string src = ""); - }; - - std::ostream &operator<<(std::ostream &ostr, const Module &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Module with name " << ref.get_cpp_obj()->name.c_str(); - else - ostr << "deleted Module"; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Design - { - unsigned int hashidx_; - Yosys::RTLIL::Design* ref_obj; - - Design(Yosys::RTLIL::Design* ref = new Yosys::RTLIL::Design()) - { - this->hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Design* get_cpp_obj() const - { - Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - boost::python::list get_modules() - { - Yosys::RTLIL::Design* cpp_obj = get_cpp_obj(); - boost::python::list result; - if(cpp_obj == NULL) - { - return result; - } - for(auto &mod_it : cpp_obj->modules_) - { - result.append(Module(mod_it.second)); - } - return result; - } - - void run(std::string command) - { - Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); - if(cpp_design != NULL) - Yosys::run_pass(command, cpp_design); - - } - - void register_monitor(Monitor* const m); - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - - //WRAPPED RTLIL::Module *module(RTLIL::IdString name); - Module module(IdString *name); - - //WRAPPED bool has(RTLIL::IdString id) const { - bool has(IdString *id); - - //WRAPPED void add(RTLIL::Module *module); - void add(Module *module); - - //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); - Module addModule(IdString *name); - - //WRAPPED void remove(RTLIL::Module *module); - void remove(Module *module); - - //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); - void rename(Module *module, IdString *new_name); - - //WRAPPED void scratchpad_unset(std::string varname); - void scratchpad_unset(std::string varname); - - //WRAPPED void scratchpad_set_int(std::string varname, int value); - void scratchpad_set_int(std::string varname, int value); - - //WRAPPED void scratchpad_set_bool(std::string varname, bool value); - void scratchpad_set_bool(std::string varname, bool value); - - //WRAPPED void scratchpad_set_string(std::string varname, std::string value); - void scratchpad_set_string(std::string varname, std::string value); - - //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; - int scratchpad_get_int(std::string varname, int default_value = 0); - - //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; - bool scratchpad_get_bool(std::string varname, bool default_value = false); - - //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; - std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()); - - //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; - bool selected_module_IdString(IdString *mod_name); - - //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; - bool selected_whole_module_IdString(IdString *mod_name); - - //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; - bool selected_member(IdString *mod_name, IdString *memb_name); - - //WRAPPED bool selected_module(RTLIL::Module *mod) const; - bool selected_module_Module(Module *mod); - - //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; - bool selected_whole_module_Module(Module *mod); - - //WRAPPED bool full_selection() const { - bool full_selection(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Design &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Design with identifier " << ref.hashidx_; - else - ostr << "deleted Design"; - return ostr; - } - - //WRAPPED static inline std::string escape_id(std::string str) { FROM FILE kernel/rtlil.h - inline std::string escape_id(std::string str) - { - return Yosys::RTLIL::escape_id(str); - } - - //WRAPPED static inline std::string unescape_id(std::string str) { FROM FILE kernel/rtlil.h - inline std::string unescape_id_std_string(std::string str) - { - return Yosys::RTLIL::unescape_id(str); - } - - //WRAPPED static inline std::string unescape_id(RTLIL::IdString str) { FROM FILE kernel/rtlil.h - inline std::string unescape_id_IdString(IdString *str) - { - return Yosys::RTLIL::unescape_id(*str->get_cpp_obj()); - } - - //WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_bool(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_bool(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_logic_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_logic_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_logic_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_logic_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_logic_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_logic_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_shl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_shl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_shr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_shr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_sshl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_sshl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_sshr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_sshr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_shift(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_shift(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_shiftx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_shiftx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_lt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_lt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_le(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_le(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_eq(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_eq(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_ne(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_ne(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_eqx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_eqx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_nex(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_nex(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_ge(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_ge(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_gt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_gt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_add(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_add(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_sub(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_sub(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_mul(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_mul(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_div(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_div(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_mod(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_mod(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_pow(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_pow(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_pos(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_pos(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_neg(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - struct Monitor : public Yosys::RTLIL::Monitor - { - - virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_add(Module(module)); - } - - virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_del(Module(module)); - } - - virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE - { - Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); - Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); - py_notify_connect_cell(Cell(cell), IdString(tmp_port), SigSpec(tmp_old_sig), SigSpec(&sig)); - } - - virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE - { - Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); - Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); - py_notify_connect_tuple(Module(module), boost::python::make_tuple(SigSpec(first), SigSpec(second))); - } - - virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE - { - boost::python::list sigsig_list; - for(auto sigsig : sigsig_vec) - sigsig_list.append(boost::python::make_tuple(*(new SigSpec(&sigsig.first)), *(new SigSpec(&sigsig.second)))); - py_notify_connect_list(Module(module), sigsig_list); - } - - virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_blackout(Module(module)); - } - - virtual void py_notify_module_add(Module){}; - virtual void py_notify_module_del(Module){}; - virtual void py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig){}; - virtual void py_notify_connect_tuple(Module module, boost::python::tuple sigsig){}; - virtual void py_notify_connect_list(Module module, boost::python::list sigsig_list){}; - virtual void py_notify_blackout(Module){}; - }; - - struct MonitorWrap : Monitor, boost::python::wrapper - { - void py_notify_module_add(Module m) - { - if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) - py_notify_module_add(m); - else - Monitor::py_notify_module_add(m); - } - - void default_py_notify_module_add(Module m) - { - this->Monitor::py_notify_module_add(m); - } - - void py_notify_module_del(Module m) - { - if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) - py_notify_module_del(m); - else - Monitor::py_notify_module_del(m); - } - - void default_py_notify_module_del(Module m) - { - this->Monitor::py_notify_module_del(m); - } - - void py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig) - { - if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) - py_notify_connect_cell(cell, port, old_sig, sig); - else - Monitor::py_notify_connect_cell(cell, port, old_sig, sig); - } - - void default_py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig) - { - this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); - } - - void py_notify_connect_tuple(Module module, boost::python::tuple sigsig) - { - if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) - py_notify_connect_tuple(module, sigsig); - else - Monitor::py_notify_connect_tuple(module, sigsig); - } - - void default_py_notify_connect_tuple(Module module, boost::python::tuple sigsig) - { - this->Monitor::py_notify_connect_tuple(module, sigsig); - } - - void py_notify_connect_list(Module module, boost::python::list sigsig_list) - { - if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) - py_notify_connect_list(module, sigsig_list); - else - Monitor::py_notify_connect_list(module, sigsig_list); - } - - void default_py_notify_connect_list(Module module, boost::python::list sigsig_list) - { - this->Monitor::py_notify_connect_list(module, sigsig_list); - } - - void py_notify_blackout(Module m) - { - if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) - py_notify_blackout(m); - else - Monitor::py_notify_blackout(m); - } - - void default_py_notify_blackout(Module m) - { - this->Monitor::py_notify_blackout(m); - } - }; - - struct PyPass : public Yosys::Pass - { - PyPass(std::string name, std::string short_help) : Yosys::Pass(name, short_help) { } - - virtual void execute(vector args, Yosys::RTLIL::Design* d) YS_OVERRIDE - { - boost::python::list py_args; - for(auto arg : args) - py_args.append(arg); - py_execute(py_args, new Design(d)); - } - - virtual void help() YS_OVERRIDE - { - py_help(); - } - - virtual void py_execute(boost::python::list args, Design* d){} - virtual void py_help(){} - }; - - struct PassWrap : PyPass, boost::python::wrapper - { - - PassWrap(std::string name, std::string short_help) : PyPass(name, short_help) { } - - void py_execute(boost::python::list args, Design* d) - { - if(boost::python::override py_execute = this->get_override("py_execute")) - py_execute(args, d); - else - PyPass::py_execute(args, d); - } - - void default_py_execute(boost::python::list args, Design* d) - { - this->PyPass::py_execute(args, d); - } - - void py_help() - { - if(boost::python::override py_help = this->get_override("py_help")) - py_help(); - else - PyPass::py_help(); - } - - void default_py_help() - { - this->PyPass::py_help(); - } - }; - - void Module::register_monitor(Monitor* const m) - { - Yosys::RTLIL::Module* cpp_module = this->get_cpp_obj(); - if(cpp_module == NULL) - return; - cpp_module->monitors.insert(m); - } - - void Design::register_monitor(Monitor* const m) - { - Yosys::RTLIL::Design* cpp_design = this->get_cpp_obj(); - if(cpp_design == NULL) - return; - cpp_design->monitors.insert(m); - } - - //WRAPPED static inline int get_reference(int idx) FROM FILE kernel/rtlil.h - inline int IdString::get_reference(int idx) - { - return Yosys::RTLIL::IdString::get_reference(idx); - } - - //WRAPPED static inline void put_reference(int idx) FROM FILE kernel/rtlil.h - inline void IdString::put_reference(int idx) - { - Yosys::RTLIL::IdString::put_reference(idx); - } - - //WRAPPED std::string str() const { FROM FILE kernel/rtlil.h - std::string IdString::str() - { - return this->get_cpp_obj()->str(); - } - - //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { FROM FILE kernel/rtlil.h - std::string IdString::substr(size_t pos, size_t len) - { - return this->get_cpp_obj()->substr(pos, len); - } - - //WRAPPED size_t size() const { FROM FILE kernel/rtlil.h - size_t IdString::size() - { - return this->get_cpp_obj()->size(); - } - - //WRAPPED bool empty() const { FROM FILE kernel/rtlil.h - bool IdString::empty() - { - return this->get_cpp_obj()->empty(); - } - - //WRAPPED void clear() { FROM FILE kernel/rtlil.h - void IdString::clear() - { - this->get_cpp_obj()->clear(); - } - - //WRAPPED unsigned int hash() const { FROM FILE kernel/rtlil.h - unsigned int IdString::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED bool in(IdString rhs) const { return *this == rhs; } FROM FILE kernel/rtlil.h - bool IdString::in_IdString(IdString *rhs) - { - return this->get_cpp_obj()->in(*rhs->get_cpp_obj()); - } - - //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } FROM FILE kernel/rtlil.h - bool IdString::in_std_string(std::string rhs) - { - return this->get_cpp_obj()->in(rhs); - } - - //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } FROM FILE kernel/rtlil.h - bool IdString::in_pool_IdString(boost::python::list rhs) - { - pool rhs_; - while(len(rhs) > 0) - { - IdString tmp = boost::python::extract(rhs.pop()); - rhs_.insert(*tmp.get_cpp_obj()); - } - return this->get_cpp_obj()->in(rhs_); - } - - //WRAPPED bool as_bool() const; FROM FILE kernel/rtlil.h - bool Const::as_bool() - { - return this->get_cpp_obj()->as_bool(); - } - - //WRAPPED int as_int(bool is_signed = false) const; FROM FILE kernel/rtlil.h - int Const::as_int(bool is_signed) - { - return this->get_cpp_obj()->as_int(is_signed); - } - - //WRAPPED std::string as_string() const; FROM FILE kernel/rtlil.h - std::string Const::as_string() - { - return this->get_cpp_obj()->as_string(); - } - - //WRAPPED static Const from_string(std::string str); FROM FILE kernel/rtlil.h - Const Const::from_string(std::string str) - { - return Const(Yosys::RTLIL::Const::from_string(str)); - } - - //WRAPPED std::string decode_string() const; FROM FILE kernel/rtlil.h - std::string Const::decode_string() - { - return this->get_cpp_obj()->decode_string(); - } - - //WRAPPED inline int size() const { return bits.size(); } FROM FILE kernel/rtlil.h - inline int Const::size() - { - return this->get_cpp_obj()->size(); - } - - //WRAPPED bool is_fully_zero() const; FROM FILE kernel/rtlil.h - bool Const::is_fully_zero() - { - return this->get_cpp_obj()->is_fully_zero(); - } - - //WRAPPED bool is_fully_ones() const; FROM FILE kernel/rtlil.h - bool Const::is_fully_ones() - { - return this->get_cpp_obj()->is_fully_ones(); - } - - //WRAPPED bool is_fully_def() const; FROM FILE kernel/rtlil.h - bool Const::is_fully_def() - { - return this->get_cpp_obj()->is_fully_def(); - } - - //WRAPPED bool is_fully_undef() const; FROM FILE kernel/rtlil.h - bool Const::is_fully_undef() - { - return this->get_cpp_obj()->is_fully_undef(); - } - - //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { FROM FILE kernel/rtlil.h - inline Const Const::extract(int offset, int len, State padding) - { - return Const(this->get_cpp_obj()->extract(offset, len, padding)); - } - - //WRAPPED inline unsigned int hash() const { FROM FILE kernel/rtlil.h - inline unsigned int Const::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED RTLIL::CaseRule *clone() const; FROM FILE kernel/rtlil.h - CaseRule CaseRule::clone() - { - return CaseRule(this->get_cpp_obj()->clone()); - } - - //WRAPPED RTLIL::SwitchRule *clone() const; FROM FILE kernel/rtlil.h - SwitchRule SwitchRule::clone() - { - return SwitchRule(this->get_cpp_obj()->clone()); - } - - //WRAPPED RTLIL::SyncRule *clone() const; FROM FILE kernel/rtlil.h - SyncRule SyncRule::clone() - { - return SyncRule(this->get_cpp_obj()->clone()); - } - - //WRAPPED RTLIL::Process *clone() const; FROM FILE kernel/rtlil.h - Process Process::clone() - { - return Process(this->get_cpp_obj()->clone()); - } - - //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; FROM FILE kernel/rtlil.h - SigChunk SigChunk::extract(int offset, int length) - { - return SigChunk(this->get_cpp_obj()->extract(offset, length)); - } - - //WRAPPED unsigned int hash() const; FROM FILE kernel/rtlil.h - unsigned int SigBit::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED size_t get_hash() const { FROM FILE kernel/rtlil.h - size_t SigSpec::get_hash() - { - return this->get_cpp_obj()->get_hash(); - } - - //WRAPPED inline int size() const { return width_; } FROM FILE kernel/rtlil.h - inline int SigSpec::size() - { - return this->get_cpp_obj()->size(); - } - - //WRAPPED inline bool empty() const { return width_ == 0; } FROM FILE kernel/rtlil.h - inline bool SigSpec::empty() - { - return this->get_cpp_obj()->empty(); - } - - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); FROM FILE kernel/rtlil.h - void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with) - { - this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj()); - } - - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h - void SigSpec::replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other) - { - this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj(), other->get_cpp_obj()); - } - - //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); FROM FILE kernel/rtlil.h - void SigSpec::replace_int_SigSpec(int offset, SigSpec *with) - { - this->get_cpp_obj()->replace(offset, *with->get_cpp_obj()); - } - - //WRAPPED void remove(const RTLIL::SigSpec &pattern); FROM FILE kernel/rtlil.h - void SigSpec::remove_SigSpec(SigSpec *pattern) - { - this->get_cpp_obj()->remove(*pattern->get_cpp_obj()); - } - - //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h - void SigSpec::remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) - { - this->get_cpp_obj()->remove(*pattern->get_cpp_obj(), other->get_cpp_obj()); - } - - //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h - void SigSpec::remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) - { - this->get_cpp_obj()->remove2(*pattern->get_cpp_obj(), other->get_cpp_obj()); - } - - //WRAPPED void remove(const pool &pattern); FROM FILE kernel/rtlil.h - void SigSpec::remove_pool_SigBit(boost::python::list pattern) - { - pool pattern_; - while(len(pattern) > 0) - { - SigBit tmp = boost::python::extract(pattern.pop()); - pattern_.insert(*tmp.get_cpp_obj()); - } - this->get_cpp_obj()->remove(pattern_); - } - - //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h - void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) - { - pool pattern_; - while(len(pattern) > 0) - { - SigBit tmp = boost::python::extract(pattern.pop()); - pattern_.insert(*tmp.get_cpp_obj()); - } - this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj()); - } - - //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h - void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) - { - pool pattern_; - while(len(pattern) > 0) - { - SigBit tmp = boost::python::extract(pattern.pop()); - pattern_.insert(*tmp.get_cpp_obj()); - } - this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj()); - } - - //WRAPPED void remove(int offset, int length = 1); FROM FILE kernel/rtlil.h - void SigSpec::remove_int_int(int offset, int length) - { - this->get_cpp_obj()->remove(offset, length); - } - - //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) - { - return SigSpec(this->get_cpp_obj()->extract(*pattern->get_cpp_obj(), other->get_cpp_obj())); - } - - //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) - { - pool pattern_; - while(len(pattern) > 0) - { - SigBit tmp = boost::python::extract(pattern.pop()); - pattern_.insert(*tmp.get_cpp_obj()); - } - return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj())); - } - - //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::extract_int_int(int offset, int length) - { - return SigSpec(this->get_cpp_obj()->extract(offset, length)); - } - - //WRAPPED void append(const RTLIL::SigSpec &signal); FROM FILE kernel/rtlil.h - void SigSpec::append(SigSpec *signal) - { - this->get_cpp_obj()->append(*signal->get_cpp_obj()); - } - - //WRAPPED void append_bit(const RTLIL::SigBit &bit); FROM FILE kernel/rtlil.h - void SigSpec::append_bit(SigBit *bit) - { - this->get_cpp_obj()->append_bit(*bit->get_cpp_obj()); - } - - //WRAPPED void extend_u0(int width, bool is_signed = false); FROM FILE kernel/rtlil.h - void SigSpec::extend_u0(int width, bool is_signed) - { - this->get_cpp_obj()->extend_u0(width, is_signed); - } - - //WRAPPED RTLIL::SigSpec repeat(int num) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::repeat(int num) - { - return SigSpec(this->get_cpp_obj()->repeat(num)); - } - - //WRAPPED bool is_wire() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_wire() - { - return this->get_cpp_obj()->is_wire(); - } - - //WRAPPED bool is_chunk() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_chunk() - { - return this->get_cpp_obj()->is_chunk(); - } - - //WRAPPED inline bool is_bit() const { return width_ == 1; } FROM FILE kernel/rtlil.h - inline bool SigSpec::is_bit() - { - return this->get_cpp_obj()->is_bit(); - } - - //WRAPPED bool is_fully_const() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_const() - { - return this->get_cpp_obj()->is_fully_const(); - } - - //WRAPPED bool is_fully_zero() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_zero() - { - return this->get_cpp_obj()->is_fully_zero(); - } - - //WRAPPED bool is_fully_ones() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_ones() - { - return this->get_cpp_obj()->is_fully_ones(); - } - - //WRAPPED bool is_fully_def() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_def() - { - return this->get_cpp_obj()->is_fully_def(); - } - - //WRAPPED bool is_fully_undef() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_undef() - { - return this->get_cpp_obj()->is_fully_undef(); - } - - //WRAPPED bool has_const() const; FROM FILE kernel/rtlil.h - bool SigSpec::has_const() - { - return this->get_cpp_obj()->has_const(); - } - - //WRAPPED bool has_marked_bits() const; FROM FILE kernel/rtlil.h - bool SigSpec::has_marked_bits() - { - return this->get_cpp_obj()->has_marked_bits(); - } - - //WRAPPED bool as_bool() const; FROM FILE kernel/rtlil.h - bool SigSpec::as_bool() - { - return this->get_cpp_obj()->as_bool(); - } - - //WRAPPED int as_int(bool is_signed = false) const; FROM FILE kernel/rtlil.h - int SigSpec::as_int(bool is_signed) - { - return this->get_cpp_obj()->as_int(is_signed); - } - - //WRAPPED std::string as_string() const; FROM FILE kernel/rtlil.h - std::string SigSpec::as_string() - { - return this->get_cpp_obj()->as_string(); - } - - //WRAPPED RTLIL::Const as_const() const; FROM FILE kernel/rtlil.h - Const SigSpec::as_const() - { - return Const(this->get_cpp_obj()->as_const()); - } - - //WRAPPED RTLIL::Wire *as_wire() const; FROM FILE kernel/rtlil.h - Wire SigSpec::as_wire() - { - return Wire(this->get_cpp_obj()->as_wire()); - } - - //WRAPPED RTLIL::SigChunk as_chunk() const; FROM FILE kernel/rtlil.h - SigChunk SigSpec::as_chunk() - { - return SigChunk(this->get_cpp_obj()->as_chunk()); - } - - //WRAPPED RTLIL::SigBit as_bit() const; FROM FILE kernel/rtlil.h - SigBit SigSpec::as_bit() - { - return SigBit(this->get_cpp_obj()->as_bit()); - } - - //WRAPPED bool match(std::string pattern) const; FROM FILE kernel/rtlil.h - bool SigSpec::match(std::string pattern) - { - return this->get_cpp_obj()->match(pattern); - } - - //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h - bool SigSpec::parse(SigSpec *sig, Module *module, std::string str) - { - return Yosys::RTLIL::SigSpec::parse(*sig->get_cpp_obj(), module->get_cpp_obj(), str); - } - - //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h - bool SigSpec::parse_sel(SigSpec *sig, Design *design, Module *module, std::string str) - { - return Yosys::RTLIL::SigSpec::parse_sel(*sig->get_cpp_obj(), design->get_cpp_obj(), module->get_cpp_obj(), str); - } - - //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h - bool SigSpec::parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str) - { - return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); - } - - //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; FROM FILE kernel/rtlil.h - unsigned int SigSpec::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED void check() const; FROM FILE kernel/rtlil.h - void SigSpec::check() - { - this->get_cpp_obj()->check(); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Cell::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED bool hasPort(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h - bool Cell::hasPort(IdString *portname) - { - return this->get_cpp_obj()->hasPort(*portname->get_cpp_obj()); - } - - //WRAPPED void unsetPort(RTLIL::IdString portname); FROM FILE kernel/rtlil.h - void Cell::unsetPort(IdString *portname) - { - this->get_cpp_obj()->unsetPort(*portname->get_cpp_obj()); - } - - //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); FROM FILE kernel/rtlil.h - void Cell::setPort(IdString *portname, SigSpec *signal) - { - this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj()); - } - - //WRAPPED bool known() const; FROM FILE kernel/rtlil.h - bool Cell::known() - { - return this->get_cpp_obj()->known(); - } - - //WRAPPED bool input(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h - bool Cell::input(IdString *portname) - { - return this->get_cpp_obj()->input(*portname->get_cpp_obj()); - } - - //WRAPPED bool output(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h - bool Cell::output(IdString *portname) - { - return this->get_cpp_obj()->output(*portname->get_cpp_obj()); - } - - //WRAPPED bool hasParam(RTLIL::IdString paramname) const; FROM FILE kernel/rtlil.h - bool Cell::hasParam(IdString *paramname) - { - return this->get_cpp_obj()->hasParam(*paramname->get_cpp_obj()); - } - - //WRAPPED void unsetParam(RTLIL::IdString paramname); FROM FILE kernel/rtlil.h - void Cell::unsetParam(IdString *paramname) - { - this->get_cpp_obj()->unsetParam(*paramname->get_cpp_obj()); - } - - //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); FROM FILE kernel/rtlil.h - void Cell::setParam(IdString *paramname, Const *value) - { - this->get_cpp_obj()->setParam(*paramname->get_cpp_obj(), *value->get_cpp_obj()); - } - - //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); FROM FILE kernel/rtlil.h - void Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) - { - this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed); - } - - //WRAPPED bool has_keep_attr() const { FROM FILE kernel/rtlil.h - bool Cell::has_keep_attr() - { - return this->get_cpp_obj()->has_keep_attr(); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Wire::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Memory::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Module::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED void connect(const RTLIL::SigSig &conn); FROM FILE kernel/rtlil.h - void Module::connect_SigSig(PyObject* conn) - { - if(!PyTuple_Check(conn) or PyTuple_Size(conn) != 2) - throw std::logic_error("Tuple of two SigSpecs required"); - SigSpec conn_sp0 = boost::python::extract(PyTuple_GetItem(conn, 0)); - SigSpec conn_sp1 = boost::python::extract(PyTuple_GetItem(conn, 1)); - Yosys::RTLIL::SigSig conn_(conn_sp0.get_cpp_obj(), conn_sp1.get_cpp_obj()); - this->get_cpp_obj()->connect(conn_); - } - - //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); FROM FILE kernel/rtlil.h - void Module::connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs) - { - this->get_cpp_obj()->connect(*lhs->get_cpp_obj(), *rhs->get_cpp_obj()); - } - - //WRAPPED void new_connections(const std::vector &new_conn); FROM FILE kernel/rtlil.h - void Module::new_connections(boost::python::list new_conn) - { - std::vector new_conn_; - while(len(new_conn) > 0) - { - boost::python::tuple tmp1 = boost::python::extract(new_conn.pop()); - SigSpec tmp2 = boost::python::extract(tmp1[0]); - SigSpec tmp3 = boost::python::extract(tmp1[1]); - new_conn_.push_back(Yosys::RTLIL::SigSig(*tmp2.get_cpp_obj(), *tmp3.get_cpp_obj())); - } - this->get_cpp_obj()->new_connections(new_conn_); - } - - //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; FROM FILE kernel/rtlil.h - void Module::cloneInto(Module *new_mod) - { - this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj()); - } - - //WRAPPED bool has_memories() const; FROM FILE kernel/rtlil.h - bool Module::has_memories() - { - return this->get_cpp_obj()->has_memories(); - } - - //WRAPPED bool has_processes() const; FROM FILE kernel/rtlil.h - bool Module::has_processes() - { - return this->get_cpp_obj()->has_processes(); - } - - //WRAPPED bool has_memories_warn() const; FROM FILE kernel/rtlil.h - bool Module::has_memories_warn() - { - return this->get_cpp_obj()->has_memories_warn(); - } - - //WRAPPED bool has_processes_warn() const; FROM FILE kernel/rtlil.h - bool Module::has_processes_warn() - { - return this->get_cpp_obj()->has_processes_warn(); - } - - //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } FROM FILE kernel/rtlil.h - Wire Module::wire(IdString *id) - { - return Wire(this->get_cpp_obj()->wire(*id->get_cpp_obj())); - } - - //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } FROM FILE kernel/rtlil.h - Cell Module::cell(IdString *id) - { - return Cell(this->get_cpp_obj()->cell(*id->get_cpp_obj())); - } - - //WRAPPED void remove(const pool &wires); FROM FILE kernel/rtlil.h - void Module::remove_pool_Wire(boost::python::list wires) - { - pool wires_; - while(len(wires) > 0) - { - Wire tmp = boost::python::extract(wires.pop()); - wires_.insert(tmp.get_cpp_obj()); - } - this->get_cpp_obj()->remove(wires_); - } - - //WRAPPED void remove(RTLIL::Cell *cell); FROM FILE kernel/rtlil.h - void Module::remove_Cell(Cell *cell) - { - this->get_cpp_obj()->remove(cell->get_cpp_obj()); - } - - //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h - void Module::rename_Wire_IdString(Wire *wire, IdString *new_name) - { - this->get_cpp_obj()->rename(wire->get_cpp_obj(), *new_name->get_cpp_obj()); - } - - //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h - void Module::rename_Cell_IdString(Cell *cell, IdString *new_name) - { - this->get_cpp_obj()->rename(cell->get_cpp_obj(), *new_name->get_cpp_obj()); - } - - //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h - void Module::rename_IdString_IdString(IdString *old_name, IdString *new_name) - { - this->get_cpp_obj()->rename(*old_name->get_cpp_obj(), *new_name->get_cpp_obj()); - } - - //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); FROM FILE kernel/rtlil.h - void Module::swap_names_Wire_Wire(Wire *w1, Wire *w2) - { - this->get_cpp_obj()->swap_names(w1->get_cpp_obj(), w2->get_cpp_obj()); - } - - //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); FROM FILE kernel/rtlil.h - void Module::swap_names_Cell_Cell(Cell *c1, Cell *c2) - { - this->get_cpp_obj()->swap_names(c1->get_cpp_obj(), c2->get_cpp_obj()); - } - - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); FROM FILE kernel/rtlil.h - IdString Module::uniquify_IdString(IdString *name) - { - return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj())); - } - - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); FROM FILE kernel/rtlil.h - IdString Module::uniquify_IdString_int(IdString *name, int index) - { - return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj(), index)); - } - - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); FROM FILE kernel/rtlil.h - Wire Module::addWire_IdString_int(IdString *name, int width) - { - return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), width)); - } - - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); FROM FILE kernel/rtlil.h - Wire Module::addWire_IdString_Wire(IdString *name, Wire *other) - { - return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), other->get_cpp_obj())); - } - - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); FROM FILE kernel/rtlil.h - Cell Module::addCell_IdString_IdString(IdString *name, IdString *type) - { - return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), *type->get_cpp_obj())); - } - - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); FROM FILE kernel/rtlil.h - Cell Module::addCell_IdString_Cell(IdString *name, Cell *other) - { - return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), other->get_cpp_obj())); - } - - //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addPos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addNeg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addShl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addShr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addSshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addSshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addShift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addShiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addEq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addNe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addEqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addNex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addGe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addGt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addAdd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addSub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addMul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addDiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addMod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed, bool b_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addPow(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), a_signed, b_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addMux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addPmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src) - { - return Cell(this->get_cpp_obj()->addSlice(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *offset->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addConcat(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src) - { - return Cell(this->get_cpp_obj()->addLut(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *lut->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addTribuf(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addAssert(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addAssume(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addLive(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addFair(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addCover(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addEquiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addSr(*name->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_q->get_cpp_obj(), set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) - { - return Cell(this->get_cpp_obj()->addFf(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffsr(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffsr(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAdff(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, Const *arst_value, bool clk_polarity, bool arst_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addAdff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_arst->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), *arst_value->get_cpp_obj(), clk_polarity, arst_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDlatchsr(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDlatchsr(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addBufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addNotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addAndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addNandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addOrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addNorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addXorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addXnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addAndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addOrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addMuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addAoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addOai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addAoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addOai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) - { - return Cell(this->get_cpp_obj()->addFfGate(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffsrGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffsrGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAdffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, bool arst_value, bool clk_polarity, bool arst_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addAdffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_arst->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), arst_value, clk_polarity, arst_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDlatchsrGate(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDlatchsrGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Not(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Pos(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Pos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Neg(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Neg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->And(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Or(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Xor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Xnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Shl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Shr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Sshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Sshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Shift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Shiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Lt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Le(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Eq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Ne(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Eqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Nex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Ge(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Gt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Add(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Sub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Mul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Div(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Mod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::LogicNot(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->LogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->LogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->LogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) - { - return SigSpec(this->get_cpp_obj()->Mux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) - { - return SigSpec(this->get_cpp_obj()->Pmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::BufGate(IdString *name, SigBit *sig_a, std::string src) - { - return SigBit(this->get_cpp_obj()->BufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::NotGate(IdString *name, SigBit *sig_a, std::string src) - { - return SigBit(this->get_cpp_obj()->NotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->AndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->NandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->OrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->NorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->XorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->XnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->AndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->OrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src) - { - return SigBit(this->get_cpp_obj()->MuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) - { - return SigBit(this->get_cpp_obj()->Aoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) - { - return SigBit(this->get_cpp_obj()->Oai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) - { - return SigBit(this->get_cpp_obj()->Aoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) - { - return SigBit(this->get_cpp_obj()->Oai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Anyconst(IdString *name, int width, std::string src) - { - return SigSpec(this->get_cpp_obj()->Anyconst(*name->get_cpp_obj(), width, src)); - } - - //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Anyseq(IdString *name, int width, std::string src) - { - return SigSpec(this->get_cpp_obj()->Anyseq(*name->get_cpp_obj(), width, src)); - } - - //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Allconst(IdString *name, int width, std::string src) - { - return SigSpec(this->get_cpp_obj()->Allconst(*name->get_cpp_obj(), width, src)); - } - - //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Allseq(IdString *name, int width, std::string src) - { - return SigSpec(this->get_cpp_obj()->Allseq(*name->get_cpp_obj(), width, src)); - } - - //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Initstate(IdString *name, std::string src) - { - return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src)); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Design::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED RTLIL::Module *module(RTLIL::IdString name); FROM FILE kernel/rtlil.h - Module Design::module(IdString *name) - { - return Module(this->get_cpp_obj()->module(*name->get_cpp_obj())); - } - - //WRAPPED bool has(RTLIL::IdString id) const { FROM FILE kernel/rtlil.h - bool Design::has(IdString *id) - { - return this->get_cpp_obj()->has(*id->get_cpp_obj()); - } - - //WRAPPED void add(RTLIL::Module *module); FROM FILE kernel/rtlil.h - void Design::add(Module *module) - { - this->get_cpp_obj()->add(module->get_cpp_obj()); - } - - //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); FROM FILE kernel/rtlil.h - Module Design::addModule(IdString *name) - { - return Module(this->get_cpp_obj()->addModule(*name->get_cpp_obj())); - } - - //WRAPPED void remove(RTLIL::Module *module); FROM FILE kernel/rtlil.h - void Design::remove(Module *module) - { - this->get_cpp_obj()->remove(module->get_cpp_obj()); - } - - //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h - void Design::rename(Module *module, IdString *new_name) - { - this->get_cpp_obj()->rename(module->get_cpp_obj(), *new_name->get_cpp_obj()); - } - - //WRAPPED void scratchpad_unset(std::string varname); FROM FILE kernel/rtlil.h - void Design::scratchpad_unset(std::string varname) - { - this->get_cpp_obj()->scratchpad_unset(varname); - } - - //WRAPPED void scratchpad_set_int(std::string varname, int value); FROM FILE kernel/rtlil.h - void Design::scratchpad_set_int(std::string varname, int value) - { - this->get_cpp_obj()->scratchpad_set_int(varname, value); - } - - //WRAPPED void scratchpad_set_bool(std::string varname, bool value); FROM FILE kernel/rtlil.h - void Design::scratchpad_set_bool(std::string varname, bool value) - { - this->get_cpp_obj()->scratchpad_set_bool(varname, value); - } - - //WRAPPED void scratchpad_set_string(std::string varname, std::string value); FROM FILE kernel/rtlil.h - void Design::scratchpad_set_string(std::string varname, std::string value) - { - this->get_cpp_obj()->scratchpad_set_string(varname, value); - } - - //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; FROM FILE kernel/rtlil.h - int Design::scratchpad_get_int(std::string varname, int default_value) - { - return this->get_cpp_obj()->scratchpad_get_int(varname, default_value); - } - - //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; FROM FILE kernel/rtlil.h - bool Design::scratchpad_get_bool(std::string varname, bool default_value) - { - return this->get_cpp_obj()->scratchpad_get_bool(varname, default_value); - } - - //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; FROM FILE kernel/rtlil.h - std::string Design::scratchpad_get_string(std::string varname, std::string default_value) - { - return this->get_cpp_obj()->scratchpad_get_string(varname, default_value); - } - - //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; FROM FILE kernel/rtlil.h - bool Design::selected_module_IdString(IdString *mod_name) - { - return this->get_cpp_obj()->selected_module(*mod_name->get_cpp_obj()); - } - - //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; FROM FILE kernel/rtlil.h - bool Design::selected_whole_module_IdString(IdString *mod_name) - { - return this->get_cpp_obj()->selected_whole_module(*mod_name->get_cpp_obj()); - } - - //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; FROM FILE kernel/rtlil.h - bool Design::selected_member(IdString *mod_name, IdString *memb_name) - { - return this->get_cpp_obj()->selected_member(*mod_name->get_cpp_obj(), *memb_name->get_cpp_obj()); - } - - //WRAPPED bool selected_module(RTLIL::Module *mod) const; FROM FILE kernel/rtlil.h - bool Design::selected_module_Module(Module *mod) - { - return this->get_cpp_obj()->selected_module(mod->get_cpp_obj()); - } - - //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; FROM FILE kernel/rtlil.h - bool Design::selected_whole_module_Module(Module *mod) - { - return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj()); - } - - //WRAPPED bool full_selection() const { FROM FILE kernel/rtlil.h - bool Design::full_selection() - { - return this->get_cpp_obj()->full_selection(); - } - - struct Initializer - { - Initializer() { - if(!Yosys::yosys_already_setup()) - { - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; - Yosys::yosys_setup(); - Yosys::yosys_banner(); - } - } - - Initializer(Initializer const &) {} - - ~Initializer() { - Yosys::yosys_shutdown(); - } - }; - - BOOST_PYTHON_MODULE(libyosys) - { - using namespace boost::python; - - enum_("State") - .value("S0",Yosys::RTLIL::S0) - .value("S1",Yosys::RTLIL::S1) - .value("Sx",Yosys::RTLIL::Sx) - .value("Sz",Yosys::RTLIL::Sz) - .value("Sa",Yosys::RTLIL::Sa) - .value("Sm",Yosys::RTLIL::Sm) - ; - - enum_("SyncType") - .value("ST0",Yosys::RTLIL::ST0) - .value("ST1",Yosys::RTLIL::ST1) - .value("STp",Yosys::RTLIL::STp) - .value("STn",Yosys::RTLIL::STn) - .value("STe",Yosys::RTLIL::STe) - .value("STa",Yosys::RTLIL::STa) - .value("STg",Yosys::RTLIL::STg) - .value("STi",Yosys::RTLIL::STi) - ; - - enum_("ConstFlags") - .value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE) - .value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING) - .value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED) - .value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL) - ; - - class_("Monitor") - .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) - .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) - .def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell) - .def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple) - .def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list) - .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) - ; - - class_("Pass", init()) - .def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute) - .def("py_help", &PyPass::py_help, &PassWrap::default_py_help) - ; - - class_("Initializer"); - scope().attr("_hidden") = new Initializer(); - - class_("IdString") - .def(init()) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_reference", &IdString::get_reference) - .def("put_reference", &IdString::put_reference) - .def("str", &IdString::str) - .def("substr", &IdString::substr) - .def("size", &IdString::size) - .def("empty", &IdString::empty) - .def("clear", &IdString::clear) - .def("hash", &IdString::hash) - .def("in_IdString", &IdString::in_IdString) - .def("in_std_string", &IdString::in_std_string) - .def("in_pool_IdString", &IdString::in_pool_IdString) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("Const") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("as_bool", &Const::as_bool) - .def("as_int", &Const::as_int) - .def("as_string", &Const::as_string) - .def("from_string", &Const::from_string) - .def("decode_string", &Const::decode_string) - .def("size", &Const::size) - .def("is_fully_zero", &Const::is_fully_zero) - .def("is_fully_ones", &Const::is_fully_ones) - .def("is_fully_def", &Const::is_fully_def) - .def("is_fully_undef", &Const::is_fully_undef) - .def("extract", &Const::extract) - .def("hash", &Const::hash) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("CaseRule") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("clone", &CaseRule::clone) - ; - - class_("SwitchRule") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("clone", &SwitchRule::clone) - ; - - class_("SyncRule") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("clone", &SyncRule::clone) - ; - - class_("Process") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("clone", &Process::clone) - ; - - class_("SigChunk") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("extract", &SigChunk::extract) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("SigBit") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("hash", &SigBit::hash) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("SigSpec") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_hash", &SigSpec::get_hash) - .def("size", &SigSpec::size) - .def("empty", &SigSpec::empty) - .def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec) - .def("replace_SigSpec_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec_SigSpec) - .def("replace_int_SigSpec", &SigSpec::replace_int_SigSpec) - .def("remove_SigSpec", &SigSpec::remove_SigSpec) - .def("remove_SigSpec_SigSpec", &SigSpec::remove_SigSpec_SigSpec) - .def("remove2_SigSpec_SigSpec", &SigSpec::remove2_SigSpec_SigSpec) - .def("remove_pool_SigBit", &SigSpec::remove_pool_SigBit) - .def("remove_pool_SigBit_SigSpec", &SigSpec::remove_pool_SigBit_SigSpec) - .def("remove2_pool_SigBit_SigSpec", &SigSpec::remove2_pool_SigBit_SigSpec) - .def("remove_int_int", &SigSpec::remove_int_int) - .def("extract_SigSpec_SigSpec", &SigSpec::extract_SigSpec_SigSpec) - .def("extract_pool_SigBit_SigSpec", &SigSpec::extract_pool_SigBit_SigSpec) - .def("extract_int_int", &SigSpec::extract_int_int) - .def("append", &SigSpec::append) - .def("append_bit", &SigSpec::append_bit) - .def("extend_u0", &SigSpec::extend_u0) - .def("repeat", &SigSpec::repeat) - .def("is_wire", &SigSpec::is_wire) - .def("is_chunk", &SigSpec::is_chunk) - .def("is_bit", &SigSpec::is_bit) - .def("is_fully_const", &SigSpec::is_fully_const) - .def("is_fully_zero", &SigSpec::is_fully_zero) - .def("is_fully_ones", &SigSpec::is_fully_ones) - .def("is_fully_def", &SigSpec::is_fully_def) - .def("is_fully_undef", &SigSpec::is_fully_undef) - .def("has_const", &SigSpec::has_const) - .def("has_marked_bits", &SigSpec::has_marked_bits) - .def("as_bool", &SigSpec::as_bool) - .def("as_int", &SigSpec::as_int) - .def("as_string", &SigSpec::as_string) - .def("as_const", &SigSpec::as_const) - .def("as_wire", &SigSpec::as_wire) - .def("as_chunk", &SigSpec::as_chunk) - .def("as_bit", &SigSpec::as_bit) - .def("match", &SigSpec::match) - .def("parse", &SigSpec::parse) - .def("parse_sel", &SigSpec::parse_sel) - .def("parse_rhs", &SigSpec::parse_rhs) - .def("hash", &SigSpec::hash) - .def("check", &SigSpec::check) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("Cell", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("hash", &Cell::hash) - .def("hasPort", &Cell::hasPort) - .def("unsetPort", &Cell::unsetPort) - .def("setPort", &Cell::setPort) - .def("known", &Cell::known) - .def("input", &Cell::input) - .def("output", &Cell::output) - .def("hasParam", &Cell::hasParam) - .def("unsetParam", &Cell::unsetParam) - .def("setParam", &Cell::setParam) - .def("fixup_parameters", &Cell::fixup_parameters) - .def("has_keep_attr", &Cell::has_keep_attr) - ; - - class_("Wire", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("hash", &Wire::hash) - ; - - class_("Memory", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("hash", &Memory::hash) - ; - - class_("Module") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_cells", &Module::get_cells) - .def("get_wires", &Module::get_wires) - .def("register_monitor", &Module::register_monitor) - .def("hash", &Module::hash) - .def("connect_SigSig", &Module::connect_SigSig) - .def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec) - .def("new_connections", &Module::new_connections) - .def("cloneInto", &Module::cloneInto) - .def("has_memories", &Module::has_memories) - .def("has_processes", &Module::has_processes) - .def("has_memories_warn", &Module::has_memories_warn) - .def("has_processes_warn", &Module::has_processes_warn) - .def("wire", &Module::wire) - .def("cell", &Module::cell) - .def("remove_pool_Wire", &Module::remove_pool_Wire) - .def("remove_Cell", &Module::remove_Cell) - .def("rename_Wire_IdString", &Module::rename_Wire_IdString) - .def("rename_Cell_IdString", &Module::rename_Cell_IdString) - .def("rename_IdString_IdString", &Module::rename_IdString_IdString) - .def("swap_names_Wire_Wire", &Module::swap_names_Wire_Wire) - .def("swap_names_Cell_Cell", &Module::swap_names_Cell_Cell) - .def("uniquify_IdString", &Module::uniquify_IdString) - .def("uniquify_IdString_int", &Module::uniquify_IdString_int) - .def("addWire_IdString_int", &Module::addWire_IdString_int) - .def("addWire_IdString_Wire", &Module::addWire_IdString_Wire) - .def("addCell_IdString_IdString", &Module::addCell_IdString_IdString) - .def("addCell_IdString_Cell", &Module::addCell_IdString_Cell) - .def("addNot", &Module::addNot) - .def("addPos", &Module::addPos) - .def("addNeg", &Module::addNeg) - .def("addAnd", &Module::addAnd) - .def("addOr", &Module::addOr) - .def("addXor", &Module::addXor) - .def("addXnor", &Module::addXnor) - .def("addReduceAnd", &Module::addReduceAnd) - .def("addReduceOr", &Module::addReduceOr) - .def("addReduceXor", &Module::addReduceXor) - .def("addReduceXnor", &Module::addReduceXnor) - .def("addReduceBool", &Module::addReduceBool) - .def("addShl", &Module::addShl) - .def("addShr", &Module::addShr) - .def("addSshl", &Module::addSshl) - .def("addSshr", &Module::addSshr) - .def("addShift", &Module::addShift) - .def("addShiftx", &Module::addShiftx) - .def("addLt", &Module::addLt) - .def("addLe", &Module::addLe) - .def("addEq", &Module::addEq) - .def("addNe", &Module::addNe) - .def("addEqx", &Module::addEqx) - .def("addNex", &Module::addNex) - .def("addGe", &Module::addGe) - .def("addGt", &Module::addGt) - .def("addAdd", &Module::addAdd) - .def("addSub", &Module::addSub) - .def("addMul", &Module::addMul) - .def("addDiv", &Module::addDiv) - .def("addMod", &Module::addMod) - .def("addPow", &Module::addPow) - .def("addLogicNot", &Module::addLogicNot) - .def("addLogicAnd", &Module::addLogicAnd) - .def("addLogicOr", &Module::addLogicOr) - .def("addMux", &Module::addMux) - .def("addPmux", &Module::addPmux) - .def("addSlice", &Module::addSlice) - .def("addConcat", &Module::addConcat) - .def("addLut", &Module::addLut) - .def("addTribuf", &Module::addTribuf) - .def("addAssert", &Module::addAssert) - .def("addAssume", &Module::addAssume) - .def("addLive", &Module::addLive) - .def("addFair", &Module::addFair) - .def("addCover", &Module::addCover) - .def("addEquiv", &Module::addEquiv) - .def("addSr", &Module::addSr) - .def("addFf", &Module::addFf) - .def("addDff", &Module::addDff) - .def("addDffe", &Module::addDffe) - .def("addDffsr", &Module::addDffsr) - .def("addAdff", &Module::addAdff) - .def("addDlatch", &Module::addDlatch) - .def("addDlatchsr", &Module::addDlatchsr) - .def("addBufGate", &Module::addBufGate) - .def("addNotGate", &Module::addNotGate) - .def("addAndGate", &Module::addAndGate) - .def("addNandGate", &Module::addNandGate) - .def("addOrGate", &Module::addOrGate) - .def("addNorGate", &Module::addNorGate) - .def("addXorGate", &Module::addXorGate) - .def("addXnorGate", &Module::addXnorGate) - .def("addAndnotGate", &Module::addAndnotGate) - .def("addOrnotGate", &Module::addOrnotGate) - .def("addMuxGate", &Module::addMuxGate) - .def("addAoi3Gate", &Module::addAoi3Gate) - .def("addOai3Gate", &Module::addOai3Gate) - .def("addAoi4Gate", &Module::addAoi4Gate) - .def("addOai4Gate", &Module::addOai4Gate) - .def("addFfGate", &Module::addFfGate) - .def("addDffGate", &Module::addDffGate) - .def("addDffeGate", &Module::addDffeGate) - .def("addDffsrGate", &Module::addDffsrGate) - .def("addAdffGate", &Module::addAdffGate) - .def("addDlatchGate", &Module::addDlatchGate) - .def("addDlatchsrGate", &Module::addDlatchsrGate) - .def("Not", &Module::Not) - .def("Pos", &Module::Pos) - .def("Neg", &Module::Neg) - .def("And", &Module::And) - .def("Or", &Module::Or) - .def("Xor", &Module::Xor) - .def("Xnor", &Module::Xnor) - .def("ReduceAnd", &Module::ReduceAnd) - .def("ReduceOr", &Module::ReduceOr) - .def("ReduceXor", &Module::ReduceXor) - .def("ReduceXnor", &Module::ReduceXnor) - .def("ReduceBool", &Module::ReduceBool) - .def("Shl", &Module::Shl) - .def("Shr", &Module::Shr) - .def("Sshl", &Module::Sshl) - .def("Sshr", &Module::Sshr) - .def("Shift", &Module::Shift) - .def("Shiftx", &Module::Shiftx) - .def("Lt", &Module::Lt) - .def("Le", &Module::Le) - .def("Eq", &Module::Eq) - .def("Ne", &Module::Ne) - .def("Eqx", &Module::Eqx) - .def("Nex", &Module::Nex) - .def("Ge", &Module::Ge) - .def("Gt", &Module::Gt) - .def("Add", &Module::Add) - .def("Sub", &Module::Sub) - .def("Mul", &Module::Mul) - .def("Div", &Module::Div) - .def("Mod", &Module::Mod) - .def("LogicNot", &Module::LogicNot) - .def("LogicAnd", &Module::LogicAnd) - .def("LogicOr", &Module::LogicOr) - .def("Mux", &Module::Mux) - .def("Pmux", &Module::Pmux) - .def("BufGate", &Module::BufGate) - .def("NotGate", &Module::NotGate) - .def("AndGate", &Module::AndGate) - .def("NandGate", &Module::NandGate) - .def("OrGate", &Module::OrGate) - .def("NorGate", &Module::NorGate) - .def("XorGate", &Module::XorGate) - .def("XnorGate", &Module::XnorGate) - .def("AndnotGate", &Module::AndnotGate) - .def("OrnotGate", &Module::OrnotGate) - .def("MuxGate", &Module::MuxGate) - .def("Aoi3Gate", &Module::Aoi3Gate) - .def("Oai3Gate", &Module::Oai3Gate) - .def("Aoi4Gate", &Module::Aoi4Gate) - .def("Oai4Gate", &Module::Oai4Gate) - .def("Anyconst", &Module::Anyconst) - .def("Anyseq", &Module::Anyseq) - .def("Allconst", &Module::Allconst) - .def("Allseq", &Module::Allseq) - .def("Initstate", &Module::Initstate) - ; - - class_("Design") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_modules", &Design::get_modules) - .def("run", &Design::run) - .def("register_monitor", &Design::register_monitor) - .def("hash", &Design::hash) - .def("module", &Design::module) - .def("has", &Design::has) - .def("add", &Design::add) - .def("addModule", &Design::addModule) - .def("remove", &Design::remove) - .def("rename", &Design::rename) - .def("scratchpad_unset", &Design::scratchpad_unset) - .def("scratchpad_set_int", &Design::scratchpad_set_int) - .def("scratchpad_set_bool", &Design::scratchpad_set_bool) - .def("scratchpad_set_string", &Design::scratchpad_set_string) - .def("scratchpad_get_int", &Design::scratchpad_get_int) - .def("scratchpad_get_bool", &Design::scratchpad_get_bool) - .def("scratchpad_get_string", &Design::scratchpad_get_string) - .def("selected_module_IdString", &Design::selected_module_IdString) - .def("selected_whole_module_IdString", &Design::selected_whole_module_IdString) - .def("selected_member", &Design::selected_member) - .def("selected_module_Module", &Design::selected_module_Module) - .def("selected_whole_module_Module", &Design::selected_whole_module_Module) - .def("full_selection", &Design::full_selection) - ; - - def("escape_id", escape_id); - def("unescape_id_std_string", unescape_id_std_string); - def("unescape_id_IdString", unescape_id_IdString); - def("const_not", const_not); - def("const_and", const_and); - def("const_or", const_or); - def("const_xor", const_xor); - def("const_xnor", const_xnor); - def("const_reduce_and", const_reduce_and); - def("const_reduce_or", const_reduce_or); - def("const_reduce_xor", const_reduce_xor); - def("const_reduce_xnor", const_reduce_xnor); - def("const_reduce_bool", const_reduce_bool); - def("const_logic_not", const_logic_not); - def("const_logic_and", const_logic_and); - def("const_logic_or", const_logic_or); - def("const_shl", const_shl); - def("const_shr", const_shr); - def("const_sshl", const_sshl); - def("const_sshr", const_sshr); - def("const_shift", const_shift); - def("const_shiftx", const_shiftx); - def("const_lt", const_lt); - def("const_le", const_le); - def("const_eq", const_eq); - def("const_ne", const_ne); - def("const_eqx", const_eqx); - def("const_nex", const_nex); - def("const_ge", const_ge); - def("const_gt", const_gt); - def("const_add", const_add); - def("const_sub", const_sub); - def("const_mul", const_mul); - def("const_div", const_div); - def("const_mod", const_mod); - def("const_pow", const_pow); - def("const_pos", const_pos); - def("const_neg", const_neg); - def("run",run); - def("log",log); - - } - -} -#endif From 05a9adfdeb3d66ea7aad1335d8658e133b54d903 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 25 Oct 2018 12:27:56 +0200 Subject: [PATCH 31/57] added py_wrap_generator --- py_wrap_generator.py | 2098 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 2098 insertions(+) create mode 100644 py_wrap_generator.py diff --git a/py_wrap_generator.py b/py_wrap_generator.py new file mode 100644 index 000000000..204b9146c --- /dev/null +++ b/py_wrap_generator.py @@ -0,0 +1,2098 @@ +# +# yosys -- Yosys Open SYnthesis Suite +# +# Copyright (C) 2012 Clifford Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# +# Author Benedikt Tutzer +# + +import copy + +#Map c++ operator Syntax to Python functions +wrappable_operators = { + "<" : "__lt__", + "==": "__eq__", + "!=": "__ne__", + "+" : "__add__", + "-" : "__sub__", + "*" : "__mul__", + "/" : "__div__", + "()": "__call__" + } + +#Restrict certain strings from being function names in Python +keyword_aliases = { + "in" : "in_", + "False" : "False_", + "None" : "None_", + "True" : "True_", + "and" : "and_", + "as" : "as_", + "assert" : "assert_", + "break" : "break_", + "class" : "class_", + "continue" : "continue_", + "def" : "def_", + "del" : "del_", + "elif" : "elif_", + "else" : "else_", + "except" : "except_", + "for" : "for_", + "from" : "from_", + "global" : "global_", + "if" : "if_", + "import" : "import_", + "in" : "in_", + "is" : "is_", + "lambda" : "lambda_", + "nonlocal" : "nonlocal_", + "not" : "not_", + "or" : "or_", + "pass" : "pass_", + "raise" : "raise_", + "return" : "return_", + "try" : "try_", + "while" : "while_", + "with" : "with_", + "yield" : "yield_" + } + +#These can be used without any explicit conversion +primitive_types = ["void", "bool", "int", "double", "size_t", "std::string", + "string", "State", "char_p"] + +from enum import Enum + +#Ways to link between Python- and C++ Objects +class link_types(Enum): + global_list = 1 #Manage a global list of objects in C++, the Python + #object contains a key to find the corresponding C++ + #object and a Pointer to the object to verify it is + #still the same, making collisions unlikely to happen + ref_copy = 2 #The Python object contains a copy of the C++ object. + #The C++ object is deleted when the Python object gets + #deleted + pointer = 3 #The Python Object contains a pointer to it's C++ + #counterpart + derive = 4 #The Python-Wrapper is derived from the C++ object. + +class attr_types(Enum): + star = "*" + amp = "&" + ampamp = "&&" + default = "" + +#For source-files +class Source: + name = "" + classes = [] + + def __init__(self, name, classes): + self.name = name + self.classes = classes + +#Splits a list by the given delimiter, without splitting strings inside +#pointy-brackets (< and >) +def split_list(str_def, delim): + str_def = str_def.strip() + if len(str_def) == 0: + return [] + if str_def.count(delim) == 0: + return [str_def] + if str_def.count("<") == 0: + return str_def.split(delim) + if str_def.find("<") < str_def.find(" "): + closing = find_closing(str_def[str_def.find("<")+1:], "<", ">") + str_def.find("<") + comma = str_def[closing:].find(delim) + if comma == -1: + return [str_def] + comma = closing + comma + else: + comma = str_def.find(delim) + rest = split_list(str_def[comma+1:], delim) + ret = [str_def[:comma]] + if rest != None and len(rest) != 0: + ret.extend(rest) + return ret + +#Represents a Type +class WType: + name = "" + cont = None + attr_type = attr_types.default + + def __init__(self, name = "", cont = None, attr_type = attr_types.default): + self.name = name + self.cont = cont + self.attr_type = attr_type + + #Python type-string + def gen_text(self): + text = self.name + if self.name in enum_names: + text = enum_by_name(self.name).namespace + "::" + self.name + if self.cont != None: + return known_containers[self.name].typename + return text + + #C++ type-string + def gen_text_cpp(self): + postfix = "" + if self.attr_type == attr_types.star: + postfix = "*" + if self.name in primitive_types: + return self.name + postfix + if self.name in enum_names: + return enum_by_name(self.name).namespace + "::" + self.name + postfix + if self.name in classnames: + return class_by_name(self.name).namespace + "::" + self.name + postfix + text = self.name + if self.cont != None: + text += "<" + for a in self.cont.args: + text += a.gen_text_cpp() + ", " + text = text[:-2] + text += ">" + return text + + @staticmethod + def from_string(str_def, containing_file, line_number): + str_def = str_def.strip() + if len(str_def) == 0: + return None + str_def = str_def.replace("RTLIL::SigSig", "std::pair").replace("SigSig", "std::pair") + t = WType() + t.name = "" + t.cont = None + t.attr_type = attr_types.default + if str_def.find("<") != -1:# and str_def.find("<") < str_def.find(" "): + candidate = WContainer.from_string(str_def, containing_file, line_number) + if candidate == None: + return None + t.name = str_def[:str_def.find("<")] + + if t.name.count("*") + t.name.count("&") > 1: + return None + + if t.name.count("*") == 1 or str_def[0] == '*' or str_def[-1] == '*': + t.attr_type = attr_types.star + t.name = t.name.replace("*","") + elif t.name.count("&&") == 1: + t.attr_type = attr_types.ampamp + t.name = t.name.replace("&&","") + elif t.name.count("&") == 1 or str_def[0] == '&' or str_def[-1] == '&': + t.attr_type = attr_types.amp + t.name = t.name.replace("&","") + + t.cont = candidate + if(t.name not in known_containers): + return None + return t + + prefix = "" + + if str.startswith(str_def, "unsigned "): + prefix = "unsigned " + str_def = str_def[9:] + while str.startswith(str_def, "long "): + prefix= "long " + prefix + str_def = str_def[5:] + while str.startswith(str_def, "short "): + prefix = "short " + prefix + str_def = str_def[6:] + + str_def = str_def.split("::")[-1] + + if str_def.count("*") + str_def.count("&") >= 2: + return None + + if str_def.count("*") == 1: + t.attr_type = attr_types.star + str_def = str_def.replace("*","") + elif str_def.count("&&") == 1: + t.attr_type = attr_types.ampamp + str_def = str_def.replace("&&","") + elif str_def.count("&") == 1: + t.attr_type = attr_types.amp + str_def = str_def.replace("&","") + + if len(str_def) > 0 and str_def.split("::")[-1] not in primitive_types and str_def.split("::")[-1] not in classnames and str_def.split("::")[-1] not in enum_names: + return None + + if str_def.count(" ") == 0: + t.name = (prefix + str_def).replace("char_p", "char *") + t.cont = None + return t + return None + +#Represents a container-type +class WContainer: + name = "" + args = [] + + def from_string(str_def, containing_file, line_number): + if str_def == None or len(str_def) < 4: + return None + cont = WContainer() + cont.name = str_def[:str_def.find("<")] + str_def = str_def[str_def.find("<")+1:find_closing(str_def, "<", ">")] + cont.args = [] + for arg in split_list(str_def, ","): + candidate = WType.from_string(arg.strip(), containing_file, line_number) + if candidate == None: + return None + cont.args.append(candidate) + return cont + +#Translators between Python and C++ containers +#Base Type +class Translator: + tmp_cntr = 0 + typename = "DefaultType" + orig_name = "DefaultCpp" + + @classmethod + def gen_type(c, types): + return "\nImplement a function that outputs the c++ type of this container here\n" + + @classmethod + def translate(c, varname, types, prefix): + return "\nImplement a function translating a python container to a c++ container here\n" + + @classmethod + def translate_cpp(c, varname, types, prefix, ref): + return "\nImplement a function translating a c++ container to a python container here\n" + +#Translates list-types (vector, pool, set), that only differ in their name and +#the name of the insertion function +class PythonListTranslator(Translator): + typename = "boost::python::list" + insert_name = "Default" + + #generate the c++ type string + @classmethod + def gen_type(c, types): + text = c.orig_name + "<" + if types[0].name in primitive_types: + text += types[0].name + elif types[0].name in known_containers: + text += known_containers[types[0].name].gen_type(types[0].cont.args) + else: + text += class_by_name(types[0].name).namespace + "::" + types[0].name + if types[0].attr_type == attr_types.star: + text += "*" + text += ">" + return text + + #Generate C++ code to translate from a boost::python::list + @classmethod + def translate(c, varname, types, prefix): + text = prefix + c.gen_type(types) + " " + varname + "___tmp;" + cntr_name = "cntr_" + str(Translator.tmp_cntr) + Translator.tmp_cntr = Translator.tmp_cntr + 1 + text += prefix + "for(int " + cntr_name + " = 0; " + cntr_name + " < len(" + varname + "); " + cntr_name + "++)" + text += prefix + "{" + tmp_name = "tmp_" + str(Translator.tmp_cntr) + Translator.tmp_cntr = Translator.tmp_cntr + 1 + if types[0].name in known_containers: + text += prefix + "\t" + known_containers[types[0].name].typename + " " + tmp_name + " = boost::python::extract<" + known_containers[types[0].name].typename + ">(" + varname + "[" + cntr_name + "]);" + text += known_containers[types[0].name].translate(tmp_name, types[0].cont.args, prefix+"\t") + tmp_name = tmp_name + "___tmp" + text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(" + tmp_name + ");" + elif types[0].name in classnames: + text += prefix + "\t" + types[0].name + "* " + tmp_name + " = boost::python::extract<" + types[0].name + "*>(" + varname + "[" + cntr_name + "]);" + if types[0].attr_type == attr_types.star: + text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(" + tmp_name + "->get_cpp_obj());" + else: + text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(*" + tmp_name + "->get_cpp_obj());" + else: + text += prefix + "\t" + types[0].name + " " + tmp_name + " = boost::python::extract<" + types[0].name + ">(" + varname + "[" + cntr_name + "]);" + text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(" + tmp_name + ");" + text += prefix + "}" + return text + + #Generate C++ code to translate to a boost::python::list + @classmethod + def translate_cpp(c, varname, types, prefix, ref): + text = prefix + c.typename + " " + varname + "___tmp;" + tmp_name = "tmp_" + str(Translator.tmp_cntr) + Translator.tmp_cntr = Translator.tmp_cntr + 1 + if ref: + text += prefix + "for(auto " + tmp_name + " : *" + varname + ")" + else: + text += prefix + "for(auto " + tmp_name + " : " + varname + ")" + text += prefix + "{" + if types[0].name in classnames: + if types[0].attr_type == attr_types.star: + text += prefix + "\t" + varname + "___tmp.append(" + types[0].name + "::get_py_obj(" + tmp_name + "));" + else: + text += prefix + "\t" + varname + "___tmp.append(*" + types[0].name + "::get_py_obj(&" + tmp_name + "));" + elif types[0].name in known_containers: + text += known_containers[types[0].name].translate_cpp(tmp_name, types[0].cont.args, prefix + "\t", types[0].attr_type == attr_types.star) + text += prefix + "\t" + varname + "___tmp.append(" + tmp_name + "___tmp);" + else: + text += prefix + "\t" + varname + "___tmp.append(" + tmp_name + ");" + text += prefix + "}" + return text + +#Sub-type for std::set +class SetTranslator(PythonListTranslator): + insert_name = "insert" + orig_name = "std::set" + +#Sub-type for std::vector +class VectorTranslator(PythonListTranslator): + insert_name = "push_back" + orig_name = "std::vector" + +#Sub-type for pool +class PoolTranslator(PythonListTranslator): + insert_name = "insert" + orig_name = "pool" + +#Translates dict-types (dict, std::map), that only differ in their name and +#the name of the insertion function +class PythonDictTranslator(Translator): + typename = "boost::python::dict" + insert_name = "Default" + + @classmethod + def gen_type(c, types): + text = c.orig_name + "<" + if types[0].name in primitive_types: + text += types[0].name + elif types[0].name in known_containers: + text += known_containers[types[0].name].gen_type(types[0].cont.args) + else: + text += class_by_name(types[0].name).namespace + "::" + types[0].name + if types[0].attr_type == attr_types.star: + text += "*" + text += ", " + if types[1].name in primitive_types: + text += types[1].name + elif types[1].name in known_containers: + text += known_containers[types[1].name].gen_type(types[1].cont.args) + else: + text += class_by_name(types[1].name).namespace + "::" + types[1].name + if types[1].attr_type == attr_types.star: + text += "*" + text += ">" + return text + + #Generate c++ code to translate from a boost::python::dict + @classmethod + def translate(c, varname, types, prefix): + text = prefix + c.gen_type(types) + " " + varname + "___tmp;" + text += prefix + "boost::python::list " + varname + "_keylist = " + varname + ".keys();" + cntr_name = "cntr_" + str(Translator.tmp_cntr) + Translator.tmp_cntr = Translator.tmp_cntr + 1 + text += prefix + "for(int " + cntr_name + " = 0; " + cntr_name + " < len(" + varname + "_keylist); " + cntr_name + "++)" + text += prefix + "{" + key_tmp_name = "key_tmp_" + str(Translator.tmp_cntr) + val_tmp_name = "val_tmp_" + str(Translator.tmp_cntr) + Translator.tmp_cntr = Translator.tmp_cntr + 1 + + if types[0].name in known_containers: + text += prefix + "\t" + known_containers[types[0].name].typename + " " + key_tmp_name + " = boost::python::extract<" + known_containers[types[0].name].typename + ">(" + varname + "_keylist[ " + cntr_name + " ]);" + text += known_containers[types[0].name].translate(key_tmp_name, types[0].cont.args, prefix+"\t") + key_tmp_name = key_tmp_name + "___tmp" + elif types[0].name in classnames: + text += prefix + "\t" + types[0].name + "* " + key_tmp_name + " = boost::python::extract<" + types[0].name + "*>(" + varname + "_keylist[ " + cntr_name + " ]);" + else: + text += prefix + "\t" + types[0].name + " " + key_tmp_name + " = boost::python::extract<" + types[0].name + ">(" + varname + "_keylist[ " + cntr_name + " ]);" + + if types[1].name in known_containers: + text += prefix + "\t" + known_containers[types[1].name].typename + " " + val_tmp_name + " = boost::python::extract<" + known_containers[types[1].name].typename + ">(" + varname + "[" + varname + "_keylist[ " + cntr_name + " ]]);" + text += known_containers[types[1].name].translate(val_tmp_name, types[1].cont.args, prefix+"\t") + val_tmp_name = val_tmp_name + "___tmp" + elif types[1].name in classnames: + text += prefix + "\t" + types[1].name + "* " + val_tmp_name + " = boost::python::extract<" + types[1].name + "*>(" + varname + "[" + varname + "_keylist[ " + cntr_name + " ]]);" + else: + text += prefix + "\t" + types[1].name + " " + val_tmp_name + " = boost::python::extract<" + types[1].name + ">(" + varname + "[" + varname + "_keylist[ " + cntr_name + " ]]);" + + text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(std::pair<" + types[0].gen_text_cpp() + ", " + types[1].gen_text_cpp() + ">(" + + if types[0].name not in classnames: + text += key_tmp_name + else: + if types[0].attr_type != attr_types.star: + text += "*" + text += key_tmp_name + "->get_cpp_obj()" + + text += ", " + if types[1].name not in classnames: + text += val_tmp_name + else: + if types[1].attr_type != attr_types.star: + text += "*" + text += val_tmp_name + "->get_cpp_obj()" + text += "));\n" + prefix + "}" + return text + + #Generate c++ code to translate to a boost::python::dict + @classmethod + def translate_cpp(c, varname, types, prefix, ref): + text = prefix + c.typename + " " + varname + "___tmp;" + tmp_name = "tmp_" + str(Translator.tmp_cntr) + Translator.tmp_cntr = Translator.tmp_cntr + 1 + if ref: + text += prefix + "for(auto " + tmp_name + " : *" + varname + ")" + else: + text += prefix + "for(auto " + tmp_name + " : " + varname + ")" + text += prefix + "{" + if types[1].name in known_containers: + text += prefix + "\tauto " + tmp_name + "_second = " + tmp_name + ".second;" + text += known_containers[types[1].name].translate_cpp(tmp_name + "_second", types[1].cont.args, prefix + "\t", types[1].attr_type == attr_types.star) + + if types[0].name in classnames: + text += prefix + "\t" + varname + "___tmp[" + types[0].name + "::get_py_obj(" + tmp_name + ".first)] = " + elif types[0].name not in known_containers: + text += prefix + "\t" + varname + "___tmp[" + tmp_name + ".first] = " + + if types[1].name in classnames: + if types[1].attr_type == attr_types.star: + text += types[1].name + "::get_py_obj(" + tmp_name + ".second);" + else: + text += "*" + types[1].name + "::get_py_obj(&" + tmp_name + ".second);" + elif types[1].name in known_containers: + text += tmp_name + "_second___tmp;" + else: + text += tmp_name + ".second;" + text += prefix + "}" + return text + +#Sub-type for dict +class DictTranslator(PythonDictTranslator): + insert_name = "insert" + orig_name = "dict" + +#Sub_type for std::map +class MapTranslator(PythonDictTranslator): + insert_name = "insert" + orig_name = "std::map" + +#Translator for std::pair. Derived from PythonDictTranslator because the +#gen_type function is the same (because both have two template parameters) +class TupleTranslator(PythonDictTranslator): + typename = "boost::python::tuple" + orig_name = "std::pair" + + #Generate c++ code to translate from a boost::python::tuple + @classmethod + def translate(c, varname, types, prefix): + text = prefix + types[0].name + " " + varname + "___tmp_0 = boost::python::extract<" + types[0].name + ">(" + varname + "[0]);" + text += prefix + types[1].name + " " + varname + "___tmp_1 = boost::python::extract<" + types[1].name + ">(" + varname + "[1]);" + text += prefix + TupleTranslator.gen_type(types) + " " + varname + "___tmp(" + if types[0].name.split(" ")[-1] in primitive_types: + text += varname + "___tmp_0, " + else: + text += varname + "___tmp_0.get_cpp_obj(), " + if types[1].name.split(" ")[-1] in primitive_types: + text += varname + "___tmp_1);" + else: + text += varname + "___tmp_1.get_cpp_obj());" + return text + + #Generate c++ code to translate to a boost::python::tuple + @classmethod + def translate_cpp(c, varname, types, prefix, ref): + text = prefix + TupleTranslator.typename + " " + varname + "___tmp = boost::python::make_tuple(" + varname + ".first, " + varname + ".second);" + return text + tmp_name = "tmp_" + str(Translator.tmp_cntr) + Translator.tmp_cntr = Translator.tmp_cntr + 1 + if ref: + text += prefix + "for(auto " + tmp_name + " : *" + varname + ")" + else: + text += prefix + "for(auto " + tmp_name + " : " + varname + ")" + text += prefix + "{" + if types[0].name.split(" ")[-1] in primitive_types or types[0].name in enum_names: + text += prefix + "\t" + varname + "___tmp.append(" + tmp_name + ");" + elif types[0].name in known_containers: + text += known_containers[types[0].name].translate_cpp(tmp_name, types[0].cont.args, prefix + "\t", types[1].attr_type == attr_types.star) + text += prefix + "\t" + varname + "___tmp.append(" + types[0].name + "::get_py_obj(" + tmp_name + "___tmp);" + elif types[0].name in classnames: + text += prefix + "\t" + varname + "___tmp.append(" + types[0].name + "::get_py_obj(" + tmp_name + "));" + text += prefix + "}" + return text + +#Associate the Translators with their c++ type +known_containers = { + "std::set" : SetTranslator, + "std::vector" : VectorTranslator, + "pool" : PoolTranslator, + "dict" : DictTranslator, + "std::pair" : TupleTranslator, + "std::map" : MapTranslator +} + +class Attribute: + wtype = None + varname = None + is_const = False + default_value = None + pos = None + pos_counter = 0 + + def __init__(self, wtype, varname, is_const = False, default_value = None): + self.wtype = wtype + self.varname = varname + self.is_const = is_const + self.default_value = None + self.container = None + + @staticmethod + def from_string(str_def, containing_file, line_number): + if len(str_def) < 3: + return None + orig = str_def + arg = Attribute(None, None) + prefix = "" + arg.wtype = None + arg.varname = None + arg.is_const = False + arg.default_value = None + arg.container = None + if str.startswith(str_def, "const "): + arg.is_const = True + str_def = str_def[6:] + if str.startswith(str_def, "unsigned "): + prefix = "unsigned " + str_def = str_def[9:] + while str.startswith(str_def, "long "): + prefix= "long " + prefix + str_def = str_def[5:] + while str.startswith(str_def, "short "): + prefix = "short " + prefix + str_def = str_def[6:] + + if str_def.find("<") != -1 and str_def.find("<") < str_def.find(" "): + closing = find_closing(str_def[str_def.find("<"):], "<", ">") + str_def.find("<") + 1 + arg.wtype = WType.from_string(str_def[:closing].strip(), containing_file, line_number) + str_def = str_def[closing+1:] + else: + if str_def.count(" ") > 0: + arg.wtype = WType.from_string(prefix + str_def[:str_def.find(" ")].strip(), containing_file, line_number) + str_def = str_def[str_def.find(" ")+1:] + else: + arg.wtype = WType.from_string(prefix + str_def.strip(), containing_file, line_number) + str_def = "" + arg.varname = "" + + if arg.wtype == None: + return None + if str_def.count("=") == 0: + arg.varname = str_def.strip() + if arg.varname.find(" ") > 0: + return None + else: + arg.varname = str_def[:str_def.find("=")].strip() + if arg.varname.find(" ") > 0: + return None + str_def = str_def[str_def.find("=")+1:].strip() + arg.default_value = str_def[arg.varname.find("=")+1:].strip() + if len(arg.varname) == 0: + arg.varname = None + return arg + if arg.varname[0] == '*': + arg.wtype.attr_type = attr_types.star + arg.varname = arg.varname[1:] + elif arg.varname[0] == '&': + if arg.wtype.attr_type != attr_types.default: + return None + if arg.varname[1] == '&': + arg.wtype.attr_type = attr_types.ampamp + arg.varname = arg.varname[2:] + else: + arg.wtype.attr_type = attr_types.amp + arg.varname = arg.varname[1:] + return arg + + #Generates the varname. If the attribute has no name in the header file, + #a name is generated + def gen_varname(self): + if self.varname != None: + return self.varname + if self.wtype.name == "void": + return "" + if self.pos == None: + self.pos = Attribute.pos_counter + Attribute.pos_counter = Attribute.pos_counter + 1 + return "gen_varname_" + str(self.pos) + + #Generates the text for the function headers with wrapper types + def gen_listitem(self): + prefix = "" + if self.is_const: + prefix = "const " + if self.wtype.name in classnames: + return prefix + self.wtype.name + "* " + self.gen_varname() + if self.wtype.name in known_containers: + return prefix + known_containers[self.wtype.name].typename + " " + self.gen_varname() + return prefix + self.wtype.name + " " + self.gen_varname() + + #Generates the test for the function headers with c++ types + def gen_listitem_cpp(self): + prefix = "" + if self.is_const: + prefix = "const " + infix = "" + if self.wtype.attr_type == attr_types.star: + infix = "*" + elif self.wtype.attr_type == attr_types.amp: + infix = "&" + elif self.wtype.attr_type == attr_types.ampamp: + infix = "&&" + if self.wtype.name in known_containers: + return prefix + known_containers[self.wtype.name].gen_type(self.wtype.cont.args) + " " + infix + self.gen_varname() + if self.wtype.name in classnames: + return prefix + class_by_name(self.wtype.name).namespace + "::" + self.wtype.name + " " + infix + self.gen_varname() + return prefix + self.wtype.name + " " + infix + self.gen_varname() + + #Generates the listitem withtout the varname, so the signature can be + #compared + def gen_listitem_hash(self): + prefix = "" + if self.is_const: + prefix = "const " + if self.wtype.name in classnames: + return prefix + self.wtype.name + "* " + if self.wtype.name in known_containers: + return known_containers[self.wtype.name].typename + return prefix + self.wtype.name + + #Generate Translation code for the attribute + def gen_translation(self): + if self.wtype.name in known_containers: + return known_containers[self.wtype.name].translate(self.gen_varname(), self.wtype.cont.args, "\n\t\t") + return "" + + #Generate Translation code from c++ for the attribute + def gen_translation_cpp(self): + if self.wtype.name in known_containers: + return known_containers[self.wtype.name].translate_cpp(self.gen_varname(), self.wtype.cont.args, "\n\t\t", self.wtype.attr_type == attr_types.star) + return "" + + #Generate Text for the call + def gen_call(self): + ret = self.gen_varname() + if self.wtype.name in known_containers: + if self.wtype.attr_type == attr_types.star: + return "&" + ret + "___tmp" + return ret + "___tmp" + if self.wtype.name in classnames: + if self.wtype.attr_type != attr_types.star: + ret = "*" + ret + return ret + "->get_cpp_obj()" + if self.wtype.name == "char *" and self.gen_varname() in ["format", "fmt"]: + return "\"%s\", " + self.gen_varname() + if self.wtype.attr_type == attr_types.star: + return "&" + ret + return ret + + def gen_call_cpp(self): + ret = self.gen_varname() + if self.wtype.name.split(" ")[-1] in primitive_types or self.wtype.name in enum_names: + if self.wtype.attr_type == attr_types.star: + return "&" + ret + return ret + if self.wtype.name not in classnames: + if self.wtype.attr_type == attr_types.star: + return "&" + ret + "___tmp" + return ret + "___tmp" + if self.wtype.attr_type != attr_types.star: + ret = "*" + ret + return self.wtype.name + "::get_py_obj(" + self.gen_varname() + ")" + + #Generate cleanup code + def gen_cleanup(self): + if self.wtype.name in primitive_types or self.wtype.name in classnames or self.wtype.name in enum_names or not self.wtype.attr_type == attr_types.star or (self.wtype.name in known_containers and self.wtype.attr_type == attr_types.star): + return "" + return "\n\t\tdelete " + self.gen_varname() + "___tmp;" + +class WClass: + name = None + namespace = None + link_type = None + id_ = None + string_id = None + hash_id = None + needs_clone = False + found_funs = [] + found_vars = [] + found_constrs = [] + + def __init__(self, name, link_type, id_, string_id = None, hash_id = None, needs_clone = False): + self.name = name + self.namespace = None + self.link_type = link_type + self.id_ = id_ + self.string_id = string_id + self.hash_id = hash_id + self.needs_clone = needs_clone + self.found_funs = [] + self.found_vars = [] + self.found_constrs = [] + + def printable_constrs(self): + ret = 0 + for con in self.found_constrs: + if not con.protected: + ret += 1 + return ret + + def gen_decl(self, filename): + long_name = self.namespace + "::" + self.name + + text = "\n\t// WRAPPED from " + filename + text += "\n\tstruct " + self.name + if self.link_type == link_types.derive: + text += " : public " + self.namespace + "::" + self.name + text += "\n\t{\n" + + if self.link_type != link_types.derive: + + text += "\t\t" + long_name + "* ref_obj;\n" + + if self.link_type == link_types.ref_copy or self.link_type == link_types.pointer: + text += "\n\t\t" + long_name + "* get_cpp_obj() const\n\t\t{\n\t\t\treturn ref_obj;\n\t\t}\n" + elif self.link_type == link_types.global_list: + text += "\t\t" + self.id_.wtype.name + " " + self.id_.varname + ";\n" + text += "\n\t\t" + long_name + "* get_cpp_obj() const\n\t\t{" + text += "\n\t\t\t" + long_name + "* ret = " + long_name + "::get_all_" + self.name.lower() + "s()->at(this->" + self.id_.varname + ");" + text += "\n\t\t\tif(ret != NULL && ret == this->ref_obj)" + text += "\n\t\t\t\treturn ret;" + text += "\n\t\t\tthrow std::runtime_error(\"" + self.name + "'s c++ object does not exist anymore.\");" + text += "\n\t\t\treturn NULL;" + text += "\n\t\t}\n" + + #if self.link_type != link_types.pointer: + text += "\n\t\tstatic " + self.name + "* get_py_obj(" + long_name + "* ref)\n\t\t{" + text += "\n\t\t\t" + self.name + "* ret = (" + self.name + "*)malloc(sizeof(" + self.name + "));" + if self.link_type == link_types.pointer: + text += "\n\t\t\tret->ref_obj = ref;" + if self.link_type == link_types.ref_copy: + if self.needs_clone: + text += "\n\t\t\tret->ref_obj = ref->clone();" + else: + text += "\n\t\t\tret->ref_obj = new "+long_name+"(*ref);" + if self.link_type == link_types.global_list: + text += "\n\t\t\tret->ref_obj = ref;" + text += "\n\t\t\tret->" + self.id_.varname + " = ret->ref_obj->" + self.id_.varname + ";" + text += "\n\t\t\treturn ret;" + text += "\n\t\t}\n" + + if self.link_type == link_types.ref_copy: + text += "\n\t\tstatic " + self.name + "* get_py_obj(" + long_name + " ref)\n\t\t{" + text += "\n\t\t\t" + self.name + "* ret = (" + self.name + "*)malloc(sizeof(" + self.name + "));" + if self.needs_clone: + text += "\n\t\t\tret->ref_obj = ref.clone();" + else: + text += "\n\t\t\tret->ref_obj = new "+long_name+"(ref);" + text += "\n\t\t\treturn ret;" + text += "\n\t\t}\n" + + if self.link_type != link_types.global_list: + text += "\n\t\t~" + self.name + "()\n\t\t{" + text += "\n\t\t\tdelete(this->ref_obj);\n\t\t}\n" + + for con in self.found_constrs: + text += con.gen_decl() + for var in self.found_vars: + text += var.gen_decl() + for fun in self.found_funs: + text += fun.gen_decl() + + + if self.link_type == link_types.derive: + duplicates = {} + for fun in self.found_funs: + if fun.name in duplicates: + fun.gen_alias() + duplicates[fun.name].gen_alias() + else: + duplicates[fun.name] = fun + + text += "\n\t\t" + long_name + "* get_cpp_obj() const\n\t\t{\n\t\t\treturn (" + self.namespace + "::" + self.name +"*)this;\n\t\t}\n" + text += "\n\t\tstatic " + self.name + "* get_py_obj(" + long_name + "* ref)\n\t\t{" + text += "\n\t\t\treturn (" + self.name + "*)ref;" + text += "\n\t\t}\n" + + for con in self.found_constrs: + text += con.gen_decl_derive() + for var in self.found_vars: + text += var.gen_decl() + for fun in self.found_funs: + text += fun.gen_decl_virtual() + + if self.hash_id != None: + text += "\n\t\tunsigned int get_hash_py()" + text += "\n\t\t{" + text += "\n\t\t\treturn get_cpp_obj()->" + self.hash_id + ";" + text += "\n\t\t}" + + text += "\n\t};\n" + + if self.link_type == link_types.derive: + text += "\n\tstruct " + self.name + "Wrap : " + self.name + ", boost::python::wrapper<" + self.name + ">" + text += "\n\t{" + + for con in self.found_constrs: + text += con.gen_decl_wrapperclass() + for fun in self.found_funs: + text += fun.gen_default_impl() + + text += "\n\t};" + + text += "\n\tstd::ostream &operator<<(std::ostream &ostr, const " + self.name + " &ref)" + text += "\n\t{" + text += "\n\t\tostr << \"" + self.name + if self.string_id != None: + text +=" \\\"\"" + text += " << ref.get_cpp_obj()->" + self.string_id + text += " << \"\\\"\"" + else: + text += " at \" << ref.get_cpp_obj()" + text += ";" + text += "\n\t\treturn ostr;" + text += "\n\t}" + text += "\n" + + return text + + def gen_funs(self, filename): + text = "" + if self.link_type != link_types.derive: + for con in self.found_constrs: + text += con.gen_def() + for var in self.found_vars: + text += var.gen_def() + for fun in self.found_funs: + text += fun.gen_def() + else: + for var in self.found_vars: + text += var.gen_def() + for fun in self.found_funs: + text += fun.gen_def_virtual() + return text + + def gen_boost_py(self): + text = "\n\t\tclass_<" + self.name + if self.link_type == link_types.derive: + text += "Wrap, boost::noncopyable" + text += ">(\"" + self.name + "\"" + if self.printable_constrs() == 0 or not self.contains_default_constr(): + text += ", no_init" + text += ")" + text += "\n\t\t\t.def(boost::python::self_ns::str(boost::python::self_ns::self))" + text += "\n\t\t\t.def(boost::python::self_ns::repr(boost::python::self_ns::self))" + for con in self.found_constrs: + text += con.gen_boost_py() + for var in self.found_vars: + text += var.gen_boost_py() + static_funs = [] + for fun in self.found_funs: + text += fun.gen_boost_py() + if fun.is_static and fun.alias not in static_funs: + static_funs.append(fun.alias) + for fun in static_funs: + text += "\n\t\t\t.staticmethod(\"" + fun + "\")" + + if self.hash_id != None: + text += "\n\t\t\t.def(\"__hash__\", &" + self.name + "::get_hash_py)" + text += "\n\t\t\t;\n" + return text + + def contains_default_constr(self): + for c in self.found_constrs: + if len(c.args) == 0: + return True + return False + +#CONFIGURE HEADER-FILES TO BE PARSED AND CLASSES EXPECTED IN THEM HERE + +sources = [ + Source("kernel/celltypes",[ + WClass("CellType", link_types.pointer, None, None, "type.hash()", True), + WClass("CellTypes", link_types.pointer, None, None, None, True) + ] + ), + Source("kernel/consteval",[ + WClass("ConstEval", link_types.pointer, None, None, None, True) + ] + ), + Source("kernel/log",[]), + Source("kernel/register",[ + WClass("Pass", link_types.derive, None, None, None, True), + ] + ), + Source("kernel/rtlil",[ + WClass("IdString", link_types.ref_copy, None, "str()", "hash()"), + WClass("Const", link_types.ref_copy, None, "as_string()", "hash()"), + WClass("AttrObject", link_types.ref_copy, None, None, None), + WClass("Selection", link_types.ref_copy, None, None, None), + WClass("Monitor", link_types.derive, None, None, None), + WClass("CaseRule",link_types.ref_copy, None, None, None, True), + WClass("SwitchRule",link_types.ref_copy, None, None, None, True), + WClass("SyncRule", link_types.ref_copy, None, None, None, True), + WClass("Process", link_types.ref_copy, None, "name.c_str()", "name.hash()"), + WClass("SigChunk", link_types.ref_copy, None, None, None), + WClass("SigBit", link_types.ref_copy, None, None, "hash()"), + WClass("SigSpec", link_types.ref_copy, None, None, "hash()"), + WClass("Cell", link_types.global_list, Attribute(WType("unsigned int"), "hashidx_"), "name.c_str()", "hash()"), + WClass("Wire", link_types.global_list, Attribute(WType("unsigned int"), "hashidx_"), "name.c_str()", "hash()"), + WClass("Memory", link_types.global_list, Attribute(WType("unsigned int"), "hashidx_"), "name.c_str()", "hash()"), + WClass("Module", link_types.global_list, Attribute(WType("unsigned int"), "hashidx_"), "name.c_str()", "hash()"), + WClass("Design", link_types.global_list, Attribute(WType("unsigned int"), "hashidx_"), "hashidx_", "hash()") + ] + ), + #Source("kernel/satgen",[ + # ] + # ), + #Source("libs/ezsat/ezsat",[ + # ] + # ), + #Source("libs/ezsat/ezminisat",[ + # ] + # ), + Source("kernel/sigtools",[ + WClass("SigMap", link_types.pointer, None, None, None, True) + ] + ), + Source("kernel/yosys",[ + ] + ), + Source("kernel/cost",[]) + ] + +blacklist_methods = ["Yosys::Pass::run_register", "Yosys::Module::Pow", "Yosys::Module::Bu0", "Yosys::CaseRule::optimize"] + +enum_names = ["State","SyncType","ConstFlags"] + +enums = [] #Do not edit + +unowned_functions = [] + +classnames = [] +for source in sources: + for wclass in source.classes: + classnames.append(wclass.name) + +def class_by_name(name): + for source in sources: + for wclass in source.classes: + if wclass.name == name: + return wclass + return None + +def enum_by_name(name): + for e in enums: + if e.name == name: + return e + return None + +def find_closing(text, open_tok, close_tok): + if text.find(open_tok) == -1 or text.find(close_tok) <= text.find(open_tok): + return text.find(close_tok) + return text.find(close_tok) + find_closing(text[text.find(close_tok)+1:], open_tok, close_tok) + 1 + +def unpretty_string(s): + s = s.strip() + while s.find(" ") != -1: + s = s.replace(" "," ") + while s.find("\t") != -1: + s = s.replace("\t"," ") + s = s.replace(" (","(") + return s + +class WEnum: + name = None + namespace = None + values = [] + + def from_string(str_def, namespace, line_number): + str_def = str_def.strip() + if not str.startswith(str_def, "enum "): + return None + if str_def.count(";") != 1: + return None + str_def = str_def[5:] + enum = WEnum() + split = str_def.split(":") + if(len(split) != 2): + return None + enum.name = split[0].strip() + if enum.name not in enum_names: + return None + str_def = split[1] + if str_def.count("{") != str_def.count("}") != 1: + return None + if len(str_def) < str_def.find("}")+2 or str_def[str_def.find("}")+1] != ';': + return None + str_def = str_def.split("{")[-1].split("}")[0] + enum.values = [] + for val in str_def.split(','): + enum.values.append(val.strip().split('=')[0].strip()) + enum.namespace = namespace + return enum + + def gen_boost_py(self): + text = "\n\t\tenum_<" + self.namespace + "::" + self.name + ">(\"" + self.name + "\")\n" + for value in self.values: + text += "\t\t\t.value(\"" + value + "\"," + self.namespace + "::" + value + ")\n" + text += "\t\t\t;\n" + return text + + def __str__(self): + ret = "Enum " + self.namespace + "::" + self.name + "(\n" + for val in self.values: + ret = ret + "\t" + val + "\n" + return ret + ")" + + def __repr__(self): + return __str__(self) + +class WConstructor: + orig_text = None + args = [] + containing_file = None + member_of = None + duplicate = False + protected = False + + def __init__(self, containing_file, class_): + self.orig_text = "Auto generated default constructor" + self.args = [] + self.containing_file = containing_file + self.member_of = class_ + self.protected = False + + def from_string(str_def, containing_file, class_, line_number, protected = False): + if class_ == None: + return None + if str_def.count("delete;") > 0: + return None + con = WConstructor(containing_file, class_) + con.orig_text = str_def + con.args = [] + con.duplicate = False + con.protected = protected + if not str.startswith(str_def, class_.name + "("): + return None + str_def = str_def[len(class_.name)+1:] + found = find_closing(str_def, "(", ")") + if found == -1: + return None + str_def = str_def[0:found].strip() + if len(str_def) == 0: + return con + for arg in split_list(str_def, ","): + parsed = Attribute.from_string(arg.strip(), containing_file, line_number) + if parsed == None: + return None + con.args.append(parsed) + return con + + def gen_decl(self): + if self.duplicate or self.protected: + return "" + text = "\n\t\t// WRAPPED from \"" + self.orig_text.replace("\n"," ") + "\" in " + self.containing_file + text += "\n\t\t" + self.member_of.name + "(" + for arg in self.args: + text += arg.gen_listitem() + ", " + if len(self.args) > 0: + text = text[:-2] + text += ");\n" + return text + + def gen_decl_derive(self): + if self.duplicate or self.protected: + return "" + text = "\n\t\t// WRAPPED from \"" + self.orig_text.replace("\n"," ") + "\" in " + self.containing_file + text += "\n\t\t" + self.member_of.name + "(" + for arg in self.args: + text += arg.gen_listitem() + ", " + if len(self.args) > 0: + text = text[:-2] + text += ")" + if len(self.args) == 0: + return text + "{}" + text += " : " + text += self.member_of.namespace + "::" + self.member_of.name + "(" + for arg in self.args: + text += arg.gen_call() + ", " + if len(self.args) > 0: + text = text[:-2] + text += "){}\n" + return text + + def gen_decl_wrapperclass(self): + if self.duplicate or self.protected: + return "" + text = "\n\t\t// WRAPPED from \"" + self.orig_text.replace("\n"," ") + "\" in " + self.containing_file + text += "\n\t\t" + self.member_of.name + "Wrap(" + for arg in self.args: + text += arg.gen_listitem() + ", " + if len(self.args) > 0: + text = text[:-2] + text += ")" + if len(self.args) == 0: + return text + "{}" + text += " : " + text += self.member_of.name + "(" + for arg in self.args: + text += arg.gen_call() + ", " + if len(self.args) > 0: + text = text[:-2] + text += "){}\n" + return text + + def gen_decl_hash_py(self): + text = self.member_of.name + "(" + for arg in self.args: + text += arg.gen_listitem_hash() + ", " + if len(self.args) > 0: + text = text[:-2] + text += ");" + return text + + def gen_def(self): + if self.duplicate or self.protected: + return "" + text = "\n\t// WRAPPED from \"" + self.orig_text.replace("\n"," ") + "\" in " + self.containing_file + text += "\n\t" + self.member_of.name + "::" + self.member_of.name + "(" + for arg in self.args: + text += arg.gen_listitem() + ", " + if len(self.args) > 0: + text = text[:-2] + text +=")\n\t{" + for arg in self.args: + text += arg.gen_translation() + if self.member_of.link_type != link_types.derive: + text += "\n\t\tthis->ref_obj = new " + self.member_of.namespace + "::" + self.member_of.name + "(" + for arg in self.args: + text += arg.gen_call() + ", " + if len(self.args) > 0: + text = text[:-2] + if self.member_of.link_type != link_types.derive: + text += ");" + if self.member_of.link_type == link_types.global_list: + text += "\n\t\tthis->" + self.member_of.id_.varname + " = this->ref_obj->" + self.member_of.id_.varname + ";" + for arg in self.args: + text += arg.gen_cleanup() + text += "\n\t}\n" + return text + + def gen_boost_py(self): + if self.duplicate or self.protected or len(self.args) == 0: + return "" + text = "\n\t\t\t.def(init" + text += "<" + for a in self.args: + text += a.gen_listitem_hash() + ", " + text = text[0:-2] + ">())" + return text + +class WFunction: + orig_text = None + is_static = False + is_inline = False + is_virtual = False + ret_attr_type = attr_types.default + is_operator = False + ret_type = None + name = None + alias = None + args = [] + containing_file = None + member_of = None + duplicate = False + namespace = "" + + def from_string(str_def, containing_file, class_, line_number, namespace): + if str_def.count("delete;") > 0: + return None + func = WFunction() + func.is_static = False + func.is_inline = False + func.is_virtual = False + func.ret_attr_type = attr_types.default + func.is_operator = False + func.member_of = None + func.orig_text = str_def + func.args = [] + func.containing_file = containing_file + func.member_of = class_ + func.duplicate = False + func.namespace = namespace + str_def = str_def.replace("operator ","operator") + if str.startswith(str_def, "static "): + func.is_static = True + str_def = str_def[7:] + else: + func.is_static = False + if str.startswith(str_def, "inline "): + func.is_inline = True + str_def = str_def[7:] + else: + func.is_inline = False + if str.startswith(str_def, "virtual "): + func.is_virtual = True + str_def = str_def[8:] + else: + func.is_virtual = False + + if str_def.count(" ") == 0: + return None + + parts = split_list(str_def.strip(), " ") + + prefix = "" + i = 0 + for part in parts: + if part in ["unsigned", "long", "short"]: + prefix += part + " " + i = i + 1 + else: + break + parts = parts[i:] + + if len(parts) <= 1: + return None + + func.ret_type = WType.from_string(prefix + parts[0], containing_file, line_number) + + if func.ret_type == None: + return None + + str_def = parts[1] + for part in parts[2:]: + str_def = str_def + " " + part + + found = str_def.find("(") + if found == -1 or (str_def.find(" ") != -1 and found > str_def.find(" ")): + return None + func.name = str_def[:found] + str_def = str_def[found:] + if func.name.find("operator") != -1 and str.startswith(str_def, "()("): + func.name += "()" + str_def = str_def[2:] + str_def = str_def[1:] + if func.name.find("operator") != -1: + func.is_operator = True + if func.name.find("*") == 0: + func.name = func.name.replace("*", "") + func.ret_type.attr_type = attr_types.star + if func.name.find("&&") == 0: + func.name = func.name.replace("&&", "") + func.ret_type.attr_type = attr_types.ampamp + if func.name.find("&") == 0: + func.name = func.name.replace("&", "") + func.ret_type.attr_type = attr_types.amp + + found = find_closing(str_def, "(", ")") + if found == -1: + return None + str_def = str_def[0:found] + if func.name in blacklist_methods: + return None + if func.namespace != None and func.namespace != "": + if (func.namespace + "::" + func.name) in blacklist_methods: + return None + if func.member_of != None: + if (func.namespace + "::" + func.member_of.name + "::" + func.name) in blacklist_methods: + return None + if func.is_operator and func.name.replace(" ","").replace("operator","").split("::")[-1] not in wrappable_operators: + return None + + testname = func.name + if func.is_operator: + testname = testname[:testname.find("operator")] + if testname.count(")") != 0 or testname.count("(") != 0 or testname.count("~") != 0 or testname.count(";") != 0 or testname.count(">") != 0 or testname.count("<") != 0 or testname.count("throw") != 0: + return None + + func.alias = func.name + if func.name in keyword_aliases: + func.alias = keyword_aliases[func.name] + str_def = str_def[:found].strip() + if(len(str_def) == 0): + return func + for arg in split_list(str_def, ","): + if arg.strip() == "...": + continue + parsed = Attribute.from_string(arg.strip(), containing_file, line_number) + if parsed == None: + return None + func.args.append(parsed) + return func + + def gen_alias(self): + self.alias = self.name + for arg in self.args: + self.alias += "__" + arg.wtype.gen_text_cpp().replace("::", "_").replace("<","_").replace(">","_").replace(" ","").replace("*","").replace(",","") + + def gen_decl(self): + if self.duplicate: + return "" + text = "\n\t\t// WRAPPED from \"" + self.orig_text.replace("\n"," ") + "\" in " + self.containing_file + text += "\n\t\t" + if self.is_static: + text += "static " + text += self.ret_type.gen_text() + " " + self.alias + "(" + for arg in self.args: + text += arg.gen_listitem() + text += ", " + if len(self.args) > 0: + text = text[:-2] + text += ");\n" + return text + + def gen_decl_virtual(self): + if self.duplicate: + return "" + if not self.is_virtual: + return self.gen_decl() + text = "\n\t\t// WRAPPED from \"" + self.orig_text.replace("\n"," ") + "\" in " + self.containing_file + text += "\n\t\tvirtual " + if self.is_static: + text += "static " + text += self.ret_type.gen_text() + " py_" + self.alias + "(" + for arg in self.args: + text += arg.gen_listitem() + text += ", " + if len(self.args) > 0: + text = text[:-2] + text += ")" + if len(self.args) == 0: + text += "{}" + else: + text += "\n\t\t{" + for arg in self.args: + text += "\n\t\t\t(void)" + arg.gen_varname() + ";" + text += "\n\t\t}\n" + text += "\n\t\tvirtual " + if self.is_static: + text += "static " + text += self.ret_type.gen_text() + " " + self.name + "(" + for arg in self.args: + text += arg.gen_listitem_cpp() + text += ", " + if len(self.args) > 0: + text = text[:-2] + text += ") YS_OVERRIDE;\n" + return text + + def gen_decl_hash_py(self): + text = self.ret_type.gen_text() + " " + self.alias + "(" + for arg in self.args: + text += arg.gen_listitem_hash() + ", " + if len(self.args) > 0: + text = text[:-2] + text += ");" + return text + + def gen_def(self): + if self.duplicate: + return "" + text = "\n\t// WRAPPED from \"" + self.orig_text.replace("\n"," ") + "\" in " + self.containing_file + text += "\n\t" + self.ret_type.gen_text() + " " + if self.member_of != None: + text += self.member_of.name + "::" + text += self.alias + "(" + for arg in self.args: + text += arg.gen_listitem() + text += ", " + if len(self.args) > 0: + text = text[:-2] + text +=")\n\t{" + for arg in self.args: + text += arg.gen_translation() + text += "\n\t\t" + if self.ret_type.name != "void": + if self.ret_type.name in known_containers: + text += self.ret_type.gen_text_cpp() + else: + text += self.ret_type.gen_text() + if self.ret_type.name in classnames or (self.ret_type.name in known_containers and self.ret_type.attr_type == attr_types.star): + text += "*" + text += " ret_ = " + if self.ret_type.name in classnames: + text += self.ret_type.name + "::get_py_obj(" + if self.member_of == None: + text += "::" + self.namespace + "::" + self.alias + "(" + elif self.is_static: + text += self.member_of.namespace + "::" + self.member_of.name + "::" + self.name + "(" + else: + text += "this->get_cpp_obj()->" + self.name + "(" + for arg in self.args: + text += arg.gen_call() + ", " + if len(self.args) > 0: + text = text[:-2] + if self.ret_type.name in classnames: + text += ")" + text += ");" + for arg in self.args: + text += arg.gen_cleanup() + if self.ret_type.name != "void": + if self.ret_type.name in classnames: + text += "\n\t\treturn *ret_;" + elif self.ret_type.name in known_containers: + text += known_containers[self.ret_type.name].translate_cpp("ret_", self.ret_type.cont.args, "\n\t\t", self.ret_type.attr_type == attr_types.star) + text += "\n\t\treturn ret____tmp;" + else: + text += "\n\t\treturn ret_;" + text += "\n\t}\n" + return text + + def gen_def_virtual(self): + if self.duplicate: + return "" + if not self.is_virtual: + return self.gen_def() + text = "\n\t// WRAPPED from \"" + self.orig_text.replace("\n"," ") + "\" in " + self.containing_file + text += "\n\t" + if self.is_static: + text += "static " + text += self.ret_type.gen_text() + " " + self.member_of.name + "::" + self.name + "(" + for arg in self.args: + text += arg.gen_listitem_cpp() + text += ", " + if len(self.args) > 0: + text = text[:-2] + text += ")\n\t{" + for arg in self.args: + text += arg.gen_translation_cpp() + text += "\n\t\t" + if self.member_of == None: + text += "::" + self.namespace + "::" + self.alias + "(" + elif self.is_static: + text += self.member_of.namespace + "::" + self.member_of.name + "::" + self.name + "(" + else: + text += "py_" + self.alias + "(" + for arg in self.args: + text += arg.gen_call_cpp() + ", " + if len(self.args) > 0: + text = text[:-2] + if self.ret_type.name in classnames: + text += ")" + text += ");" + for arg in self.args: + text += arg.gen_cleanup() + text += "\n\t}\n" + return text + + def gen_default_impl(self): + if self.duplicate: + return "" + if not self.is_virtual: + return "" + text = "\n\n\t\t" + self.ret_type.gen_text() + " py_" + self.alias + "(" + for arg in self.args: + text += arg.gen_listitem() + ", " + if len(self.args) > 0: + text = text[:-2] + + call_string = "py_" + self.alias + "(" + for arg in self.args: + call_string += arg.gen_varname() + ", " + if len(self.args) > 0: + call_string = call_string[0:-2] + call_string += ");" + + text += ")\n\t\t{" + text += "\n\t\t\tif(boost::python::override py_" + self.alias + " = this->get_override(\"py_" + self.alias + "\"))" + text += "\n\t\t\t\t" + call_string + text += "\n\t\t\telse" + text += "\n\t\t\t\t" + self.member_of.name + "::" + call_string + text += "\n\t\t}" + + text += "\n\n\t\t" + self.ret_type.gen_text() + " default_py_" + self.alias + "(" + for arg in self.args: + text += arg.gen_listitem() + ", " + if len(self.args) > 0: + text = text[:-2] + text += ")\n\t\t{" + text += "\n\t\t\tthis->" + self.member_of.name + "::" + call_string + text += "\n\t\t}" + return text + + + def gen_boost_py(self): + if self.duplicate: + return "" + if self.member_of == None: + text = "\n\t\tdef" + else: + text = "\n\t\t\t.def" + if len(self.args) > -1: + if self.ret_type.name in known_containers: + text += "<" + known_containers[self.ret_type.name].typename + " " + else: + text += "<" + self.ret_type.name + " " + if self.member_of == None or self.is_static: + text += "(*)(" + else: + text += "(" + self.member_of.name + "::*)(" + for a in self.args: + text += a.gen_listitem_hash() + ", " + if len(self.args) > 0: + text = text[0:-2] + ")>" + else: + text += "void)>" + + if self.is_operator: + text += "(\"" + wrappable_operators[self.name.replace("operator","")] + "\"" + else: + if self.member_of != None and self.member_of.link_type == link_types.derive and self.is_virtual: + text += "(\"py_" + self.alias + "\"" + else: + text += "(\"" + self.alias + "\"" + if self.member_of != None: + text += ", &" + self.member_of.name + "::" + if self.member_of.link_type == link_types.derive and self.is_virtual: + text += "py_" + self.alias + text += ", &" + self.member_of.name + "Wrap::default_py_" + self.alias + else: + text += self.alias + + text += ")" + else: + text += ", " + "YOSYS_PYTHON::" + self.alias + ");" + return text + +class WMember: + orig_text = None + wtype = attr_types.default + name = None + containing_file = None + member_of = None + namespace = "" + is_const = False + + def from_string(str_def, containing_file, class_, line_number, namespace): + member = WMember() + member.orig_text = str_def + member.wtype = None + member.name = "" + member.containing_file = containing_file + member.member_of = class_ + member.namespace = namespace + member.is_const = False + + if str.startswith(str_def, "const "): + member.is_const = True + str_def = str_def[6:] + + if str_def.count(" ") == 0: + return None + + parts = split_list(str_def.strip(), " ") + + prefix = "" + i = 0 + for part in parts: + if part in ["unsigned", "long", "short"]: + prefix += part + " " + i = i + 1 + else: + break + parts = parts[i:] + + if len(parts) <= 1: + return None + + member.wtype = WType.from_string(prefix + parts[0], containing_file, line_number) + + if member.wtype == None: + return None + + str_def = parts[1] + for part in parts[2:]: + str_def = str_def + " " + part + + if str_def.find("(") != -1 or str_def.find(")") != -1 or str_def.find("{") != -1 or str_def.find("}") != -1: + return None + + found = str_def.find(";") + if found == -1: + return None + + found_eq = str_def.find("=") + if found_eq != -1: + found = found_eq + + member.name = str_def[:found] + str_def = str_def[found+1:] + if member.name.find("*") == 0: + member.name = member.name.replace("*", "") + member.wtype.attr_type = attr_types.star + if member.name.find("&&") == 0: + member.name = member.name.replace("&&", "") + member.wtype.attr_type = attr_types.ampamp + if member.name.find("&") == 0: + member.name = member.name.replace("&", "") + member.wtype.attr_type = attr_types.amp + + if(len(str_def.strip()) != 0): + return None + + if len(member.name.split(",")) > 1: + member_list = [] + for name in member.name.split(","): + name = name.strip(); + member_list.append(WMember()) + member_list[-1].orig_text = member.orig_text + member_list[-1].wtype = member.wtype + member_list[-1].name = name + member_list[-1].containing_file = member.containing_file + member_list[-1].member_of = member.member_of + member_list[-1].namespace = member.namespace + member_list[-1].is_const = member.is_const + return member_list + + return member + + def gen_decl(self): + text = "\n\t\t" + self.wtype.gen_text() + " get_var_py_" + self.name + "();\n" + if self.is_const: + return text + if self.wtype.name in classnames: + text += "\n\t\tvoid set_var_py_" + self.name + "(" + self.wtype.gen_text() + " *rhs);\n" + else: + text += "\n\t\tvoid set_var_py_" + self.name + "(" + self.wtype.gen_text() + " rhs);\n" + return text + + def gen_def(self): + text = "\n\t" + self.wtype.gen_text() + " " + self.member_of.name +"::get_var_py_" + self.name + "()" + text += "\n\t{\n\t\t" + if self.wtype.name in known_containers: + text += self.wtype.gen_text_cpp() + else: + text += self.wtype.gen_text() + + if self.wtype.name in classnames or (self.wtype.name in known_containers and self.wtype.attr_type == attr_types.star): + text += "*" + text += " ret_ = " + if self.wtype.name in classnames: + text += self.wtype.name + "::get_py_obj(" + if self.wtype.attr_type != attr_types.star: + text += "&" + text += "this->get_cpp_obj()->" + self.name + if self.wtype.name in classnames: + text += ")" + text += ";" + + if self.wtype.name in classnames: + text += "\n\t\treturn *ret_;" + elif self.wtype.name in known_containers: + text += known_containers[self.wtype.name].translate_cpp("ret_", self.wtype.cont.args, "\n\t\t", self.wtype.attr_type == attr_types.star) + text += "\n\t\treturn ret____tmp;" + else: + text += "\n\t\treturn ret_;" + text += "\n\t}\n" + + if self.is_const: + return text + + ret = Attribute(self.wtype, "rhs"); + + if self.wtype.name in classnames: + text += "\n\tvoid " + self.member_of.name+ "::set_var_py_" + self.name + "(" + self.wtype.gen_text() + " *rhs)" + else: + text += "\n\tvoid " + self.member_of.name+ "::set_var_py_" + self.name + "(" + self.wtype.gen_text() + " rhs)" + text += "\n\t{" + text += ret.gen_translation() + text += "\n\t\tthis->get_cpp_obj()->" + self.name + " = " + ret.gen_call() + ";" + text += "\n\t}\n" + + return text; + + def gen_boost_py(self): + text = "\n\t\t\t.add_property(\"" + self.name + "\", &" + self.member_of.name + "::get_var_py_" + self.name + if not self.is_const: + text += ", &" + self.member_of.name + "::set_var_py_" + self.name + text += ")" + return text + +def concat_namespace(tuple_list): + if len(tuple_list) == 0: + return "" + ret = "" + for namespace in tuple_list: + ret += "::" + namespace[0] + return ret[2:] + +def calc_ident(text): + if len(text) == 0 or text[0] != ' ': + return 0 + return calc_ident(text[1:]) + 1 + +def assure_length(text, length, left = False): + if len(text) > length: + return text[:length] + if left: + return text + " "*(length - len(text)) + return " "*(length - len(text)) + text + +def parse_header(source): + debug("Parsing " + source.name + ".pyh",1) + source_file = open(source.name + ".pyh", "r") + + source_text = [] + in_line = source_file.readline() + + namespaces = [] + + while(in_line): + if(len(in_line)>1): + source_text.append(in_line.replace("char *", "char_p ").replace("char* ", "char_p ")) + in_line = source_file.readline() + + i = 0 + + namespaces = [] + class_ = None + private_segment = False + + while i < len(source_text): + line = source_text[i].replace("YOSYS_NAMESPACE_BEGIN", " namespace Yosys{").replace("YOSYS_NAMESPACE_END"," }") + ugly_line = unpretty_string(line) + + if str.startswith(ugly_line, "namespace "):# and ugly_line.find("std") == -1 and ugly_line.find("__") == -1: + namespace_name = ugly_line[10:].replace("{","").strip() + namespaces.append((namespace_name, ugly_line.count("{"))) + debug("-----NAMESPACE " + concat_namespace(namespaces) + "-----",3) + i = i + 1 + continue + + if len(namespaces) != 0: + namespaces[-1] = (namespaces[-1][0], namespaces[-1][1] + ugly_line.count("{") - ugly_line.count("}")) + if namespaces[-1][1] == 0: + debug("-----END NAMESPACE " + concat_namespace(namespaces) + "-----",3) + del namespaces[-1] + i = i + 1 + continue + + if class_ == None and (str.startswith(ugly_line, "struct ") or str.startswith(ugly_line, "class")) and ugly_line.count(";") == 0: + + struct_name = ugly_line.split(" ")[1].split("::")[-1] + impl_namespaces = ugly_line.split(" ")[1].split("::")[:-1] + complete_namespace = concat_namespace(namespaces) + for namespace in impl_namespaces: + complete_namespace += "::" + namespace + debug("\tFound " + struct_name + " in " + complete_namespace,2) + class_ = (class_by_name(struct_name), ugly_line.count("{"))#calc_ident(line)) + if struct_name in classnames: + class_[0].namespace = complete_namespace + i = i + 1 + continue + + if class_ != None: + class_ = (class_[0], class_[1] + ugly_line.count("{") - ugly_line.count("}")) + if class_[1] == 0: + if class_[0] == None: + debug("\tExiting unknown class", 3) + else: + debug("\tExiting class " + class_[0].name, 3) + class_ = None + private_segment = False + i = i + 1 + continue + + if class_ != None and (line.find("private:") != -1 or line.find("protected:") != -1): + private_segment = True + i = i + 1 + continue + if class_ != None and line.find("public:") != -1: + private_segment = False + i = i + 1 + continue + + candidate = None + + if private_segment and class_ != None and class_[0] != None: + candidate = WConstructor.from_string(ugly_line, source.name, class_[0], i, True) + if candidate != None: + debug("\t\tFound constructor of class \"" + class_[0].name + "\" in namespace " + concat_namespace(namespaces),2) + class_[0].found_constrs.append(candidate) + i = i + 1 + continue + + if not private_segment and (class_ == None or class_[0] != None): + if class_ != None: + candidate = WFunction.from_string(ugly_line, source.name, class_[0], i, concat_namespace(namespaces)) + else: + candidate = WFunction.from_string(ugly_line, source.name, None, i, concat_namespace(namespaces)) + if candidate != None and candidate.name.find("::") == -1: + if class_ == None: + debug("\tFound unowned function \"" + candidate.name + "\" in namespace " + concat_namespace(namespaces),2) + unowned_functions.append(candidate) + else: + debug("\t\tFound function \"" + candidate.name + "\" of class \"" + class_[0].name + "\" in namespace " + concat_namespace(namespaces),2) + class_[0].found_funs.append(candidate) + else: + candidate = WEnum.from_string(ugly_line, concat_namespace(namespaces), i) + if candidate != None: + enums.append(candidate) + debug("\tFound enum \"" + candidate.name + "\" in namespace " + concat_namespace(namespaces),2) + elif class_ != None and class_[1] == 1: + candidate = WConstructor.from_string(ugly_line, source.name, class_[0], i) + if candidate != None: + debug("\t\tFound constructor of class \"" + class_[0].name + "\" in namespace " + concat_namespace(namespaces),2) + class_[0].found_constrs.append(candidate) + else: + candidate = WMember.from_string(ugly_line, source.name, class_[0], i, concat_namespace(namespaces)) + if candidate != None: + if type(candidate) == list: + for c in candidate: + debug("\t\tFound member \"" + c.name + "\" of class \"" + class_[0].name + "\" of type \"" + c.wtype.name + "\"", 2) + class_[0].found_vars.extend(candidate) + else: + debug("\t\tFound member \"" + candidate.name + "\" of class \"" + class_[0].name + "\" of type \"" + candidate.wtype.name + "\"", 2) + class_[0].found_vars.append(candidate) + + j = i + line = unpretty_string(line) + while candidate == None and j+1 < len(source_text) and line.count(';') <= 1 and line.count("(") >= line.count(")"): + j = j + 1 + line = line + "\n" + unpretty_string(source_text[j]) + if class_ != None: + candidate = WFunction.from_string(ugly_line, source.name, class_[0], i, concat_namespace(namespaces)) + else: + candidate = WFunction.from_string(ugly_line, source.name, None, i, concat_namespace(namespaces)) + if candidate != None and candidate.name.find("::") == -1: + if class_ == None: + debug("\tFound unowned function \"" + candidate.name + "\" in namespace " + concat_namespace(namespaces),2) + unowned_functions.append(candidate) + else: + debug("\t\tFound function \"" + candidate.name + "\" of class \"" + class_[0].name + "\" in namespace " + concat_namespace(namespaces),2) + class_[0].found_funs.append(candidate) + continue + candidate = WEnum.from_string(line, concat_namespace(namespaces), i) + if candidate != None: + enums.append(candidate) + debug("\tFound enum \"" + candidate.name + "\" in namespace " + concat_namespace(namespaces),2) + continue + if class_ != None: + candidate = WConstructor.from_string(line, source.name, class_[0], i) + if candidate != None: + debug("\t\tFound constructor of class \"" + class_[0].name + "\" in namespace " + concat_namespace(namespaces),2) + class_[0].found_constrs.append(candidate) + continue + if candidate != None: + while i < j: + i = i + 1 + line = source_text[i].replace("YOSYS_NAMESPACE_BEGIN", " namespace Yosys{").replace("YOSYS_NAMESPACE_END"," }") + ugly_line = unpretty_string(line) + if len(namespaces) != 0: + namespaces[-1] = (namespaces[-1][0], namespaces[-1][1] + ugly_line.count("{") - ugly_line.count("}")) + if namespaces[-1][1] == 0: + debug("-----END NAMESPACE " + concat_namespace(namespaces) + "-----",3) + del namespaces[-1] + if class_ != None: + class_ = (class_[0] , class_[1] + ugly_line.count("{") - ugly_line.count("}")) + if class_[1] == 0: + if class_[0] == None: + debug("\tExiting unknown class", 3) + else: + debug("\tExiting class " + class_[0].name, 3) + class_ = None + private_segment = False + i = i + 1 + #i = j + 1 + else: + i = i + 1 + +def debug(message, level): + if level <= debug.debug_level: + print(message) + +def expand_function(f): + fun_list = [] + arg_list = [] + for arg in f.args: + if arg.default_value != None and (arg.wtype.name.split(" ")[-1] in primitive_types or arg.wtype.name in enum_names or (arg.wtype.name in classnames and arg.default_value == "nullptr")): + fi = copy.deepcopy(f) + fi.args = copy.deepcopy(arg_list) + fun_list.append(fi) + arg_list.append(arg) + fun_list.append(f) + return fun_list + +def expand_functions(): + global unowned_functions + new_funs = [] + for fun in unowned_functions: + new_funs.extend(expand_function(fun)) + unowned_functions = new_funs + for source in sources: + for class_ in source.classes: + new_funs = [] + for fun in class_.found_funs: + new_funs.extend(expand_function(fun)) + class_.found_funs = new_funs + +def clean_duplicates(): + for source in sources: + for class_ in source.classes: + known_decls = {} + for fun in class_.found_funs: + if fun.gen_decl_hash_py() in known_decls: + debug("Multiple declarations of " + fun.gen_decl_hash_py(),3) + other = known_decls[fun.gen_decl_hash_py()] + other.gen_alias() + fun.gen_alias() + if fun.gen_decl_hash_py() == other.gen_decl_hash_py(): + fun.duplicate = True + debug("Disabled \"" + fun.gen_decl_hash_py() + "\"", 3) + else: + known_decls[fun.gen_decl_hash_py()] = fun + known_decls = [] + for con in class_.found_constrs: + if con.gen_decl_hash_py() in known_decls: + debug("Multiple declarations of " + con.gen_decl_hash_py(),3) + con.duplicate = True + else: + known_decls.append(con.gen_decl_hash_py()) + known_decls = [] + for fun in unowned_functions: + if fun.gen_decl_hash_py() in known_decls: + debug("Multiple declarations of " + fun.gen_decl_hash_py(),3) + fun.duplicate = True + else: + known_decls.append(fun.gen_decl_hash_py()) + +def gen_wrappers(filename, debug_level_ = 30): + debug.debug_level = debug_level_ + for source in sources: + parse_header(source) + + expand_functions() + clean_duplicates() + + import shutil + import math + col = shutil.get_terminal_size((80,20)).columns + debug("-"*col, 1) + debug("-"*math.floor((col-7)/2)+"SUMMARY"+"-"*math.ceil((col-7)/2), 1) + debug("-"*col, 1) + for source in sources: + for class_ in source.classes: + debug("Class " + assure_length(class_.name, len(max(classnames, key=len)), True) + " contains " + assure_length(str(len(class_.found_vars)), 3, False) + " member variables, "+ assure_length(str(len(class_.found_funs)), 3, False) + " methods and " + assure_length(str(len(class_.found_constrs)), 2, False) + " constructors", 1) + if len(class_.found_constrs) == 0: + class_.found_constrs.append(WConstructor(source.name, class_)) + debug(str(len(unowned_functions)) + " functions are unowned", 1) + for enum in enums: + debug("Enum " + assure_length(enum.name, len(max(enum_names, key=len)), True) + " contains " + assure_length(str(len(enum.values)), 2, False) + " values", 1) + debug("-"*col, 1) + wrapper_file = open(filename, "w+") + wrapper_file.write( +"""/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * This is a generated file and can be overwritten by make + */ + +#ifdef WITH_PYTHON +""") + for source in sources: + wrapper_file.write("#include \""+source.name+".h\"\n") + wrapper_file.write(""" +#include +#include +#include +#include +#include +#include + +using namespace Yosys; + +namespace YOSYS_PYTHON { +""") + + for source in sources: + for wclass in source.classes: + wrapper_file.write("\n\tstruct " + wclass.name + ";") + + wrapper_file.write("\n") + + for source in sources: + for wclass in source.classes: + wrapper_file.write(wclass.gen_decl(source.name)) + + wrapper_file.write("\n") + + for source in sources: + for wclass in source.classes: + wrapper_file.write(wclass.gen_funs(source.name)) + + for fun in unowned_functions: + wrapper_file.write(fun.gen_def()) + + wrapper_file.write(""" struct Initializer + { + Initializer() { + if(!Yosys::yosys_already_setup()) + { + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + Yosys::yosys_setup(); + Yosys::yosys_banner(); + } + } + + Initializer(Initializer const &) {} + + ~Initializer() { + Yosys::yosys_shutdown(); + } + }; + + BOOST_PYTHON_MODULE(libyosys) + { + using namespace boost::python; + + class_("Initializer"); + scope().attr("_hidden") = new Initializer(); +""") + + for enum in enums: + wrapper_file.write(enum.gen_boost_py()) + + for source in sources: + for wclass in source.classes: + wrapper_file.write(wclass.gen_boost_py()) + + for fun in unowned_functions: + wrapper_file.write(fun.gen_boost_py()) + + wrapper_file.write("\n\t}\n}\n#endif") + +def print_includes(): + for source in sources: + print(source.name + ".pyh") From a13cba31c99340816cde520f0b51fcb6880c0172 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 25 Oct 2018 15:06:26 +0200 Subject: [PATCH 32/57] removed deletes --- py_wrap_generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py_wrap_generator.py b/py_wrap_generator.py index 204b9146c..f26c15070 100644 --- a/py_wrap_generator.py +++ b/py_wrap_generator.py @@ -805,7 +805,7 @@ class WClass: if self.link_type != link_types.global_list: text += "\n\t\t~" + self.name + "()\n\t\t{" - text += "\n\t\t\tdelete(this->ref_obj);\n\t\t}\n" + text += "\n\t\t\t//delete(this->ref_obj);\n\t\t}\n" for con in self.found_constrs: text += con.gen_decl() From e7880bab20c0c44943f3ec217fc1cb31cc25d393 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 25 Oct 2018 15:06:55 +0200 Subject: [PATCH 33/57] removed debug output from make --- py_wrap_generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py_wrap_generator.py b/py_wrap_generator.py index f26c15070..40b4ddc17 100644 --- a/py_wrap_generator.py +++ b/py_wrap_generator.py @@ -1973,7 +1973,7 @@ def clean_duplicates(): else: known_decls.append(fun.gen_decl_hash_py()) -def gen_wrappers(filename, debug_level_ = 30): +def gen_wrappers(filename, debug_level_ = 0): debug.debug_level = debug_level_ for source in sources: parse_header(source) From 0b81629779f70edf27b77939a3b291ec1ea35102 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 25 Oct 2018 16:19:22 +0200 Subject: [PATCH 34/57] changed dlopen flags to support plugins --- __init__.py | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 __init__.py diff --git a/__init__.py b/__init__.py new file mode 100644 index 000000000..118ba306b --- /dev/null +++ b/__init__.py @@ -0,0 +1,3 @@ +import os +import sys +sys.setdlopenflags(os.RTLD_NOW | os.RTLD_GLOBAL) From 5c59429893b24ff539c65172066a6f343d3dc28e Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 25 Oct 2018 16:32:28 +0200 Subject: [PATCH 35/57] added all variable in __init__.py to allow importing of the whole module --- __init__.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/__init__.py b/__init__.py index 118ba306b..330fd6d86 100644 --- a/__init__.py +++ b/__init__.py @@ -1,3 +1,5 @@ import os import sys sys.setdlopenflags(os.RTLD_NOW | os.RTLD_GLOBAL) + +__all__ = ["libyosys"] From 6577a6924665f54c6db8f12cda5b089247516981 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 6 Dec 2018 12:17:09 +0100 Subject: [PATCH 36/57] throw exception when member is NULL --- py_wrap_generator.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/py_wrap_generator.py b/py_wrap_generator.py index 40b4ddc17..658779ca6 100644 --- a/py_wrap_generator.py +++ b/py_wrap_generator.py @@ -1676,6 +1676,9 @@ class WMember: def gen_def(self): text = "\n\t" + self.wtype.gen_text() + " " + self.member_of.name +"::get_var_py_" + self.name + "()" text += "\n\t{\n\t\t" + if self.wtype.attr_type == attr_types.star: + text += "if(this->get_cpp_obj()->" + self.name + " == NULL)\n\t\t\t" + text += "throw std::runtime_error(\"Member \\\"" + self.name + "\\\" is NULL\");\n\t\t" if self.wtype.name in known_containers: text += self.wtype.gen_text_cpp() else: From c151bb31eb9bc905f3a91803a2f4ea882a254b3c Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 11 Dec 2018 08:13:42 +0100 Subject: [PATCH 37/57] Added sample code for python-api --- examples/python-api/.gitignore | 1 + examples/python-api/netlist_graph.py | 472 +++++++++++++++++++++++++++ examples/python-api/run.sh | 6 + 3 files changed, 479 insertions(+) create mode 100644 examples/python-api/.gitignore create mode 100644 examples/python-api/netlist_graph.py create mode 100755 examples/python-api/run.sh diff --git a/examples/python-api/.gitignore b/examples/python-api/.gitignore new file mode 100644 index 000000000..758de1134 --- /dev/null +++ b/examples/python-api/.gitignore @@ -0,0 +1 @@ +out/** diff --git a/examples/python-api/netlist_graph.py b/examples/python-api/netlist_graph.py new file mode 100644 index 000000000..c8da76e3d --- /dev/null +++ b/examples/python-api/netlist_graph.py @@ -0,0 +1,472 @@ +from libyosys import * +from scipy.sparse import coo_matrix +from numpy import savetxt + +from enum import Enum +class NodeType(Enum): + GRAPH_CELL = 0 + GRAPH_PI = 1 + GRAPH_PO = 2 + GRAPH_CONST = 3 + GRAPH_WIRE = 4 + +class NetlistElement: + + def __init__(self, design, module, name): + self.design = design + self.module = module + self.name = name + +class Bit(NetlistElement): + + def __init__(self, bit, design, module, node, port, pos): + super().__init__(design, module, IdString("\\__BIT__")) + self.bit = bit + self.node = node + self.port = port + self.pos = pos + +class Port(NetlistElement): + + def __init__(self, name): + super().__init__(None, None, name) + self.input = False + self.output = False + self.bits = [] + +class Node(NetlistElement): + + def __init__(self, design, module, name, nodeType): + super().__init__(design, module, name) + self.nodeType = nodeType + self.ports = [] + + def __lt__(self, other): + if isinstance(other, self.__class): + if self.type == other.type: + return self.name.str() < other.name.str() + return self.type < other.type + return False + +class PyCell(Node): + + def __init__(self, design, module, name, cell): + super().__init__(design, module, name, NodeType.GRAPH_CELL) + self.cell = cell + +class PyWire(Node): + + def __init__(self, design, module, name): + super().__init__(design, module, name, NodeType.GRAPH_WIRE) + +class NetlistGraph: + + def __init__(self, design, module = None): + self.design = design + if module != None: + self.module = module + else: + self.module = list(design.modules_.values())[0] + self.cells = [] + self.wires = [] + self.nodes = [] + self.node_bits = [] + self.wire_bits = [] + self.node_index = {} + self.node_bit_index = {} + self.wire_bit_index = {} + + self.incoming = None + self.outgoing = None + self.create() + + def create(self): + + log_header(self.design, "Creating abstract graph representation of " + + "module " + self.module.name.str() + "\n") + log_push() + + sigmap = SigMap(self.module) + + log(" Creating const node\n") + const_node = Node(self.design, self.module, IdString("\\__CONST__"), NodeType.GRAPH_CONST) + const_port = Port(IdString("\\__CONST__")) + const_port.input = False + const_port.output = True + cb = SigBit(State.Sx) + const_bit = Bit(cb, self.design, self.module, const_node, const_port, 0) + const_node.ports.append(const_port) + const_port.bits.append(const_bit) + + self.nodes.append(const_node) + self.wires.append(const_node) + log(" Creating cell nodes\n") + + for cell in self.module.selected_cells(): + c = PyCell(self.design, self.module, cell.name, cell) + for first, second in cell.connections_.items(): + p = Port(first) + p.input = cell.input(p.name) + p.output = cell.output(p.name) + for bit in sigmap(second).to_sigbit_vector(): + b = Bit(bit, self.design, self.module, c, p, len(p.bits)) + p.bits.append(b) + c.ports.append(p) + + self.cells.append(c) + + log(" Creating wire nodes\n") + + for wire in self.module.selected_wires(): + node = PyWire(self.design, self.module, wire.name) + p = Port(IdString("")) + if wire.port_input: + node.nodeType = NodeType.GRAPH_PI + p.name = IdString("\\PI") + p.input = False + p.output = True + elif wire.port_output: + node.nodeType = NodeType.GRAPH_PO + p.name = IdString("\\PO") + p.input = True + p.output = False + for bit in sigmap(wire).to_sigbit_set(): + b = Bit(bit, self.design, self.module, node, p, len(p.bits)) + p.bits.append(b) + node.ports.append(p) + self.wires.append(node) + + self.nodes.extend(self.cells) + self.nodes.extend(wire for wire in self.wires if wire.nodeType in [NodeType.GRAPH_PI, NodeType.GRAPH_PO]) + + log(" Creating node index for fast lookup\n") + + idx = 0 + + for node in self.nodes: + self.node_index[node.name] = idx + idx += 1 + + log(" Creating node bits (= const + cell + PI + PO)\n") + + for node in self.nodes: + for port in node.ports: + for bit in port.bits: + self.node_bits.append(bit) + + log(" Creating wire bits\n") + + for wire in self.wires: + for port in wire.ports: + for bit in port.bits: + self.wire_bits.append(bit) + + log(" Creating node bit index for fast lookup\n") + + idx = 0 + + for bit in self.node_bits: + self.node_bit_index[bit] = idx + idx += 1 + + log(" Creating wire bit index for fast lookup\n") + + idx = 0 + + for bit in self.wire_bits: + self.wire_bit_index[bit] = idx + idx += 1 + + log(" Mapping port.wire connections to wire bit index\n") + + idx = 0 + + wbitmap = {} + for wbit in self.wire_bits: + wbitmap[wbit.bit] = idx + idx += 1 + + inputTriplets = [] + outputTriplets = [(0,0,1)] + + log(" Mapping node bits to wire bits\n") + + idx = 0 + + for nbit in self.node_bits: + row = idx + idx += 1 + col = 0 + val = 1 + + def check_wire(): + nonlocal nbit + try: + wire = nbit.bit.wire + return True + except: + return False + + if check_wire() and not self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name): + continue + + if check_wire(): + col = wbitmap[nbit.bit] + + triplet = (row, col, val) + + if col == 0 and row != 0: + inputTriplets.append(triplet) + continue + + if nbit.node.nodeType == NodeType.GRAPH_CELL: + cell = nbit.node + if check_wire() and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name): + if cell.cell.input(nbit.port.name): + inputTriplets.append(triplet) + if cell.cell.output(nbit.port.name): + outputTriplets.append(triplet) + continue + + if nbit.node.nodeType == NodeType.GRAPH_PI and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name): + outputTriplets.append(triplet) + continue + + if nbit.node.nodeType == NodeType.GRAPH_PO and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name): + inputTriplets.append(triplet) + continue + + log(" Creating port-to-wire incidence matrices\n") + + sizeX = len(self.node_bits) + sizeY= len(self.wire_bits) + + inputRows = [i[0] for i in inputTriplets] + inputCols = [i[1] for i in inputTriplets] + inputVals = [i[2] for i in inputTriplets] + self.incoming = coo_matrix((inputVals, (inputRows, inputCols)), shape=(sizeX, sizeY), dtype='int32') + + outputRows = [i[0] for i in outputTriplets] + outputCols = [i[1] for i in outputTriplets] + outputVals = [i[2] for i in outputTriplets] + self.outgoing = coo_matrix((outputVals, (outputRows, outputCols)), shape=(sizeX, sizeY), dtype='int32') + + def dot(self): + log_header(self.design, "Creating 'dot' bipartite module graph representation of module " + self.module.name.str() + "\n") + log_push() + bitmap = {} + + ss = "digraph g{\n" + ss += " rankdir = LR\n" + nidx = 0 + pidx = 0 + bidx = 0 + cells_wires = [] + cells_wires.extend(self.cells) + cells_wires.extend(self.wires) + + idx = 0 + + for node in cells_wires: + for port in node.ports: + for bit in port.bits: + bitmap[bit] = idx + idx += 1 + + for node in cells_wires: + ss += " subgraph cluster" + str(nidx) + " {\n" + ss += " style = \"setlinewidth(2)\";\n" + ss += " margin = .2;\n" + ss += " n" + str(node.name.index_) + + def s_cell(): + nonlocal ss + ss += "[shape=ellipse,label=\"" + str(nidx) + ":" + ss += unescape_id(node.cell.type) + "\"" + def s_pi(): + nonlocal ss + ss += "[shape = box, label=\"" + str(nidx) + ":" + ss += unescape_id(node.name.str()) + "\"" + def s_po(): + nonlocal ss + ss += "[shape = diamond, label=\"" + str(nidx) + ":" + ss += unescape_id(node.name.str()) + "\"" + def s_const(): + nonlocal ss + ss += "[shape = octagon, label=\"" + str(nidx) + ":CO\"" + def s_wire(): + nonlocal ss + ss += "[shape = plaintext, label=\"" + str(nidx - len(self.cells)) + ":" + ss += unescape_id(node.name.str()) + "\"" + switch = { + NodeType.GRAPH_CELL : s_cell, + NodeType.GRAPH_PI : s_pi, + NodeType.GRAPH_PO : s_po, + NodeType.GRAPH_CONST : s_const, + NodeType.GRAPH_WIRE : s_wire + } + switch[node.nodeType]() + + ss += "];\n" + + pidx = 0 + for port in node.ports: + ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_) + ss += "[shape=none,label=<\n" + ss += " \n" + ss += " \n" + + bidx = 0; + for bit in port.bits: + + ss += " \n" + + bidx += 1 + + ss += "
" + ss += unescape_id(port.name.str()) + ss += "
" + str(bitmap[bit]) + ":" + str(bidx) + "
\n >];\n" + + if node.nodeType == NodeType.GRAPH_CELL: + if node.cell.output(port.name): + ss += " n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n" + else: + ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) + ";\n" + if node.nodeType == NodeType.GRAPH_PI or node.nodeType == NodeType.GRAPH_CONST: + ss += " n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n" + if node.nodeType == NodeType.GRAPH_PO: + ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) + ";\n" + + pidx += 1 + ss += " }\n" + nidx += 1 + + for i in range(len(self.incoming.nonzero()[0])): + b1 = self.node_bits[self.incoming.nonzero()[0][i]] + b2 = self.wire_bits[self.incoming.nonzero()[1][i]] + + if b1.node.nodeType == NodeType.GRAPH_PO or b1.node.nodeType == NodeType.GRAPH_CONST: + continue + + ss += " " + ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":" + ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos) + ss += " -> " + ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":" + ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos) + ss += ";\n" + + for i in range(len(self.outgoing.nonzero()[0])): + b1 = self.node_bits[self.outgoing.nonzero()[0][i]] + b2 = self.wire_bits[self.outgoing.nonzero()[1][i]] + + if b1.node.nodeType == NodeType.GRAPH_PI: + continue + + ss += " " + ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":" + ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos) + ss += " -> " + ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":" + ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos) + ss += ";\n" + + ss += "}\n" + + log_pop() + + return ss + + def save_dot(self, filename): + savetxt(filename, [self.dot()], fmt="%s") + + def save_incoming(self, filename, delimiter = ","): + savetxt(filename, self.incoming.todense(), "%d", delimiter=delimiter) + + def save_outgoing(self, filename, delimiter = ","): + savetxt(filename, self.outgoing.todense(), "%d", delimiter=delimiter) + + def save_adjacency(self, filename, delimiter = ","): + savetxt(filename, (self.outgoing*self.incoming.transpose()).todense(), "%d", delimiter=delimiter) + +p = None + +class NetlistGraphPass(Pass): + + def __init__(self): + super().__init__("netlist_graph", "Generates the Netlist-Graph of a module") + + import argparse + self.parser = argparse.ArgumentParser() + + self.parser.add_argument("-mod", nargs=1, metavar="MOD", help="The Netlist-Graph of the module with the id-string will be generated. If this argument is not given, the first module will be used") + self.parser.add_argument("-dot", nargs=1, metavar="FILE", help="Write the Netlist-Graph to FILE in dot format") + self.parser.add_argument("-i","-incoming", nargs=1, metavar="FILE", help="Write the incoming incidence matrix to FILE in csv format") + self.parser.add_argument("-o","-outgoing", nargs=1, metavar="FILE", help="Write the outgoing incidence matrix to FILE in csv format") + self.parser.add_argument("-a","-adjacency", nargs=1, metavar="FILE", help="Write the adjacency matrix to FILE in csv format") + + def py_help(self): + + log("This pass generates the Netlist-Graph of a module\n") + log(self.parser.format_help()) + + def py_execute(self, args, des): + + args = self.parser.parse_args(args[1:]) + + graph = None + if args.mod: + try: + graph = NetlistGraph(des, des.modules_[IdString(args.mod[0])]) + except KeyError: + log("Module \"" + args.mod[0] + "\" not found!\n") + exit() + else: + graph = NetlistGraph(des, list(des.modules_.values())[0]) + + if args.dot: + graph.save_dot(args.dot[0]) + + if args.i: + graph.save_incoming(args.i[0]) + + if args.o: + graph.save_outgoing(args.o[0]) + + if args.a: + graph.save_adjacency(args.a[0]) + + def py_clear_flags(self): + log("Clear\n") + +if __name__ == "__main__": + + designs = {} + graphs = {} + + testdir = "../../tests/simple/" + + import os + for testcase in os.listdir(testdir): + if not testcase.endswith(".v"): + continue + designs[testcase] = Design() + run_pass("read_verilog " + testdir + testcase, designs[testcase]) + run_pass("hierarchy -check -auto-top", designs[testcase]) + run_pass("proc", designs[testcase]) + run_pass("clean", designs[testcase]) + run_pass("memory", designs[testcase]) + run_pass("clean", designs[testcase]) + run_pass("opt -full", designs[testcase]) + run_pass("clean", designs[testcase]) + graphs[testcase] = NetlistGraph(designs[testcase]) + + file_prefix = "out/" + testcase + graphs[testcase].save_dot(file_prefix + ".dot") + graphs[testcase].save_incoming(file_prefix + "_in.csv") + graphs[testcase].save_outgoing(file_prefix + "_out.csv") + graphs[testcase].save_adjacency(file_prefix + "_adjacency.csv") + +else: + p = NetlistGraphPass() diff --git a/examples/python-api/run.sh b/examples/python-api/run.sh new file mode 100755 index 000000000..5852ea9ac --- /dev/null +++ b/examples/python-api/run.sh @@ -0,0 +1,6 @@ +PYTHONPATH=`pwd`/../../:$PYTHONPATH +mkdir -p out +if [ ! -f ../../libyosys.so ]; then + make -C ../.. +fi +python3.5 netlist_graph.py From 7ca9fa64f7438cc4238b9245defd72a242da0fe7 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 11 Dec 2018 08:42:57 +0100 Subject: [PATCH 38/57] Added python-api to install --- Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Makefile b/Makefile index e1d66e566..c1943758a 100644 --- a/Makefile +++ b/Makefile @@ -20,6 +20,7 @@ ENABLE_PROTOBUF := 0 # python wrappers ENABLE_PYTHON := 1 PYTHON_VERSION := 3.5 +PYTHON_DESTDIR := /usr/local/lib/python$(PYTHON_VERSION)/dist-packages # other configuration flags ENABLE_GPROF := 0 @@ -602,6 +603,11 @@ ifeq ($(ENABLE_LIBYOSYS),1) $(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(LIBDIR) $(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(LIBDIR)/libyosys.so $(INSTALL_SUDO) ldconfig +ifeq ($(ENABLE_PYTHON),1) + $(INSTALL_SUDO) mkdir -p $(PYTHON_DESTDIR)/libyosys + $(INSTALL_SUDO) cp libyosys.so $(PYTHON_DESTDIR)/libyosys + $(INSTALL_SUDO) cp __init__.py $(PYTHON_DESTDIR)/libyosys +endif endif uninstall: @@ -609,6 +615,11 @@ uninstall: $(INSTALL_SUDO) rm -rvf $(DESTDIR)$(DATDIR) ifeq ($(ENABLE_LIBYOSYS),1) $(INSTALL_SUDO) rm -vf $(DESTDIR)$(LIBDIR)/libyosys.so +ifeq ($(ENABLE_PYTHON),1) + $(INSTALL_SUDO) rm -vf $(PYTHON_DESTDIR)/libyosys/libyosys.so + $(INSTALL_SUDO) rm -vf $(PYTHON_DESTDIR)/libyosys/__init__.py + $(INSTALL_SUDO) rmdir $(PYTHON_DESTDIR)/libyosys +endif endif update-manual: $(TARGETS) $(EXTRA_TARGETS) From b9288b216dce110ad11eb0615a6a911a9fcae05b Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Fri, 21 Dec 2018 14:08:23 +0100 Subject: [PATCH 39/57] Make can now install Python libraries to system path --- Makefile | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index c1943758a..de1e2c404 100644 --- a/Makefile +++ b/Makefile @@ -18,7 +18,7 @@ ENABLE_LIBYOSYS := 1 ENABLE_PROTOBUF := 0 # python wrappers -ENABLE_PYTHON := 1 +ENABLE_PYOSYS := 1 PYTHON_VERSION := 3.5 PYTHON_DESTDIR := /usr/local/lib/python$(PYTHON_VERSION)/dist-packages @@ -233,7 +233,7 @@ ifeq ($(ENABLE_LIBYOSYS),1) TARGETS += libyosys.so endif -ifeq ($(ENABLE_PYTHON),1) +ifeq ($(ENABLE_PYOSYS),1) LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON PY_WRAPPER_FILE = kernel/python_wrappers @@ -603,10 +603,10 @@ ifeq ($(ENABLE_LIBYOSYS),1) $(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(LIBDIR) $(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(LIBDIR)/libyosys.so $(INSTALL_SUDO) ldconfig -ifeq ($(ENABLE_PYTHON),1) - $(INSTALL_SUDO) mkdir -p $(PYTHON_DESTDIR)/libyosys - $(INSTALL_SUDO) cp libyosys.so $(PYTHON_DESTDIR)/libyosys - $(INSTALL_SUDO) cp __init__.py $(PYTHON_DESTDIR)/libyosys +ifeq ($(ENABLE_PYOSYS),1) + $(INSTALL_SUDO) mkdir -p $(PYTHON_DESTDIR)/pyosys + $(INSTALL_SUDO) cp libyosys.so $(PYTHON_DESTDIR)/pyosys + $(INSTALL_SUDO) cp __init__.py $(PYTHON_DESTDIR)/pyosys endif endif @@ -615,10 +615,10 @@ uninstall: $(INSTALL_SUDO) rm -rvf $(DESTDIR)$(DATDIR) ifeq ($(ENABLE_LIBYOSYS),1) $(INSTALL_SUDO) rm -vf $(DESTDIR)$(LIBDIR)/libyosys.so -ifeq ($(ENABLE_PYTHON),1) - $(INSTALL_SUDO) rm -vf $(PYTHON_DESTDIR)/libyosys/libyosys.so - $(INSTALL_SUDO) rm -vf $(PYTHON_DESTDIR)/libyosys/__init__.py - $(INSTALL_SUDO) rmdir $(PYTHON_DESTDIR)/libyosys +ifeq ($(ENABLE_PYOSYS),1) + $(INSTALL_SUDO) rm -vf $(PYTHON_DESTDIR)/pyosys/libyosys.so + $(INSTALL_SUDO) rm -vf $(PYTHON_DESTDIR)/pyosys/__init__.py + $(INSTALL_SUDO) rmdir $(PYTHON_DESTDIR)/pyosys endif endif From 072c9393805d59b988f93b184356c54731237a5a Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 1 Apr 2019 13:36:01 +0200 Subject: [PATCH 40/57] Fixed identation --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index ceb1d1d39..a12355f1d 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -63,7 +63,7 @@ extern "C" PyObject* INIT_MODULE(); #else # define INIT_MODULE initlibyosys - extern "C" void INIT_MODULE(); + extern "C" void INIT_MODULE(); #endif #endif From 7472c5268663ce5f97cf58ea5fb805c45e1f4b0f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 1 Apr 2019 13:39:38 +0200 Subject: [PATCH 41/57] Use addition assignment operator --- py_wrap_generator.py | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/py_wrap_generator.py b/py_wrap_generator.py index 658779ca6..ec5b4b71a 100644 --- a/py_wrap_generator.py +++ b/py_wrap_generator.py @@ -1263,7 +1263,7 @@ class WFunction: for part in parts: if part in ["unsigned", "long", "short"]: prefix += part + " " - i = i + 1 + i += 1 else: break parts = parts[i:] @@ -1604,7 +1604,7 @@ class WMember: for part in parts: if part in ["unsigned", "long", "short"]: prefix += part + " " - i = i + 1 + i += 1 else: break parts = parts[i:] @@ -1776,7 +1776,7 @@ def parse_header(source): namespace_name = ugly_line[10:].replace("{","").strip() namespaces.append((namespace_name, ugly_line.count("{"))) debug("-----NAMESPACE " + concat_namespace(namespaces) + "-----",3) - i = i + 1 + i += 1 continue if len(namespaces) != 0: @@ -1784,7 +1784,7 @@ def parse_header(source): if namespaces[-1][1] == 0: debug("-----END NAMESPACE " + concat_namespace(namespaces) + "-----",3) del namespaces[-1] - i = i + 1 + i += 1 continue if class_ == None and (str.startswith(ugly_line, "struct ") or str.startswith(ugly_line, "class")) and ugly_line.count(";") == 0: @@ -1798,7 +1798,7 @@ def parse_header(source): class_ = (class_by_name(struct_name), ugly_line.count("{"))#calc_ident(line)) if struct_name in classnames: class_[0].namespace = complete_namespace - i = i + 1 + i += 1 continue if class_ != None: @@ -1810,16 +1810,16 @@ def parse_header(source): debug("\tExiting class " + class_[0].name, 3) class_ = None private_segment = False - i = i + 1 + i += 1 continue if class_ != None and (line.find("private:") != -1 or line.find("protected:") != -1): private_segment = True - i = i + 1 + i += 1 continue if class_ != None and line.find("public:") != -1: private_segment = False - i = i + 1 + i += 1 continue candidate = None @@ -1829,7 +1829,7 @@ def parse_header(source): if candidate != None: debug("\t\tFound constructor of class \"" + class_[0].name + "\" in namespace " + concat_namespace(namespaces),2) class_[0].found_constrs.append(candidate) - i = i + 1 + i += 1 continue if not private_segment and (class_ == None or class_[0] != None): @@ -1868,7 +1868,7 @@ def parse_header(source): j = i line = unpretty_string(line) while candidate == None and j+1 < len(source_text) and line.count(';') <= 1 and line.count("(") >= line.count(")"): - j = j + 1 + j += 1 line = line + "\n" + unpretty_string(source_text[j]) if class_ != None: candidate = WFunction.from_string(ugly_line, source.name, class_[0], i, concat_namespace(namespaces)) @@ -1895,7 +1895,7 @@ def parse_header(source): continue if candidate != None: while i < j: - i = i + 1 + i += 1 line = source_text[i].replace("YOSYS_NAMESPACE_BEGIN", " namespace Yosys{").replace("YOSYS_NAMESPACE_END"," }") ugly_line = unpretty_string(line) if len(namespaces) != 0: @@ -1912,10 +1912,9 @@ def parse_header(source): debug("\tExiting class " + class_[0].name, 3) class_ = None private_segment = False - i = i + 1 - #i = j + 1 + i += 1 else: - i = i + 1 + i += 1 def debug(message, level): if level <= debug.debug_level: From 2586e091189534144426df0c6f0af60563cb4811 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 1 Apr 2019 15:05:30 +0200 Subject: [PATCH 42/57] Removed generation of commented-out code --- py_wrap_generator.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/py_wrap_generator.py b/py_wrap_generator.py index ec5b4b71a..aa2c46b2c 100644 --- a/py_wrap_generator.py +++ b/py_wrap_generator.py @@ -803,10 +803,6 @@ class WClass: text += "\n\t\t\treturn ret;" text += "\n\t\t}\n" - if self.link_type != link_types.global_list: - text += "\n\t\t~" + self.name + "()\n\t\t{" - text += "\n\t\t\t//delete(this->ref_obj);\n\t\t}\n" - for con in self.found_constrs: text += con.gen_decl() for var in self.found_vars: From adfd8d463dcc222843eebe2186bc274228d06acc Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 11:17:50 +0200 Subject: [PATCH 43/57] Autodetect highest installed python version --- Makefile | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 80b12c826..6f7448843 100644 --- a/Makefile +++ b/Makefile @@ -21,7 +21,9 @@ ENABLE_PROTOBUF := 0 # python wrappers ENABLE_PYOSYS := 1 -PYTHON_VERSION := 3.5 +PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)" +PYTHON_VERSION := $(shell if python3 -c ""; then python3 -c ""$(PYTHON_VERSION_TESTCODE)""; else python -c ""$(PYTHON_VERSION_TESTCODE)""; fi) +PYTHON_MAJOR_VERSION := $(shell echo $(PYTHON_VERSION) | cut -f1 -d.) PYTHON_DESTDIR := /usr/local/lib/python$(PYTHON_VERSION)/dist-packages # other configuration flags @@ -267,7 +269,11 @@ TARGETS += libyosys.so endif ifeq ($(ENABLE_PYOSYS),1) -LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system + ifeq ($(PYTHON_MAJOR_VERSION),3) + LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system + else + LDLIBS += -lpython$(PYTHON_VERSION) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system + endif CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON PY_WRAPPER_FILE = kernel/python_wrappers OBJS += $(PY_WRAPPER_FILE).o From d287596be3ea5bc623b27e958c427b991f3400bd Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 11:18:34 +0200 Subject: [PATCH 44/57] Added dependencies to README and travis configuration --- .travis.yml | 15 +++++++++++++++ README.md | 9 +++++---- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/.travis.yml b/.travis.yml index 7c6e4e43c..c97294960 100644 --- a/.travis.yml +++ b/.travis.yml @@ -32,6 +32,9 @@ matrix: - xdot - pkg-config - python + - python3 + - libboost-system-dev + - libboost-python-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8" @@ -56,6 +59,9 @@ matrix: - xdot - pkg-config - python + - python3 + - libboost-system-dev + - libboost-python-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-6 && CXX=g++-6" @@ -80,6 +86,9 @@ matrix: - xdot - pkg-config - python + - python3 + - libboost-system-dev + - libboost-python-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7" @@ -105,6 +114,9 @@ matrix: - xdot - pkg-config - python + - python3 + - libboost-system-dev + - libboost-python-dev env: - MATRIX_EVAL="CONFIG=clang && CC=clang-3.8 && CXX=clang++-3.8" @@ -129,6 +141,9 @@ matrix: - xdot - pkg-config - python + - python3 + - libboost-system-dev + - libboost-python-dev env: - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0" diff --git a/README.md b/README.md index 4048ecbc7..87c2adcce 100644 --- a/README.md +++ b/README.md @@ -66,25 +66,26 @@ prerequisites for building yosys: $ sudo apt-get install build-essential clang bison flex \ libreadline-dev gawk tcl-dev libffi-dev git \ - graphviz xdot pkg-config python3 + graphviz xdot pkg-config python3 libboost-system-dev \ + libboost-python-dev Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies: $ brew tap Homebrew/bundle && brew bundle $ sudo port install bison flex readline gawk libffi \ - git graphviz pkgconfig python36 + git graphviz pkgconfig python36 boost On FreeBSD use the following command to install all prerequisites: # pkg install bison flex readline gawk libffi\ - git graphviz pkgconfig python3 python36 tcl-wrapper + git graphviz pkgconfig python3 python36 tcl-wrapper boost-libs On FreeBSD system use gmake instead of make. To run tests use: % MAKE=gmake CC=cc gmake test For Cygwin use the following command to install all prerequisites, or select these additional packages: - setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel + setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well as a source distribution for Visual Studio. Visit the Yosys download page for From 539a7f3fbce2f27f0de9a298993b13623c5c8f95 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 11:24:50 +0200 Subject: [PATCH 45/57] Added cell_stats example --- examples/python-api/netlist_graph.py | 472 --------------------------- examples/python-api/pass.py | 32 ++ examples/python-api/run.sh | 6 - examples/python-api/script.py | 22 ++ 4 files changed, 54 insertions(+), 478 deletions(-) delete mode 100644 examples/python-api/netlist_graph.py create mode 100755 examples/python-api/pass.py delete mode 100755 examples/python-api/run.sh create mode 100755 examples/python-api/script.py diff --git a/examples/python-api/netlist_graph.py b/examples/python-api/netlist_graph.py deleted file mode 100644 index c8da76e3d..000000000 --- a/examples/python-api/netlist_graph.py +++ /dev/null @@ -1,472 +0,0 @@ -from libyosys import * -from scipy.sparse import coo_matrix -from numpy import savetxt - -from enum import Enum -class NodeType(Enum): - GRAPH_CELL = 0 - GRAPH_PI = 1 - GRAPH_PO = 2 - GRAPH_CONST = 3 - GRAPH_WIRE = 4 - -class NetlistElement: - - def __init__(self, design, module, name): - self.design = design - self.module = module - self.name = name - -class Bit(NetlistElement): - - def __init__(self, bit, design, module, node, port, pos): - super().__init__(design, module, IdString("\\__BIT__")) - self.bit = bit - self.node = node - self.port = port - self.pos = pos - -class Port(NetlistElement): - - def __init__(self, name): - super().__init__(None, None, name) - self.input = False - self.output = False - self.bits = [] - -class Node(NetlistElement): - - def __init__(self, design, module, name, nodeType): - super().__init__(design, module, name) - self.nodeType = nodeType - self.ports = [] - - def __lt__(self, other): - if isinstance(other, self.__class): - if self.type == other.type: - return self.name.str() < other.name.str() - return self.type < other.type - return False - -class PyCell(Node): - - def __init__(self, design, module, name, cell): - super().__init__(design, module, name, NodeType.GRAPH_CELL) - self.cell = cell - -class PyWire(Node): - - def __init__(self, design, module, name): - super().__init__(design, module, name, NodeType.GRAPH_WIRE) - -class NetlistGraph: - - def __init__(self, design, module = None): - self.design = design - if module != None: - self.module = module - else: - self.module = list(design.modules_.values())[0] - self.cells = [] - self.wires = [] - self.nodes = [] - self.node_bits = [] - self.wire_bits = [] - self.node_index = {} - self.node_bit_index = {} - self.wire_bit_index = {} - - self.incoming = None - self.outgoing = None - self.create() - - def create(self): - - log_header(self.design, "Creating abstract graph representation of " - + "module " + self.module.name.str() + "\n") - log_push() - - sigmap = SigMap(self.module) - - log(" Creating const node\n") - const_node = Node(self.design, self.module, IdString("\\__CONST__"), NodeType.GRAPH_CONST) - const_port = Port(IdString("\\__CONST__")) - const_port.input = False - const_port.output = True - cb = SigBit(State.Sx) - const_bit = Bit(cb, self.design, self.module, const_node, const_port, 0) - const_node.ports.append(const_port) - const_port.bits.append(const_bit) - - self.nodes.append(const_node) - self.wires.append(const_node) - log(" Creating cell nodes\n") - - for cell in self.module.selected_cells(): - c = PyCell(self.design, self.module, cell.name, cell) - for first, second in cell.connections_.items(): - p = Port(first) - p.input = cell.input(p.name) - p.output = cell.output(p.name) - for bit in sigmap(second).to_sigbit_vector(): - b = Bit(bit, self.design, self.module, c, p, len(p.bits)) - p.bits.append(b) - c.ports.append(p) - - self.cells.append(c) - - log(" Creating wire nodes\n") - - for wire in self.module.selected_wires(): - node = PyWire(self.design, self.module, wire.name) - p = Port(IdString("")) - if wire.port_input: - node.nodeType = NodeType.GRAPH_PI - p.name = IdString("\\PI") - p.input = False - p.output = True - elif wire.port_output: - node.nodeType = NodeType.GRAPH_PO - p.name = IdString("\\PO") - p.input = True - p.output = False - for bit in sigmap(wire).to_sigbit_set(): - b = Bit(bit, self.design, self.module, node, p, len(p.bits)) - p.bits.append(b) - node.ports.append(p) - self.wires.append(node) - - self.nodes.extend(self.cells) - self.nodes.extend(wire for wire in self.wires if wire.nodeType in [NodeType.GRAPH_PI, NodeType.GRAPH_PO]) - - log(" Creating node index for fast lookup\n") - - idx = 0 - - for node in self.nodes: - self.node_index[node.name] = idx - idx += 1 - - log(" Creating node bits (= const + cell + PI + PO)\n") - - for node in self.nodes: - for port in node.ports: - for bit in port.bits: - self.node_bits.append(bit) - - log(" Creating wire bits\n") - - for wire in self.wires: - for port in wire.ports: - for bit in port.bits: - self.wire_bits.append(bit) - - log(" Creating node bit index for fast lookup\n") - - idx = 0 - - for bit in self.node_bits: - self.node_bit_index[bit] = idx - idx += 1 - - log(" Creating wire bit index for fast lookup\n") - - idx = 0 - - for bit in self.wire_bits: - self.wire_bit_index[bit] = idx - idx += 1 - - log(" Mapping port.wire connections to wire bit index\n") - - idx = 0 - - wbitmap = {} - for wbit in self.wire_bits: - wbitmap[wbit.bit] = idx - idx += 1 - - inputTriplets = [] - outputTriplets = [(0,0,1)] - - log(" Mapping node bits to wire bits\n") - - idx = 0 - - for nbit in self.node_bits: - row = idx - idx += 1 - col = 0 - val = 1 - - def check_wire(): - nonlocal nbit - try: - wire = nbit.bit.wire - return True - except: - return False - - if check_wire() and not self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name): - continue - - if check_wire(): - col = wbitmap[nbit.bit] - - triplet = (row, col, val) - - if col == 0 and row != 0: - inputTriplets.append(triplet) - continue - - if nbit.node.nodeType == NodeType.GRAPH_CELL: - cell = nbit.node - if check_wire() and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name): - if cell.cell.input(nbit.port.name): - inputTriplets.append(triplet) - if cell.cell.output(nbit.port.name): - outputTriplets.append(triplet) - continue - - if nbit.node.nodeType == NodeType.GRAPH_PI and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name): - outputTriplets.append(triplet) - continue - - if nbit.node.nodeType == NodeType.GRAPH_PO and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name): - inputTriplets.append(triplet) - continue - - log(" Creating port-to-wire incidence matrices\n") - - sizeX = len(self.node_bits) - sizeY= len(self.wire_bits) - - inputRows = [i[0] for i in inputTriplets] - inputCols = [i[1] for i in inputTriplets] - inputVals = [i[2] for i in inputTriplets] - self.incoming = coo_matrix((inputVals, (inputRows, inputCols)), shape=(sizeX, sizeY), dtype='int32') - - outputRows = [i[0] for i in outputTriplets] - outputCols = [i[1] for i in outputTriplets] - outputVals = [i[2] for i in outputTriplets] - self.outgoing = coo_matrix((outputVals, (outputRows, outputCols)), shape=(sizeX, sizeY), dtype='int32') - - def dot(self): - log_header(self.design, "Creating 'dot' bipartite module graph representation of module " + self.module.name.str() + "\n") - log_push() - bitmap = {} - - ss = "digraph g{\n" - ss += " rankdir = LR\n" - nidx = 0 - pidx = 0 - bidx = 0 - cells_wires = [] - cells_wires.extend(self.cells) - cells_wires.extend(self.wires) - - idx = 0 - - for node in cells_wires: - for port in node.ports: - for bit in port.bits: - bitmap[bit] = idx - idx += 1 - - for node in cells_wires: - ss += " subgraph cluster" + str(nidx) + " {\n" - ss += " style = \"setlinewidth(2)\";\n" - ss += " margin = .2;\n" - ss += " n" + str(node.name.index_) - - def s_cell(): - nonlocal ss - ss += "[shape=ellipse,label=\"" + str(nidx) + ":" - ss += unescape_id(node.cell.type) + "\"" - def s_pi(): - nonlocal ss - ss += "[shape = box, label=\"" + str(nidx) + ":" - ss += unescape_id(node.name.str()) + "\"" - def s_po(): - nonlocal ss - ss += "[shape = diamond, label=\"" + str(nidx) + ":" - ss += unescape_id(node.name.str()) + "\"" - def s_const(): - nonlocal ss - ss += "[shape = octagon, label=\"" + str(nidx) + ":CO\"" - def s_wire(): - nonlocal ss - ss += "[shape = plaintext, label=\"" + str(nidx - len(self.cells)) + ":" - ss += unescape_id(node.name.str()) + "\"" - switch = { - NodeType.GRAPH_CELL : s_cell, - NodeType.GRAPH_PI : s_pi, - NodeType.GRAPH_PO : s_po, - NodeType.GRAPH_CONST : s_const, - NodeType.GRAPH_WIRE : s_wire - } - switch[node.nodeType]() - - ss += "];\n" - - pidx = 0 - for port in node.ports: - ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_) - ss += "[shape=none,label=<\n" - ss += " \n" - ss += " \n" - - bidx = 0; - for bit in port.bits: - - ss += " \n" - - bidx += 1 - - ss += "
" - ss += unescape_id(port.name.str()) - ss += "
" + str(bitmap[bit]) + ":" + str(bidx) + "
\n >];\n" - - if node.nodeType == NodeType.GRAPH_CELL: - if node.cell.output(port.name): - ss += " n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n" - else: - ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) + ";\n" - if node.nodeType == NodeType.GRAPH_PI or node.nodeType == NodeType.GRAPH_CONST: - ss += " n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n" - if node.nodeType == NodeType.GRAPH_PO: - ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) + ";\n" - - pidx += 1 - ss += " }\n" - nidx += 1 - - for i in range(len(self.incoming.nonzero()[0])): - b1 = self.node_bits[self.incoming.nonzero()[0][i]] - b2 = self.wire_bits[self.incoming.nonzero()[1][i]] - - if b1.node.nodeType == NodeType.GRAPH_PO or b1.node.nodeType == NodeType.GRAPH_CONST: - continue - - ss += " " - ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":" - ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos) - ss += " -> " - ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":" - ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos) - ss += ";\n" - - for i in range(len(self.outgoing.nonzero()[0])): - b1 = self.node_bits[self.outgoing.nonzero()[0][i]] - b2 = self.wire_bits[self.outgoing.nonzero()[1][i]] - - if b1.node.nodeType == NodeType.GRAPH_PI: - continue - - ss += " " - ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":" - ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos) - ss += " -> " - ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":" - ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos) - ss += ";\n" - - ss += "}\n" - - log_pop() - - return ss - - def save_dot(self, filename): - savetxt(filename, [self.dot()], fmt="%s") - - def save_incoming(self, filename, delimiter = ","): - savetxt(filename, self.incoming.todense(), "%d", delimiter=delimiter) - - def save_outgoing(self, filename, delimiter = ","): - savetxt(filename, self.outgoing.todense(), "%d", delimiter=delimiter) - - def save_adjacency(self, filename, delimiter = ","): - savetxt(filename, (self.outgoing*self.incoming.transpose()).todense(), "%d", delimiter=delimiter) - -p = None - -class NetlistGraphPass(Pass): - - def __init__(self): - super().__init__("netlist_graph", "Generates the Netlist-Graph of a module") - - import argparse - self.parser = argparse.ArgumentParser() - - self.parser.add_argument("-mod", nargs=1, metavar="MOD", help="The Netlist-Graph of the module with the id-string will be generated. If this argument is not given, the first module will be used") - self.parser.add_argument("-dot", nargs=1, metavar="FILE", help="Write the Netlist-Graph to FILE in dot format") - self.parser.add_argument("-i","-incoming", nargs=1, metavar="FILE", help="Write the incoming incidence matrix to FILE in csv format") - self.parser.add_argument("-o","-outgoing", nargs=1, metavar="FILE", help="Write the outgoing incidence matrix to FILE in csv format") - self.parser.add_argument("-a","-adjacency", nargs=1, metavar="FILE", help="Write the adjacency matrix to FILE in csv format") - - def py_help(self): - - log("This pass generates the Netlist-Graph of a module\n") - log(self.parser.format_help()) - - def py_execute(self, args, des): - - args = self.parser.parse_args(args[1:]) - - graph = None - if args.mod: - try: - graph = NetlistGraph(des, des.modules_[IdString(args.mod[0])]) - except KeyError: - log("Module \"" + args.mod[0] + "\" not found!\n") - exit() - else: - graph = NetlistGraph(des, list(des.modules_.values())[0]) - - if args.dot: - graph.save_dot(args.dot[0]) - - if args.i: - graph.save_incoming(args.i[0]) - - if args.o: - graph.save_outgoing(args.o[0]) - - if args.a: - graph.save_adjacency(args.a[0]) - - def py_clear_flags(self): - log("Clear\n") - -if __name__ == "__main__": - - designs = {} - graphs = {} - - testdir = "../../tests/simple/" - - import os - for testcase in os.listdir(testdir): - if not testcase.endswith(".v"): - continue - designs[testcase] = Design() - run_pass("read_verilog " + testdir + testcase, designs[testcase]) - run_pass("hierarchy -check -auto-top", designs[testcase]) - run_pass("proc", designs[testcase]) - run_pass("clean", designs[testcase]) - run_pass("memory", designs[testcase]) - run_pass("clean", designs[testcase]) - run_pass("opt -full", designs[testcase]) - run_pass("clean", designs[testcase]) - graphs[testcase] = NetlistGraph(designs[testcase]) - - file_prefix = "out/" + testcase - graphs[testcase].save_dot(file_prefix + ".dot") - graphs[testcase].save_incoming(file_prefix + "_in.csv") - graphs[testcase].save_outgoing(file_prefix + "_out.csv") - graphs[testcase].save_adjacency(file_prefix + "_adjacency.csv") - -else: - p = NetlistGraphPass() diff --git a/examples/python-api/pass.py b/examples/python-api/pass.py new file mode 100755 index 000000000..d67cf4a23 --- /dev/null +++ b/examples/python-api/pass.py @@ -0,0 +1,32 @@ +#!/usr/bin/python3 + +from pyosys import libyosys as ys + +import matplotlib.pyplot as plt +import numpy as np + +class CellStatsPass(ys.Pass): + + def __init__(self): + super().__init__("cell_stats", "Shows cell stats as plot") + + def py_help(self): + ys.log("This pass uses the matplotlib library to display cell stats\n") + + def py_execute(self, args, design): + ys.log_header(design, "Plotting cell stats\n") + cell_stats = {} + for module in design.selected_whole_modules_warn(): + for cell in module.selected_cells(): + if cell.type.str() in cell_stats: + cell_stats[cell.type.str()] += 1 + else: + cell_stats[cell.type.str()] = 1 + plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center') + plt.xticks(range(len(cell_stats)), list(cell_stats.keys())) + plt.show() + + def py_clear_flags(self): + ys.log("Clear Flags - CellStatsPass\n") + +p = CellStatsPass() diff --git a/examples/python-api/run.sh b/examples/python-api/run.sh deleted file mode 100755 index 5852ea9ac..000000000 --- a/examples/python-api/run.sh +++ /dev/null @@ -1,6 +0,0 @@ -PYTHONPATH=`pwd`/../../:$PYTHONPATH -mkdir -p out -if [ ! -f ../../libyosys.so ]; then - make -C ../.. -fi -python3.5 netlist_graph.py diff --git a/examples/python-api/script.py b/examples/python-api/script.py new file mode 100755 index 000000000..f0fa5a0b8 --- /dev/null +++ b/examples/python-api/script.py @@ -0,0 +1,22 @@ +#!/usr/bin/python3 + +from pyosys import libyosys as ys + +import matplotlib.pyplot as plt +import numpy as np + +design = ys.Design() +ys.run_pass("read_verilog ../../tests/simple/fiedler-cooley.v", design); +ys.run_pass("prep", design) +ys.run_pass("opt -full", design) + +cell_stats = {} +for module in design.selected_whole_modules_warn(): + for cell in module.selected_cells(): + if cell.type.str() in cell_stats: + cell_stats[cell.type.str()] += 1 + else: + cell_stats[cell.type.str()] = 1 +plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center') +plt.xticks(range(len(cell_stats)), list(cell_stats.keys())) +plt.show() From 0774a500d4a03104787e6514c69ff4995633a65f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 12:21:21 +0200 Subject: [PATCH 46/57] Added support for changing Yosys namespace --- kernel/yosys.h | 1 + py_wrap_generator.py | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/kernel/yosys.h b/kernel/yosys.h index a630798bb..2cf6188b4 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -119,6 +119,7 @@ extern const char *Tcl_GetStringResult(Tcl_Interp *interp); # define PATH_MAX 4096 #endif +#define YOSYS_NAMESPACE Yosys #define PRIVATE_NAMESPACE_BEGIN namespace { #define PRIVATE_NAMESPACE_END } #define YOSYS_NAMESPACE_BEGIN namespace Yosys { diff --git a/py_wrap_generator.py b/py_wrap_generator.py index aa2c46b2c..09f934040 100644 --- a/py_wrap_generator.py +++ b/py_wrap_generator.py @@ -972,7 +972,7 @@ sources = [ Source("kernel/cost",[]) ] -blacklist_methods = ["Yosys::Pass::run_register", "Yosys::Module::Pow", "Yosys::Module::Bu0", "Yosys::CaseRule::optimize"] +blacklist_methods = ["YOSYS_NAMESPACE::Pass::run_register", "YOSYS_NAMESPACE::Module::Pow", "YOSYS_NAMESPACE::Module::Bu0", "YOSYS_NAMESPACE::CaseRule::optimize"] enum_names = ["State","SyncType","ConstFlags"] @@ -1765,7 +1765,7 @@ def parse_header(source): private_segment = False while i < len(source_text): - line = source_text[i].replace("YOSYS_NAMESPACE_BEGIN", " namespace Yosys{").replace("YOSYS_NAMESPACE_END"," }") + line = source_text[i].replace("YOSYS_NAMESPACE_BEGIN", " namespace YOSYS_NAMESPACE{").replace("YOSYS_NAMESPACE_END"," }") ugly_line = unpretty_string(line) if str.startswith(ugly_line, "namespace "):# and ugly_line.find("std") == -1 and ugly_line.find("__") == -1: @@ -1892,7 +1892,7 @@ def parse_header(source): if candidate != None: while i < j: i += 1 - line = source_text[i].replace("YOSYS_NAMESPACE_BEGIN", " namespace Yosys{").replace("YOSYS_NAMESPACE_END"," }") + line = source_text[i].replace("YOSYS_NAMESPACE_BEGIN", " namespace YOSYS_NAMESPACE{").replace("YOSYS_NAMESPACE_END"," }") ugly_line = unpretty_string(line) if len(namespaces) != 0: namespaces[-1] = (namespaces[-1][0], namespaces[-1][1] + ugly_line.count("{") - ugly_line.count("}")) @@ -2028,7 +2028,7 @@ def gen_wrappers(filename, debug_level_ = 0): #include #include -using namespace Yosys; +USING_YOSYS_NAMESPACE namespace YOSYS_PYTHON { """) From bbfb43006d2a7d67d06ee151a1b8ad05ec5b1750 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 12:21:56 +0200 Subject: [PATCH 47/57] Improved Error reporting when Python passes are loaded --- passes/cmds/plugin.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 2b06690f9..bb1ec8716 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -61,12 +61,14 @@ void load_plugin(std::string filename, std::vector aliases) PyObject *filename_p = PyUnicode_FromString(filename.c_str()); if(filename_p == NULL) { + PyErr_Print(); log_cmd_error("Issues converting `%s' to Python\n", filename.c_str()); return; } PyObject *module_p = PyImport_Import(filename_p); if(module_p == NULL) { + PyErr_Print(); log_cmd_error("Can't load python module `%s'\n", filename.c_str()); return; } From fd7fb1377d4d30d692c78eb55173198339fea17d Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 13:21:40 +0200 Subject: [PATCH 48/57] Added cross-platform support for plugin-paths --- Makefile | 4 ++-- passes/cmds/plugin.cc | 16 ++++++++++------ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 6f7448843..618e4b603 100644 --- a/Makefile +++ b/Makefile @@ -270,9 +270,9 @@ endif ifeq ($(ENABLE_PYOSYS),1) ifeq ($(PYTHON_MAJOR_VERSION),3) - LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system + LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lstdc++fs else - LDLIBS += -lpython$(PYTHON_VERSION) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system + LDLIBS += -lpython$(PYTHON_VERSION) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lstdc++fs endif CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON PY_WRAPPER_FILE = kernel/python_wrappers diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index bb1ec8716..60dab38dd 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -26,6 +26,7 @@ #ifdef WITH_PYTHON # include # include +# include #endif YOSYS_NAMESPACE_BEGIN @@ -51,25 +52,28 @@ void load_plugin(std::string filename, std::vector aliases) #endif #ifdef WITH_PYTHON - if(boost::algorithm::ends_with(filename, ".py")) + + std::experimental::filesystem::path full_path(filename); + + if(strcmp(full_path.extension().c_str(), ".py") == 0) { - int last_slash = filename.find_last_of('/'); - std::string path = filename.substr(0, last_slash); - filename = filename.substr(last_slash+1, filename.size()); + std::string path(full_path.parent_path().c_str()); + filename = full_path.filename().c_str(); filename = filename.substr(0,filename.size()-3); PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); + PyErr_Print(); PyObject *filename_p = PyUnicode_FromString(filename.c_str()); if(filename_p == NULL) { PyErr_Print(); - log_cmd_error("Issues converting `%s' to Python\n", filename.c_str()); + log_cmd_error("Issues converting `%s' to Python\n", full_path.filename().c_str()); return; } PyObject *module_p = PyImport_Import(filename_p); if(module_p == NULL) { PyErr_Print(); - log_cmd_error("Can't load python module `%s'\n", filename.c_str()); + log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str()); return; } loaded_python_plugins[orig_filename] = module_p; From 827a96d3a38afe025c9efbd182069a9c9adee267 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 14:27:39 +0200 Subject: [PATCH 49/57] Global lists in rtlil.cc are now static objects --- kernel/rtlil.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index efe2c3559..bb870f66f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -387,10 +387,10 @@ RTLIL::Design::~Design() } #ifdef WITH_PYTHON -static std::map *all_designs = new std::map(); +static std::map all_designs; std::map *RTLIL::Design::get_all_designs(void) { - return all_designs; + return &all_designs; } #endif @@ -671,10 +671,10 @@ RTLIL::Module::~Module() } #ifdef WITH_PYTHON -static std::map *all_modules = new std::map(); +static std::map all_modules; std::map *RTLIL::Module::get_all_modules(void) { - return all_modules; + return &all_modules; } #endif @@ -2253,10 +2253,10 @@ RTLIL::Wire::~Wire() } #ifdef WITH_PYTHON -static std::map *all_wires = new std::map(); +static std::map all_wires; std::map *RTLIL::Wire::get_all_wires(void) { - return all_wires; + return &all_wires; } #endif @@ -2296,10 +2296,10 @@ RTLIL::Cell::~Cell() } #ifdef WITH_PYTHON -static std::map *all_cells = new std::map(); +static std::map all_cells; std::map *RTLIL::Cell::get_all_cells(void) { - return all_cells; + return &all_cells; } #endif @@ -3959,10 +3959,10 @@ RTLIL::Memory::~Memory() { RTLIL::Memory::get_all_memorys()->erase(hashidx_); } -static std::map *all_memorys = new std::map(); +static std::map all_memorys; std::map *RTLIL::Memory::get_all_memorys(void) { - return all_memorys; + return &all_memorys; } #endif YOSYS_NAMESPACE_END From c5a8dceff85c766c229d331c342e866dcef9af5f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 15:13:58 +0200 Subject: [PATCH 50/57] Preprocessing does not need all the flags --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 618e4b603..7f37fe6aa 100644 --- a/Makefile +++ b/Makefile @@ -532,7 +532,7 @@ libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) %.pyh: %.h $(Q) mkdir -p $(dir $@) - $(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(LD) -x c++ -o $@ -E -P $(CPPFLAGS) $(CXXFLAGS) -Qunused-arguments - + $(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(LD) -x c++ -o $@ -E -P -Qunused-arguments - $(PY_WRAPPER_FILE).cc: $(PY_GEN_SCRIPT).py $(PY_WRAP_INCLUDES) $(Q) mkdir -p $(dir $@) From d330f4e009874b24bc656a04ea1a650897f641ba Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 15:34:31 +0200 Subject: [PATCH 51/57] Even less options for the preprocessor --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 7f37fe6aa..06d020e68 100644 --- a/Makefile +++ b/Makefile @@ -532,7 +532,7 @@ libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) %.pyh: %.h $(Q) mkdir -p $(dir $@) - $(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(LD) -x c++ -o $@ -E -P -Qunused-arguments - + $(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(LD) -x c++ -o $@ -E -P - $(PY_WRAPPER_FILE).cc: $(PY_GEN_SCRIPT).py $(PY_WRAP_INCLUDES) $(Q) mkdir -p $(dir $@) From c3486c42709f0d1cfaca1fc24c86e0211f35996d Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 16:19:47 +0200 Subject: [PATCH 52/57] Removed compiler flags that are clang specific --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 06d020e68..119afc594 100644 --- a/Makefile +++ b/Makefile @@ -71,8 +71,8 @@ all: top-all YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST))) VPATH := $(YOSYS_SRC) -CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -D_YOSYS_ -fPIC -I$(PREFIX)/include -ferror-limit=0 -LDFLAGS := $(LDFLAGS) -L$(LIBDIR) -ferror-limit=0 +CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -D_YOSYS_ -fPIC -I$(PREFIX)/include +LDFLAGS := $(LDFLAGS) -L$(LIBDIR) LDLIBS := $(LDLIBS) -lstdc++ -lm PLUGIN_LDFLAGS := From e64b3f107411c150bbc773fc72b915bc60813c52 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 4 Apr 2019 09:24:50 +0200 Subject: [PATCH 53/57] Changed filesystem dependency to boost instead of experimental std library --- .travis.yml | 5 +++++ Makefile | 4 ++-- README.md | 2 +- passes/cmds/plugin.cc | 5 +++-- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/.travis.yml b/.travis.yml index c97294960..957735f1d 100644 --- a/.travis.yml +++ b/.travis.yml @@ -35,6 +35,7 @@ matrix: - python3 - libboost-system-dev - libboost-python-dev + - libboost-filesystem-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8" @@ -62,6 +63,7 @@ matrix: - python3 - libboost-system-dev - libboost-python-dev + - libboost-filesystem-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-6 && CXX=g++-6" @@ -89,6 +91,7 @@ matrix: - python3 - libboost-system-dev - libboost-python-dev + - libboost-filesystem-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7" @@ -117,6 +120,7 @@ matrix: - python3 - libboost-system-dev - libboost-python-dev + - libboost-filesystem-dev env: - MATRIX_EVAL="CONFIG=clang && CC=clang-3.8 && CXX=clang++-3.8" @@ -144,6 +148,7 @@ matrix: - python3 - libboost-system-dev - libboost-python-dev + - libboost-filesystem-dev env: - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0" diff --git a/Makefile b/Makefile index 119afc594..2038801e6 100644 --- a/Makefile +++ b/Makefile @@ -270,9 +270,9 @@ endif ifeq ($(ENABLE_PYOSYS),1) ifeq ($(PYTHON_MAJOR_VERSION),3) - LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lstdc++fs + LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lboost_filesystem -lstdc++fs else - LDLIBS += -lpython$(PYTHON_VERSION) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lstdc++fs + LDLIBS += -lpython$(PYTHON_VERSION) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lboost_filesystem -lstdc++fs endif CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON PY_WRAPPER_FILE = kernel/python_wrappers diff --git a/README.md b/README.md index 87c2adcce..45577ade2 100644 --- a/README.md +++ b/README.md @@ -67,7 +67,7 @@ prerequisites for building yosys: $ sudo apt-get install build-essential clang bison flex \ libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 libboost-system-dev \ - libboost-python-dev + libboost-python-dev libboost-filesystem-dev Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies: diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 60dab38dd..5da8f5b0b 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -26,7 +26,7 @@ #ifdef WITH_PYTHON # include # include -# include +# include #endif YOSYS_NAMESPACE_BEGIN @@ -53,7 +53,7 @@ void load_plugin(std::string filename, std::vector aliases) #ifdef WITH_PYTHON - std::experimental::filesystem::path full_path(filename); + boost::filesystem::path full_path(filename); if(strcmp(full_path.extension().c_str(), ".py") == 0) { @@ -63,6 +63,7 @@ void load_plugin(std::string filename, std::vector aliases) PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); PyErr_Print(); PyObject *filename_p = PyUnicode_FromString(filename.c_str()); + if(filename_p == NULL) { PyErr_Print(); From 574dfb2ef9b31ff1396e48cb37b5f59996c5db24 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 4 Apr 2019 09:51:14 +0200 Subject: [PATCH 54/57] Removed link to experimental filesystem library --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 2038801e6..9f81c3417 100644 --- a/Makefile +++ b/Makefile @@ -270,9 +270,9 @@ endif ifeq ($(ENABLE_PYOSYS),1) ifeq ($(PYTHON_MAJOR_VERSION),3) - LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lboost_filesystem -lstdc++fs + LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lboost_filesystem else - LDLIBS += -lpython$(PYTHON_VERSION) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lboost_filesystem -lstdc++fs + LDLIBS += -lpython$(PYTHON_VERSION) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lboost_filesystem endif CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON PY_WRAPPER_FILE = kernel/python_wrappers From cae657cebd1f4aa119a1264f80d89294a23be845 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 4 Apr 2019 10:35:01 +0200 Subject: [PATCH 55/57] Used PyImport_ImportModule instead of PyImport_Import to avoid the explicit conversion to a python string --- passes/cmds/plugin.cc | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 5da8f5b0b..4c16b56c4 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -60,17 +60,9 @@ void load_plugin(std::string filename, std::vector aliases) std::string path(full_path.parent_path().c_str()); filename = full_path.filename().c_str(); filename = filename.substr(0,filename.size()-3); - PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); + PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); PyErr_Print(); - PyObject *filename_p = PyUnicode_FromString(filename.c_str()); - - if(filename_p == NULL) - { - PyErr_Print(); - log_cmd_error("Issues converting `%s' to Python\n", full_path.filename().c_str()); - return; - } - PyObject *module_p = PyImport_Import(filename_p); + PyObject *module_p = PyImport_ImportModule(filename.c_str()); if(module_p == NULL) { PyErr_Print(); From cc270ea81bc7209e9e1673e6c3dbd5db6d3ceee8 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Fri, 5 Apr 2019 11:56:01 +0200 Subject: [PATCH 56/57] Autodetect Python paths and boost python libraries for different distributions --- Makefile | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 9f81c3417..c6c56b604 100644 --- a/Makefile +++ b/Makefile @@ -22,9 +22,10 @@ ENABLE_PROTOBUF := 0 # python wrappers ENABLE_PYOSYS := 1 PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)" -PYTHON_VERSION := $(shell if python3 -c ""; then python3 -c ""$(PYTHON_VERSION_TESTCODE)""; else python -c ""$(PYTHON_VERSION_TESTCODE)""; fi) +PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi) +PYTHON_VERSION := $(shell $(PYTHON_EXECUTABLE) -c ""$(PYTHON_VERSION_TESTCODE)"") PYTHON_MAJOR_VERSION := $(shell echo $(PYTHON_VERSION) | cut -f1 -d.) -PYTHON_DESTDIR := /usr/local/lib/python$(PYTHON_VERSION)/dist-packages +PYTHON_DESTDIR := `$(PYTHON_EXECUTABLE)-config --prefix`/lib/python$(PYTHON_VERSION)/dist-packages # other configuration flags ENABLE_GCOV := 0 @@ -269,12 +270,27 @@ TARGETS += libyosys.so endif ifeq ($(ENABLE_PYOSYS),1) - ifeq ($(PYTHON_MAJOR_VERSION),3) - LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lboost_filesystem - else - LDLIBS += -lpython$(PYTHON_VERSION) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system -lboost_filesystem - endif -CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON + +#Detect name of boost_python library. Some distros usbe boost_python-py, other boost_python, some only use the major version number, some a concatenation of major and minor version numbers +BOOST_PYTHON_LIB ?= $(shell \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -; then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) -; then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_VERSION)) -; then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) -; then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ + echo ""; fi; fi; fi; fi;) + +ifeq ($(BOOST_PYTHON_LIB),) +$(error BOOST_PYTHON_LIB could not be detected. Please define manualy) +endif + +ifeq ($(PYTHON_MAJOR_VERSION),3) +LDLIBS += `$(PYTHON_EXECUTABLE)-config --libs` $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem +CXXFLAGS += `$(PYTHON_EXECUTABLE)-config --includes` -D WITH_PYTHON +else +LDLIBS += `$(PYTHON_EXECUTABLE)-config --libs` $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem +CXXFLAGS += `$(PYTHON_EXECUTABLE)-config --includes` -D WITH_PYTHON +endif + PY_WRAPPER_FILE = kernel/python_wrappers OBJS += $(PY_WRAPPER_FILE).o PY_GEN_SCRIPT= py_wrap_generator From e19981ab6111765baa5b2ab7a16c92278130fd8b Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Sun, 7 Apr 2019 10:11:35 +0200 Subject: [PATCH 57/57] Suppress error from the compiler run during libboost-python* detection --- Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index c6c56b604..993cbb7e5 100644 --- a/Makefile +++ b/Makefile @@ -273,10 +273,10 @@ ifeq ($(ENABLE_PYOSYS),1) #Detect name of boost_python library. Some distros usbe boost_python-py, other boost_python, some only use the major version number, some a concatenation of major and minor version numbers BOOST_PYTHON_LIB ?= $(shell \ - if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -; then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))"; else \ - if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) -; then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ - if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_VERSION)) -; then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))"; else \ - if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) -; then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ echo ""; fi; fi; fi; fi;) ifeq ($(BOOST_PYTHON_LIB),)