riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed ice40 handling of negclk RAM40

This commit is contained in:
Clifford Wolf 2015-09-10 17:35:19 +02:00
parent 6f9a6fd783
commit 99ccb3180d
2 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
techlibs/ice40/brams_map.v
View File

@ -90,7 +90,7 @@ module \$__ICE40_RAM4K (
.RCLKE(RCLKE), .RCLKE(RCLKE),
.RE (RE ), .RE (RE ),
.RADDR(RADDR), .RADDR(RADDR),
.WCLK (WCLK ), .WCLKN(WCLK ),
.WCLKE(WCLKE), .WCLKE(WCLKE),
.WE (WE ), .WE (WE ),
.WADDR(WADDR), .WADDR(WADDR),
@ -119,7 +119,7 @@ module \$__ICE40_RAM4K (
.INIT_F(INIT_F) .INIT_F(INIT_F)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.RDATA(RDATA), .RDATA(RDATA),
.RCLK (RCLK ), .RCLKN(RCLK ),
.RCLKE(RCLKE), .RCLKE(RCLKE),
.RE (RE ), .RE (RE ),
.RADDR(RADDR), .RADDR(RADDR),
@ -152,11 +152,11 @@ module \$__ICE40_RAM4K (
.INIT_F(INIT_F) .INIT_F(INIT_F)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.RDATA(RDATA), .RDATA(RDATA),
.RCLK (RCLK ), .RCLKN(RCLK ),
.RCLKE(RCLKE), .RCLKE(RCLKE),
.RE (RE ), .RE (RE ),
.RADDR(RADDR), .RADDR(RADDR),
.WCLK (WCLK ), .WCLKN(WCLK ),
.WCLKE(WCLKE), .WCLKE(WCLKE),
.WE (WE ), .WE (WE ),
.WADDR(WADDR), .WADDR(WADDR),

16
techlibs/ice40/cells_sim.v
View File

@ -473,7 +473,7 @@ endmodule
module SB_RAM40_4KNR ( module SB_RAM40_4KNR (
output [15:0] RDATA, output [15:0] RDATA,
input RCLK, RCLKE, RE, input RCLKN, RCLKE, RE,
input [10:0] RADDR, input [10:0] RADDR,
input WCLK, WCLKE, WE, input WCLK, WCLKE, WE,
input [10:0] WADDR, input [10:0] WADDR,
@ -520,7 +520,7 @@ module SB_RAM40_4KNR (
.INIT_F (INIT_F ) .INIT_F (INIT_F )
) RAM ( ) RAM (
.RDATA(RDATA), .RDATA(RDATA),
.RCLK (~RCLK), .RCLK (~RCLKN),
.RCLKE(RCLKE), .RCLKE(RCLKE),
.RE (RE ), .RE (RE ),
.RADDR(RADDR), .RADDR(RADDR),
@ -537,7 +537,7 @@ module SB_RAM40_4KNW (
output [15:0] RDATA, output [15:0] RDATA,
input RCLK, RCLKE, RE, input RCLK, RCLKE, RE,
input [10:0] RADDR, input [10:0] RADDR,
input WCLK, WCLKE, WE, input WCLKN, WCLKE, WE,
input [10:0] WADDR, input [10:0] WADDR,
input [15:0] MASK, WDATA input [15:0] MASK, WDATA
); );
@ -586,7 +586,7 @@ module SB_RAM40_4KNW (
.RCLKE(RCLKE), .RCLKE(RCLKE),
.RE (RE ), .RE (RE ),
.RADDR(RADDR), .RADDR(RADDR),
.WCLK (~WCLK), .WCLK (~WCLKN),
.WCLKE(WCLKE), .WCLKE(WCLKE),
.WE (WE ), .WE (WE ),
.WADDR(WADDR), .WADDR(WADDR),
@ -597,9 +597,9 @@ endmodule
module SB_RAM40_4KNRNW ( module SB_RAM40_4KNRNW (
output [15:0] RDATA, output [15:0] RDATA,
input RCLK, RCLKE, RE, input RCLKN, RCLKE, RE,
input [10:0] RADDR, input [10:0] RADDR,
input WCLK, WCLKE, WE, input WCLKN, WCLKE, WE,
input [10:0] WADDR, input [10:0] WADDR,
input [15:0] MASK, WDATA input [15:0] MASK, WDATA
); );
@ -644,11 +644,11 @@ module SB_RAM40_4KNRNW (
.INIT_F (INIT_F ) .INIT_F (INIT_F )
) RAM ( ) RAM (
.RDATA(RDATA), .RDATA(RDATA),
.RCLK (~RCLK), .RCLK (~RCLKN),
.RCLKE(RCLKE), .RCLKE(RCLKE),
.RE (RE ), .RE (RE ),
.RADDR(RADDR), .RADDR(RADDR),
.WCLK (~WCLK), .WCLK (~WCLKN),
.WCLKE(WCLKE), .WCLKE(WCLKE),
.WE (WE ), .WE (WE ),
.WADDR(WADDR), .WADDR(WADDR),