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Merge pull request #2023 from YosysHQ/eddie/specify_src 

verilog: fix specify src attribute
This commit is contained in:
Eddie Hung 2020-05-05 06:49:06 -07:00 committed by GitHub
parent 584780d776 eb5eb60fd4
commit 99aff5a0f9
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 26 additions and 18 deletions
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2
frontends/verilog/verilog_parser.y
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@ -885,6 +885,7 @@ specify_item:
cell->str = stringf("$specify$%d", autoidx++);
cell->children.push_back(new AstNode(AST_CELLTYPE));
cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
char oper_polarity = 0;
char oper_type = oper->at(0);
@ -973,6 +974,7 @@ specify_item:
cell->str = stringf("$specify$%d", autoidx++);
cell->children.push_back(new AstNode(AST_CELLTYPE));
cell->children.back()->str = "$specrule";
SET_AST_NODE_LOC(cell, @1, @14);
cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
cell->children.back()->str = "\\TYPE";

6
tests/various/specify.ys
View File

@ -4,10 +4,16 @@ cd test
select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1
select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1
select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1
cd test2
select t:$specify2 -assert-count 2
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1
# ^^ Note use of macro
select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1
cd
write_verilog specify.out
design -stash gold