mirror of https://github.com/YosysHQ/yosys.git
Remove ununsed files
This commit is contained in:
parent
22f440506b
commit
99a0958601
|
@ -1,19 +0,0 @@
|
||||||
module multiple_blocking #(parameter WIDTH=256, SELW=2)
|
|
||||||
(input clk ,
|
|
||||||
input [9:0] ctrl ,
|
|
||||||
input [15:0] din ,
|
|
||||||
input [SELW-1:0] sel ,
|
|
||||||
output reg [WIDTH:0] dout);
|
|
||||||
|
|
||||||
localparam SLICE = WIDTH/(SELW**2);
|
|
||||||
reg [9:0] a;
|
|
||||||
reg [SELW-1:0] b;
|
|
||||||
reg [15:0] c;
|
|
||||||
always @(posedge clk) begin
|
|
||||||
a = ctrl + 1;
|
|
||||||
b = sel - 1;
|
|
||||||
c = ~din;
|
|
||||||
dout = dout + 1;
|
|
||||||
dout[a*b+:SLICE] = c;
|
|
||||||
end
|
|
||||||
endmodule
|
|
|
@ -1,14 +0,0 @@
|
||||||
module nonblocking #(parameter WIDTH=256, SELW=2)
|
|
||||||
(input clk ,
|
|
||||||
input [9:0] ctrl ,
|
|
||||||
input [15:0] din ,
|
|
||||||
input [SELW-1:0] sel ,
|
|
||||||
output reg [WIDTH-1:0] dout);
|
|
||||||
|
|
||||||
localparam SLICE = WIDTH/(SELW**2);
|
|
||||||
always @(posedge clk) begin
|
|
||||||
dout <= dout + 1;
|
|
||||||
dout[ctrl*sel+:SLICE] <= din ;
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
|
@ -1,13 +0,0 @@
|
||||||
module original #(parameter WIDTH=256, SELW=2)
|
|
||||||
(input clk ,
|
|
||||||
input [9:0] ctrl ,
|
|
||||||
input [15:0] din ,
|
|
||||||
input [SELW-1:0] sel ,
|
|
||||||
output reg [WIDTH-1:0] dout);
|
|
||||||
|
|
||||||
localparam SLICE = WIDTH/(SELW**2);
|
|
||||||
always @(posedge clk)
|
|
||||||
begin
|
|
||||||
dout[ctrl*sel+:SLICE] <= din ;
|
|
||||||
end
|
|
||||||
endmodule
|
|
|
@ -1,24 +0,0 @@
|
||||||
module reset_test #(parameter WIDTH=256, SELW=2)
|
|
||||||
(input clk ,
|
|
||||||
input [9:0] ctrl ,
|
|
||||||
input [15:0] din ,
|
|
||||||
input [SELW-1:0] sel ,
|
|
||||||
input wire reset,
|
|
||||||
output reg [WIDTH-1:0] dout);
|
|
||||||
|
|
||||||
reg [5:0] i;
|
|
||||||
wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}};
|
|
||||||
localparam SLICE = WIDTH/(SELW**2);
|
|
||||||
// Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for
|
|
||||||
// whatever reason.
|
|
||||||
always @(posedge clk) begin
|
|
||||||
if (reset) begin: reset_mask
|
|
||||||
for (i = 0; i < 16; i=i+1) begin
|
|
||||||
dout[i*rval+:SLICE] <= 32'hDEAD;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
//else begin
|
|
||||||
dout[ctrl*sel+:SLICE] <= din;
|
|
||||||
//end
|
|
||||||
end
|
|
||||||
endmodule
|
|
|
@ -1,13 +0,0 @@
|
||||||
module reversed #(parameter WIDTH=256, SELW=2)
|
|
||||||
(input clk ,
|
|
||||||
input [9:0] ctrl ,
|
|
||||||
input [15:0] din ,
|
|
||||||
input [SELW-1:0] sel ,
|
|
||||||
output reg [WIDTH-1:0] dout);
|
|
||||||
|
|
||||||
localparam SLICE = WIDTH/(SELW**2);
|
|
||||||
always @(posedge clk) begin
|
|
||||||
dout[(WIDTH-ctrl*sel)-:SLICE] <= din;
|
|
||||||
end
|
|
||||||
endmodule
|
|
||||||
|
|
Loading…
Reference in New Issue