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genrtlil: fix mux2rtlil generated wire signedness

This commit is contained in:
Zachary Snow 2020-12-22 17:38:51 -07:00
parent d15c63effc
commit 999eec5617
2 changed files with 10 additions and 4 deletions
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1
frontends/ast/genrtlil.cc
View File

@ -141,6 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);
wire->is_signed = that->is_signed;
for (auto &attr : that->attributes) { for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)

13
tests/various/port_sign_extend.v
View File

@ -24,8 +24,8 @@ module PassThrough(a, b);
assign b = a; assign b = a;
endmodule endmodule
module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2); module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
output wire [3:0] o1, o2, o3, o4, o5; output wire [3:0] o1, o2, o3, o4, o5, o6;
// unsigned constant // unsigned constant
PassThrough pt1(1'b1, o1); PassThrough pt1(1'b1, o1);
@ -48,6 +48,10 @@ module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);
wire signed [1:0] tmp5b = 2'b01; wire signed [1:0] tmp5b = 2'b01;
PassThrough pt5(tmp5a ^ tmp5b, o5); PassThrough pt5(tmp5a ^ tmp5b, o5);
wire signed [2:0] tmp6a = 3'b100;
wire signed [2:0] tmp6b = 3'b001;
PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6);
output wire [2:0] yay1, nay1; output wire [2:0] yay1, nay1;
GeneratorSigned1 os1(yay1); GeneratorSigned1 os1(yay1);
GeneratorUnsigned1 ou1(nay1); GeneratorUnsigned1 ou1(nay1);
@ -57,14 +61,15 @@ module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);
GeneratorUnsigned2 ou2(nay2); GeneratorUnsigned2 ou2(nay2);
endmodule endmodule
module ref(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2); module ref(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
output wire [3:0] o1, o2, o3, o4, o5; output wire [3:0] o1, o2, o3, o4, o5, o6;
assign o1 = 4'b0001; assign o1 = 4'b0001;
assign o2 = 4'b0001; assign o2 = 4'b0001;
assign o3 = 4'b1111; assign o3 = 4'b1111;
assign o4 = 4'b1111; assign o4 = 4'b1111;
assign o5 = 4'b1110; assign o5 = 4'b1110;
assign o6 = 4'b1100;
output wire [2:0] yay1, nay1; output wire [2:0] yay1, nay1;
assign yay1 = 3'b111; assign yay1 = 3'b111;