From 992a728ec7ad5b7a19d58e544fd0901065bb2f71 Mon Sep 17 00:00:00 2001
From: Charlotte <charlotte@hrzn.ee>
Date: Wed, 28 Jun 2023 11:51:28 +1000
Subject: [PATCH] tests: CXX may be e.g. gcc, so use CC and link stdc++
 explicitly

---
 frontends/ast/genrtlil.cc | 4 ++--
 tests/fmt/run-test.sh     | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 2e2d0de74..849b5ebad 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -700,7 +700,7 @@ struct AST_INTERNAL::ProcessGenerator
 				sstr << ast->str << "$" << ast->filename << ":" << ast->location.first_line << "$" << (autoidx++);
 
 				RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print));
-				cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
+				set_src_attr(cell, ast);
 
 				RTLIL::SigSpec triggers;
 				RTLIL::Const polarity;
@@ -719,7 +719,7 @@ struct AST_INTERNAL::ProcessGenerator
 				cell->setPort(ID::TRG, triggers);
 
 				Wire *wire = current_module->addWire(sstr.str() + "_EN", 1);
-				wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
+				set_src_attr(wire, ast);
 				cell->setPort(ID::EN, wire);
 
 				proc->root_case.actions.push_back(SigSig(wire, false));
diff --git a/tests/fmt/run-test.sh b/tests/fmt/run-test.sh
index a5a0c0c7e..0e073a707 100644
--- a/tests/fmt/run-test.sh
+++ b/tests/fmt/run-test.sh
@@ -48,7 +48,7 @@ test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=""
 test_roundtrip bin_signed -DBASE_HEX -DSIGN="signed"
 
 ../../yosys -p "read_verilog always_full.v; write_cxxrtl -print-output std::cerr yosys-always_full.cc"
-${CXX:-g++} -o yosys-always_full -I../.. always_full_tb.cc
+${CC:-gcc} -o yosys-always_full -I../.. always_full_tb.cc -lstdc++
 ./yosys-always_full 2>yosys-always_full.log
 iverilog -o iverilog-always_full always_full.v always_full_tb.v
 ./iverilog-always_full | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >iverilog-always_full.log
@@ -56,7 +56,7 @@ diff iverilog-always_full.log yosys-always_full.log
 
 ../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log
 ../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc"
-${CXX:-g++} -o yosys-display_lm_cc -I../.. display_lm_tb.cc
+${CC:-gcc} -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++
 ./yosys-display_lm_cc >yosys-display_lm_cc.log
 for log in yosys-display_lm.log yosys-display_lm_cc.log; do
 	grep "^%l: \\\\bot\$" "$log"