riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger

This commit is contained in:
Eddie Hung 2019-12-06 17:05:02 -08:00
parent 7dece7955e
commit 98c9ea605b
3 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
techlibs/ecp5/synth_ecp5.cc
View File

@ -312,6 +312,11 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap " + techmap_args); run("techmap " + techmap_args);
if (abc9) { if (abc9) {
run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
run("wbflip @abc9_boxes");
run("techmap -autoproc @abc9_boxes");
run("aigmap @abc9_boxes");
run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/ecp5/abc9_model.v"); run("read_verilog -icells -lib +/ecp5/abc9_model.v");
if (nowidelut) if (nowidelut)
run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");

5
techlibs/ice40/synth_ice40.cc
View File

@ -350,6 +350,11 @@ struct SynthIce40Pass : public ScriptPass
} }
if (!noabc) { if (!noabc) {
if (abc == "abc9") { if (abc == "abc9") {
run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
run("wbflip @abc9_boxes");
run("techmap -autoproc @abc9_boxes");
run("aigmap @abc9_boxes");
run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/ice40/abc9_model.v"); run("read_verilog -icells -lib +/ice40/abc9_model.v");
int wire_delay; int wire_delay;
if (device_opt == "lp") if (device_opt == "lp")

5
techlibs/xilinx/synth_xilinx.cc
View File

@ -533,6 +533,11 @@ struct SynthXilinxPass : public ScriptPass
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str()); "will use timing for 'xc7' instead.\n", family.c_str());
run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
run("wbflip @abc9_boxes");
run("techmap -autoproc @abc9_boxes");
run("aigmap @abc9_boxes");
run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/xilinx/abc9_model.v"); run("read_verilog -icells -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);