tests: read +/xilinx/cell_sim.v before xilinx_dsp test

2020-04-22 17:50:30 -07:00 · 2020-04-22 17:50:30 -07:00 · 988d47af85
parent 592baebd22
commit 988d47af85
1 changed files with 1 additions and 0 deletions
--- a/tests/arch/xilinx/xilinx_dsp.ys
+++ b/tests/arch/xilinx/xilinx_dsp.ys
@ -8,4 +8,5 @@ assign o4 = a * b;
 DSP48E1 m3 (.A(a), .B(b), .P(o5));
 endmodule
 EOT
+read_verilog -lib +/xilinx/cells_sim.v
 xilinx_dsp