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tests: read +/xilinx/cell_sim.v before xilinx_dsp test

This commit is contained in:
Eddie Hung 2020-04-22 17:50:30 -07:00
parent 592baebd22
commit 988d47af85
1 changed files with 1 additions and 0 deletions
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tests/arch/xilinx/xilinx_dsp.ys
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@ -8,4 +8,5 @@ assign o4 = a * b;
DSP48E1 m3 (.A(a), .B(b), .P(o5)); DSP48E1 m3 (.A(a), .B(b), .P(o5));
endmodule endmodule
EOT EOT
read_verilog -lib +/xilinx/cells_sim.v
xilinx_dsp xilinx_dsp