diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc
index 51eb28d44..43d8fdf79 100644
--- a/techlibs/quicklogic/Makefile.inc
+++ b/techlibs/quicklogic/Makefile.inc
@@ -1,13 +1,12 @@
 OBJS += techlibs/quicklogic/synth_quicklogic.o
 
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v))
+$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v))
 
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v))
diff --git a/techlibs/quicklogic/cells_sim.v b/techlibs/quicklogic/common/cells_sim.v
similarity index 100%
rename from techlibs/quicklogic/cells_sim.v
rename to techlibs/quicklogic/common/cells_sim.v
diff --git a/techlibs/quicklogic/lut_sim.v b/techlibs/quicklogic/lut_sim.v
deleted file mode 100644
index 851ce4d68..000000000
--- a/techlibs/quicklogic/lut_sim.v
+++ /dev/null
@@ -1,76 +0,0 @@
-(* abc9_lut=1, lib_whitebox *)
-module LUT1 (
-  output O,
-  input I0
-);
-  parameter [1:0] INIT = 0;
-  parameter EQN = "(I0)";
-
-  // These timings are for PolarPro 3E; other families will need updating.
-  specify
-    (I0 => O) = 698; // FS -> FZ
-  endspecify
-
-  assign O = I0 ? INIT[1] : INIT[0];
-endmodule
-
-//               TZ        TSL TAB
-(* abc9_lut=2, lib_whitebox *)
-module LUT2 (
-  output O,
-  input I0, I1
-);
-  parameter [3:0] INIT = 4'h0;
-  parameter EQN = "(I0)";
-
-  // These timings are for PolarPro 3E; other families will need updating.
-  specify
-    (I0 => O) = 1251; // TAB -> TZ
-    (I1 => O) = 1406; // TSL -> TZ
-  endspecify
-
-  wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
-  assign O = I0 ? s1[1] : s1[0];
-endmodule
-
-(* abc9_lut=2, lib_whitebox *)
-module LUT3 (
-  output O,
-  input I0, I1, I2
-);
-  parameter [7:0] INIT = 8'h0;
-  parameter EQN = "(I0)";
-
-  // These timings are for PolarPro 3E; other families will need updating.
-  specify
-    (I0 => O) = 1251; // TAB -> TZ
-    (I1 => O) = 1406; // TSL -> TZ
-    (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
-  endspecify
-
-  wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
-  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
-  assign O = I0 ? s1[1] : s1[0];
-endmodule
-
-(* abc9_lut=4, lib_whitebox *)
-module LUT4 (
-  output O,
-  input I0, I1, I2, I3
-);
-  parameter [15:0] INIT = 16'h0;
-  parameter EQN = "(I0)";
-
-  // These timings are for PolarPro 3E; other families will need updating.
-  specify
-    (I0 => O) = 995;  // TBS -> CZ
-    (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
-    (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
-    (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
-  endspecify
-
-  wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
-  wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
-  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
-  assign O = I0 ? s1[1] : s1[0];
-endmodule
diff --git a/techlibs/quicklogic/abc9_map.v b/techlibs/quicklogic/pp3/abc9_map.v
similarity index 100%
rename from techlibs/quicklogic/abc9_map.v
rename to techlibs/quicklogic/pp3/abc9_map.v
diff --git a/techlibs/quicklogic/abc9_model.v b/techlibs/quicklogic/pp3/abc9_model.v
similarity index 100%
rename from techlibs/quicklogic/abc9_model.v
rename to techlibs/quicklogic/pp3/abc9_model.v
diff --git a/techlibs/quicklogic/abc9_unmap.v b/techlibs/quicklogic/pp3/abc9_unmap.v
similarity index 100%
rename from techlibs/quicklogic/abc9_unmap.v
rename to techlibs/quicklogic/pp3/abc9_unmap.v
diff --git a/techlibs/quicklogic/pp3_cells_map.v b/techlibs/quicklogic/pp3/cells_map.v
similarity index 100%
rename from techlibs/quicklogic/pp3_cells_map.v
rename to techlibs/quicklogic/pp3/cells_map.v
diff --git a/techlibs/quicklogic/pp3_cells_sim.v b/techlibs/quicklogic/pp3/cells_sim.v
similarity index 76%
rename from techlibs/quicklogic/pp3_cells_sim.v
rename to techlibs/quicklogic/pp3/cells_sim.v
index 5820d7a9e..201a7d333 100644
--- a/techlibs/quicklogic/pp3_cells_sim.v
+++ b/techlibs/quicklogic/pp3/cells_sim.v
@@ -327,3 +327,80 @@ module qlal4s3b_cell_macro (
 );
 
 endmodule
+
+(* abc9_lut=1, lib_whitebox *)
+module LUT1 (
+  output O,
+  input I0
+);
+  parameter [1:0] INIT = 0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 698; // FS -> FZ
+  endspecify
+
+  assign O = I0 ? INIT[1] : INIT[0];
+endmodule
+
+//               TZ        TSL TAB
+(* abc9_lut=2, lib_whitebox *)
+module LUT2 (
+  output O,
+  input I0, I1
+);
+  parameter [3:0] INIT = 4'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 1251; // TAB -> TZ
+    (I1 => O) = 1406; // TSL -> TZ
+  endspecify
+
+  wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+(* abc9_lut=2, lib_whitebox *)
+module LUT3 (
+  output O,
+  input I0, I1, I2
+);
+  parameter [7:0] INIT = 8'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 1251; // TAB -> TZ
+    (I1 => O) = 1406; // TSL -> TZ
+    (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
+  endspecify
+
+  wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
+  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+(* abc9_lut=4, lib_whitebox *)
+module LUT4 (
+  output O,
+  input I0, I1, I2, I3
+);
+  parameter [15:0] INIT = 16'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 995;  // TBS -> CZ
+    (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
+    (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
+    (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
+  endspecify
+
+  wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
+  wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
+  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
diff --git a/techlibs/quicklogic/pp3_ffs_map.v b/techlibs/quicklogic/pp3/ffs_map.v
similarity index 100%
rename from techlibs/quicklogic/pp3_ffs_map.v
rename to techlibs/quicklogic/pp3/ffs_map.v
diff --git a/techlibs/quicklogic/pp3_latches_map.v b/techlibs/quicklogic/pp3/latches_map.v
similarity index 100%
rename from techlibs/quicklogic/pp3_latches_map.v
rename to techlibs/quicklogic/pp3/latches_map.v
diff --git a/techlibs/quicklogic/pp3_lut_map.v b/techlibs/quicklogic/pp3/lut_map.v
similarity index 100%
rename from techlibs/quicklogic/pp3_lut_map.v
rename to techlibs/quicklogic/pp3/lut_map.v
diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc
index 94bd44db0..7fddbc970 100644
--- a/techlibs/quicklogic/synth_quicklogic.cc
+++ b/techlibs/quicklogic/synth_quicklogic.cc
@@ -60,13 +60,14 @@ struct SynthQuickLogicPass : public ScriptPass {
 		log("\n");
 	}
 
-	string top_opt, blif_file, family, currmodule, verilog_file;
+	string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path;
 	bool abc9;
 
 	void clear_flags() override
 	{
 		top_opt = "-auto-top";
 		blif_file = "";
+		edif_file = "";
 		verilog_file = "";
 		currmodule = "";
 		family = "pp3";
@@ -81,6 +82,14 @@ struct SynthQuickLogicPass : public ScriptPass {
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
 			if (args[argidx] == "-top" && argidx+1 < args.size()) {
 				top_opt = "-top " + args[++argidx];
 				continue;
@@ -93,6 +102,10 @@ struct SynthQuickLogicPass : public ScriptPass {
 				blif_file = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-edif" && argidx + 1 < args.size()) {
+				edif_file = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-verilog" && argidx+1 < args.size()) {
 				verilog_file = args[++argidx];
 				continue;
@@ -126,13 +139,16 @@ struct SynthQuickLogicPass : public ScriptPass {
 
 	void script() override
 	{
+		if (help_mode) {
+			family = "<family>";
+		}
+
 		if (check_label("begin")) {
-			run(stringf("read_verilog -lib -specify +/quicklogic/cells_sim.v +/quicklogic/%s_cells_sim.v", family.c_str()));
-			run("read_verilog -lib -specify +/quicklogic/lut_sim.v");
+			run(stringf("read_verilog -lib -specify +/quicklogic/common/cells_sim.v +/quicklogic/%s/cells_sim.v", family.c_str()));
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-		if (check_label("coarse")) {
+		if (check_label("prepare")) {
 			run("proc");
 			run("flatten");
 			run("tribuf -logic");
@@ -147,6 +163,9 @@ struct SynthQuickLogicPass : public ScriptPass {
 			run("peepopt");
 			run("opt_clean");
 			run("share");
+		}
+
+		if (check_label("coarse")) {
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 			run("opt_expr");
 			run("opt_clean");
@@ -175,18 +194,18 @@ struct SynthQuickLogicPass : public ScriptPass {
 			run("opt_expr");
 			run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
 
-			run(stringf("techmap -map +/quicklogic/%s_cells_map.v -map +/quicklogic/%s_ffs_map.v", family.c_str(), family.c_str()));
+			run(stringf("techmap -map +/quicklogic/%s/cells_map.v -map +/quicklogic/%s/ffs_map.v", family.c_str(), family.c_str()));
 
 			run("opt_expr -mux_undef");
 		}
 
 		if (check_label("map_luts")) {
-			run(stringf("techmap -map +/quicklogic/%s_latches_map.v", family.c_str()));
+			run(stringf("techmap -map +/quicklogic/%s/latches_map.v", family.c_str()));
 			if (abc9) {
-				run("read_verilog -lib -specify -icells +/quicklogic/abc9_model.v");
-				run("techmap -map +/quicklogic/abc9_map.v");
+				run(stringf("read_verilog -lib -specify -icells +/quicklogic/%s/abc9_model.v", family.c_str()));
+				run(stringf("techmap -map +/quicklogic/%s/abc9_map.v", family.c_str()));
 				run("abc9 -maxlut 4 -dff");
-				run("techmap -map +/quicklogic/abc9_unmap.v");
+				run(stringf("techmap -map +/quicklogic/%s/abc9_unmap.v", family.c_str()));
 			} else {
 				run("abc -luts 1,2,2,4 -dress");
 			}
@@ -194,7 +213,7 @@ struct SynthQuickLogicPass : public ScriptPass {
 		}
 
 		if (check_label("map_cells")) {
-			run(stringf("techmap -map +/quicklogic/%s_lut_map.v", family.c_str()));
+			run(stringf("techmap -map +/quicklogic/%s/lut_map.v", family.c_str()));
 			run("clean");
 		}
 
@@ -218,17 +237,24 @@ struct SynthQuickLogicPass : public ScriptPass {
 			run("blackbox =A:whitebox");
 		}
 
-		if (check_label("blif")) {
+		if (check_label("blif", "(if -blif)")) {
 			if (!blif_file.empty() || help_mode) {
 				run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str()));
 			}
 		}
 
-		if (check_label("verilog")) {
+		if (check_label("verilog", "(if -verilog)")) {
 			if (!verilog_file.empty() || help_mode) {
 				run(stringf("write_verilog -noattr -nohex %s", help_mode ? "<file-name>" : verilog_file.c_str()));
 			}
 		}
+
+		if (check_label("edif", "(if -edif)")) {
+			if (!edif_file.empty() || help_mode) {
+				run("splitnets -ports -format ()");
+				run(stringf("write_edif -nogndvcc -attrprop -pvector par %s %s", top_opt.c_str(), edif_file.c_str()));
+			}
+		}
 	}
 
 } SynthQuicklogicPass;
diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys
index 73ee5cb44..47db42afc 100644
--- a/tests/arch/quicklogic/add_sub.ys
+++ b/tests/arch/quicklogic/add_sub.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT2
diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/adffs.ys
index 41a175844..43f36c20c 100644
--- a/tests/arch/quicklogic/adffs.ys
+++ b/tests/arch/quicklogic/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:dffepc
@@ -19,7 +19,7 @@ select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:*
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
@@ -36,7 +36,7 @@ select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT2
@@ -53,7 +53,7 @@ select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/counter.ys
index 2e266417c..9a7dcdf08 100644
--- a/tests/arch/quicklogic/counter.ys
+++ b/tests/arch/quicklogic/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -multiclock -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/dffs.ys
index e1fbef635..2bcfbf672 100644
--- a/tests/arch/quicklogic/dffs.ys
+++ b/tests/arch/quicklogic/dffs.ys
@@ -5,7 +5,7 @@ design -save read
 
 hierarchy -top my_dff
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd my_dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:ckpad
@@ -20,7 +20,7 @@ select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:*
 design -load read
 hierarchy -top my_dffe
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd my_dffe # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/fsm.ys
index 130dacf42..50dcb71b1 100644
--- a/tests/arch/quicklogic/fsm.ys
+++ b/tests/arch/quicklogic/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic
+equiv_opt -run :prove -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys
index 4b327c00a..9c34ddaeb 100644
--- a/tests/arch/quicklogic/logic.ys
+++ b/tests/arch/quicklogic/logic.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys
index ea17fa99b..5214bb787 100644
--- a/tests/arch/quicklogic/mux.ys
+++ b/tests/arch/quicklogic/mux.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
@@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 3 t:LUT3
@@ -27,7 +27,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
@@ -41,7 +41,7 @@ select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/tribuf.ys
index de763009e..d74fbbcdd 100644
--- a/tests/arch/quicklogic/tribuf.ys
+++ b/tests/arch/quicklogic/tribuf.ys
@@ -4,7 +4,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 2 t:inpad