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A fix in memory_dff for write ports with static addresses

This commit is contained in:
Clifford Wolf 2013-12-01 14:08:18 +01:00
parent 73e28f0e39
commit 97efc2ed5f
1 changed files with 10 additions and 10 deletions
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6
passes/memory/memory_dff.cc
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@ -31,7 +31,6 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
{ {
bool replaced_bits = false;
normalize_sig(module, sig); normalize_sig(module, sig);
sig.expand(); sig.expand();
@ -67,7 +66,6 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
chunk = d.chunks[0]; chunk = d.chunks[0];
clk = cell->connections["\\CLK"]; clk = cell->connections["\\CLK"];
clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
replaced_bits = true;
goto replaced_this_bit; goto replaced_this_bit;
} }
@ -76,7 +74,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
} }
sig.optimize(); sig.optimize();
return replaced_bits; return true;
} }
static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
@ -104,6 +102,7 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
return; return;
} }
if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
cell->connections["\\CLK"] = clk; cell->connections["\\CLK"] = clk;
cell->connections["\\ADDR"] = sig_addr; cell->connections["\\ADDR"] = sig_addr;
cell->connections["\\DATA"] = sig_data; cell->connections["\\DATA"] = sig_data;
@ -111,6 +110,7 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
log("merged $dff to cell.\n"); log("merged $dff to cell.\n");
}
} }
#if 1 #if 1