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verific: support VHDL enums too

This commit is contained in:
Eddie Hung 2020-04-27 15:17:13 -07:00
parent dd5f206d9e
commit 97bfe65d3a
1 changed files with 44 additions and 14 deletions
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30
frontends/verific/verific.cc
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@ -170,11 +170,14 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
return;
if (!type_range->IsTypeEnum())
return;
if (nl->IsFromVhdl() && strcmp(type_range->GetTypeName(), "STD_LOGIC") == 0)
return;
attributes.emplace(ID::wiretype, RTLIL::escape_id(type_range->GetTypeName()));
MapIter mi;
const char *k, *v;
FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) {
if (nl->IsFromVerilog()) {
// Expect <decimal>'b<binary>
auto p = strchr(v, '\'');
if (p) {
@ -191,6 +194,33 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
log_error("Expected TypeRange value '%s' to be of form <decimal>'b<binary>.\n", v);
attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k));
}
else if (nl->IsFromVhdl()) {
// Expect "<binary>"
auto p = v;
if (p) {
if (*p != '"')
p = nullptr;
else {
auto *q = p+1;
for (; *q != '"'; q++)
if (*q != '0' && *q != '1') {
p = nullptr;
break;
}
if (p && *(q+1) != '\0')
p = nullptr;
}
}
if (p == nullptr)
log_error("Expected TypeRange value '%s' to be of form \"<binary>\".\n", v);
auto l = strlen(p);
auto q = (char*)malloc(l+1-2);
strncpy(q, p+1, l-2);
q[l-2] = '\0';
attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k));
free(q);
}
}
}
}