riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Bugfix in "setundef" pass

This commit is contained in:
Clifford Wolf 2016-11-08 18:53:36 +01:00
parent 84badc97b3
commit 97ac77513f
1 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
passes/cmds/setundef.cc
View File

@ -90,6 +90,8 @@ struct SetundefPass : public Pass {
bool init_mode = false;
SetundefWorker worker;
log_header(design, "Executing SETUNDEF pass (replace undef values with defined constants).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@ -137,9 +139,12 @@ struct SetundefPass : public Pass {
SigPool undriven_signals;
for (auto &it : module->wires_)
if (!it.second->port_input)
undriven_signals.add(sigmap(it.second));
for (auto &it : module->wires_)
if (it.second->port_input)
undriven_signals.del(sigmap(it.second));
CellTypes ct(design);
for (auto &it : module->cells_)
for (auto &conn : it.second->connections())