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Packed SigBit::data and SigBit::offset in a union

This commit is contained in:
Clifford Wolf 2014-08-01 15:25:42 +02:00
parent 5e641acc90
commit 97a17d39e2
2 changed files with 13 additions and 9 deletions
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4
kernel/rtlil.cc
View File

@ -1681,9 +1681,11 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit) RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
{ {
wire = bit.wire; wire = bit.wire;
offset = 0;
if (wire == NULL) if (wire == NULL)
data = RTLIL::Const(bit.data); data = RTLIL::Const(bit.data);
offset = bit.offset; else
offset = bit.offset;
width = 1; width = 1;
} }

18
kernel/rtlil.h
View File

@ -707,15 +707,17 @@ struct RTLIL::SigChunk
struct RTLIL::SigBit struct RTLIL::SigBit
{ {
RTLIL::Wire *wire; RTLIL::Wire *wire;
RTLIL::State data; union {
int offset; RTLIL::State data;
int offset;
};
SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { } SigBit() : wire(NULL), data(RTLIL::State::S0) { }
SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { log_assert(wire && wire->width == 1); } SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); }
SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { log_assert(wire); } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { log_assert(chunk.width == 1); } SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; log_assert(chunk.width == 1); }
SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; }
SigBit(const RTLIL::SigSpec &sig); SigBit(const RTLIL::SigSpec &sig);
bool operator <(const RTLIL::SigBit &other) const { bool operator <(const RTLIL::SigBit &other) const {