mirror of https://github.com/YosysHQ/yosys.git
Fix spacing
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parent
d2172c6846
commit
978fda94f6
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@ -43,9 +43,8 @@ struct MuxpackWorker
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for (auto wire : module->wires())
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for (auto wire : module->wires())
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{
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{
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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for (auto bit : sigmap(wire)) {
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for (auto bit : sigmap(wire))
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sigbit_with_non_chain_users.insert(bit);
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sigbit_with_non_chain_users.insert(bit);
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}
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}
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}
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}
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}
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@ -58,8 +57,8 @@ struct MuxpackWorker
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SigSpec y_sig = sigmap(cell->getPort("\\Y"));
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SigSpec y_sig = sigmap(cell->getPort("\\Y"));
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if (sig_chain_next.count(a_sig))
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if (sig_chain_next.count(a_sig))
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for (auto a_bit : a_sig.bits())
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for (auto a_bit : a_sig.bits())
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sigbit_with_non_chain_users.insert(a_bit);
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sigbit_with_non_chain_users.insert(a_bit);
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else
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else
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sig_chain_next[a_sig] = cell;
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sig_chain_next[a_sig] = cell;
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@ -70,7 +69,7 @@ struct MuxpackWorker
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sig_chain_next[b_sig] = cell;
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sig_chain_next[b_sig] = cell;
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sig_chain_prev[y_sig] = cell;
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sig_chain_prev[y_sig] = cell;
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continue;
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continue;
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}
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}
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for (auto conn : cell->connections())
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for (auto conn : cell->connections())
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@ -182,7 +181,7 @@ struct MuxpackWorker
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first_cell->setPort("\\B", b_sig);
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first_cell->setPort("\\B", b_sig);
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first_cell->setPort("\\S", s_sig);
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first_cell->setPort("\\S", s_sig);
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first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
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first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
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first_cell->setPort("\\Y", last_cell->getPort("\\Y"));
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first_cell->setPort("\\Y", last_cell->getPort("\\Y"));
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cursor += cases;
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cursor += cases;
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