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Actually use pm.st.shiftxB

This commit is contained in:
Eddie Hung 2019-04-25 19:59:33 -07:00
parent f14d7f0df6
commit 976d8030dc
2 changed files with 6 additions and 3 deletions
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5
passes/pmgen/split_shiftx.cc
View File

@ -30,10 +30,11 @@ void create_split_shiftx(split_shiftx_pm &pm)
if (pm.blacklist_cells.count(pm.st.shiftx)) if (pm.blacklist_cells.count(pm.st.shiftx))
return; return;
SigSpec A = pm.st.shiftx->getPort("\\A"); SigSpec A = pm.st.shiftx->getPort("\\A");
SigSpec B = pm.st.shiftx->getPort("\\B"); SigSpec B = pm.st.shiftxB;
log_assert(!B.empty());
SigSpec Y = pm.st.shiftx->getPort("\\Y"); SigSpec Y = pm.st.shiftx->getPort("\\Y");
const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int(); const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int();
const int B_WIDTH = pm.st.shiftx->getParam("\\B_WIDTH").as_int(); const int B_WIDTH = GetSize(pm.st.shiftxB);
const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int(); const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int();
int trailing_zeroes = 0; int trailing_zeroes = 0;
for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ; for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ;

4
passes/pmgen/split_shiftx.pmg
View File

@ -12,11 +12,13 @@ match macc
endmatch endmatch
code shiftxB code shiftxB
shiftxB = port(shiftx, \B);
if (macc) { if (macc) {
shiftxB = port(shiftx, \B);
const int b_width = param(shiftx, \B_WIDTH).as_int(); const int b_width = param(shiftx, \B_WIDTH).as_int();
if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0) if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
shiftxB = shiftxB.extract(0, b_width-1); shiftxB = shiftxB.extract(0, b_width-1);
if (port(macc, \Y) != shiftxB) { if (port(macc, \Y) != shiftxB) {
blacklist(shiftx); blacklist(shiftx);
reject; reject;