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abc9 cleanup

This commit is contained in:
Eddie Hung 2019-02-25 18:40:53 -08:00
parent 316232a7dd
commit 967297cd57
1 changed files with 4 additions and 6 deletions
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10
passes/techmap/abc9.cc
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@ -892,21 +892,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
} }
log_assert(GetSize(signal) >= GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire));
if (w->port_input) { log_assert(w->port_input || w->port_output);
RTLIL::SigSig conn; RTLIL::SigSig conn;
if (w->port_input) {
conn.first = remap_wire; conn.first = remap_wire;
conn.second = signal; conn.second = signal;
in_wires++; in_wires++;
module->connect(conn);
} }
else if (w->port_output) { if (w->port_output) {
RTLIL::SigSig conn;
conn.first = signal; conn.first = signal;
conn.second = remap_wire; conn.second = remap_wire;
out_wires++; out_wires++;
module->connect(conn);
} }
else log_abort(); module->connect(conn);
} }
//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);