Remove asicworld tests for (unsupported) switch-level modelling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

tests/asicworld/code_hdl_models_misc1.v

@@ -1,22 +0,0 @@
-module misc1 (a,b,c,d,y);
-input a, b,c,d;
-output y;
-
-wire net1,net2,net3;
-
-supply1 vdd;
-supply0 vss;
-
-// y = !((a+b+c).d)
-
-pmos p1 (vdd,net1,a);
-pmos p2 (net1,net2,b);
-pmos p3 (net2,y,c);
-pmos p4 (vdd,y,d);
-
-nmos n1 (vss,net3,a);
-nmos n2 (vss,net3,b);
-nmos n3 (vss,net3,c);
-nmos n4 (net3,y,d);
-
-endmodule

tests/asicworld/code_hdl_models_mux21_switch.v

@@ -1,22 +0,0 @@
-//-----------------------------------------------------
-// Design Name : mux21_switch
-// File Name   : mux21_switch.v
-// Function    : 2:1 Mux using Switch Primitives
-// Coder       : Deepak Kumar Tala
-//-----------------------------------------------------
-module mux21_switch (out, ctrl, in1, in2);
-   
-   output out;                    
-   input  ctrl, in1, in2;         
-   wire          w;            
-
-   supply1 power;             
-   supply0 ground;      
-   
-   pmos N1 (w, power, ctrl);     
-   nmos N2 (w, ground, ctrl);   
-   
-   cmos C1 (out, in1, w, ctrl);   
-   cmos C2 (out, in2, ctrl, w);
-   
-endmodule

tests/asicworld/code_hdl_models_nand_switch.v

@@ -1,14 +0,0 @@
-module nand_switch(a,b,out);
-input a,b;
-output out;
-
-supply0 vss;
-supply1 vdd;
-wire net1;
-
-pmos p1 (vdd,out,a);
-pmos p2 (vdd,out,b);
-nmos n1 (vss,net1,a);
-nmos n2 (net1,out,b);
-
-endmodule

tests/asicworld/code_hdl_models_t_gate_switch.v

@@ -1,11 +0,0 @@
-module t_gate_switch (L,R,nC,C);
- inout L;
- inout R;
- input nC;
- input C;
-
- //Syntax: keyword unique_name (drain. source, gate);
- pmos p1 (L,R,nC);
- nmos p2 (L,R,C);
-
-endmodule