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More flexible handling of initialization values

This commit is contained in:
Clifford Wolf 2016-04-22 12:13:06 +02:00
parent 0bc95f1e04
commit 965b0d59b5
1 changed files with 22 additions and 7 deletions
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29
passes/proc/proc_init.cc
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@ -61,13 +61,28 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
int offset = 0;
for (auto &lhs_c : lhs.chunks()) {
if (lhs_c.wire != NULL) {
RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
if (value.size() != lhs_c.wire->width)
log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
lhs_c.wire->attributes["\\init"] = value.as_const();
for (auto &lhs_c : lhs.chunks())
{
if (lhs_c.wire != nullptr)
{
SigSpec valuesig = rhs.extract(offset, lhs_c.width);
if (!valuesig.is_fully_const())
log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
Const value = valuesig.as_const();
Const &wireinit = lhs_c.wire->attributes["\\init"];
while (GetSize(wireinit.bits) < lhs_c.wire->width)
wireinit.bits.push_back(State::Sx);
for (int i = 0; i < lhs_c.width; i++) {
auto &initbit = wireinit.bits[i + lhs_c.offset];
if (initbit != State::Sx && initbit != value[i])
log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
initbit = value[i];
}
log(" Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
}
offset += lhs_c.width;
}