mirror of https://github.com/YosysHQ/yosys.git
More flexible handling of initialization values
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@ -61,13 +61,28 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
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log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
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log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
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int offset = 0;
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int offset = 0;
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for (auto &lhs_c : lhs.chunks()) {
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for (auto &lhs_c : lhs.chunks())
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if (lhs_c.wire != NULL) {
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{
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RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
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if (lhs_c.wire != nullptr)
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if (value.size() != lhs_c.wire->width)
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{
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log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
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SigSpec valuesig = rhs.extract(offset, lhs_c.width);
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log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
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if (!valuesig.is_fully_const())
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lhs_c.wire->attributes["\\init"] = value.as_const();
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log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
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Const value = valuesig.as_const();
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Const &wireinit = lhs_c.wire->attributes["\\init"];
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while (GetSize(wireinit.bits) < lhs_c.wire->width)
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wireinit.bits.push_back(State::Sx);
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for (int i = 0; i < lhs_c.width; i++) {
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auto &initbit = wireinit.bits[i + lhs_c.offset];
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if (initbit != State::Sx && initbit != value[i])
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log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
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initbit = value[i];
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}
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log(" Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
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}
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}
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offset += lhs_c.width;
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offset += lhs_c.width;
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}
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}
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