riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add support {A,B,P}REG packing

This commit is contained in:
Eddie Hung 2019-07-16 14:06:32 -07:00
parent d086dfb5b0
commit 9616dbd125
2 changed files with 95 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
passes/pmgen/xilinx_dsp.cc
View File

@ -25,46 +25,60 @@ PRIVATE_NAMESPACE_BEGIN
#include "passes/pmgen/xilinx_dsp_pm.h" #include "passes/pmgen/xilinx_dsp_pm.h"
void create_xilinx_dsp(xilinx_dsp_pm &pm) void pack_xilinx_dsp(xilinx_dsp_pm &pm)
{ {
auto &st = pm.st_xilinx_dsp; auto &st = pm.st_xilinx_dsp;
#if 0 #if 1
log("\n"); log("\n");
log("ffA: %s\n", log_id(st.ffA, "--")); log("ffA: %s\n", log_id(st.ffA, "--"));
log("ffB: %s\n", log_id(st.ffB, "--")); log("ffB: %s\n", log_id(st.ffB, "--"));
log("mul: %s\n", log_id(st.mul, "--")); log("dsp: %s\n", log_id(st.dsp, "--"));
log("ffY: %s\n", log_id(st.ffY, "--")); log("ffP: %s\n", log_id(st.ffP, "--"));
log("muxP: %s\n", log_id(st.muxP, "--"));
log("P_WIDTH: %d\n", st.P_WIDTH);
#endif #endif
log("Analysing %s.%s for Xilinx DSP register packing.\n", log_id(pm.module), log_id(st.mul)); log("Analysing %s.%s for Xilinx DSP register packing.\n", log_id(pm.module), log_id(st.dsp));
Cell *cell = st.mul; Cell *cell = st.dsp;
log_assert(cell); log_assert(cell);
// Input Interface
cell->setPort("\\A", st.sigA);
cell->setPort("\\B", st.sigB);
cell->setParam("\\AREG", st.ffA ? State::S1 : State::S0);
cell->setParam("\\BREG", st.ffB ? State::S1 : State::S0);
if (st.clock != SigBit()) if (st.clock != SigBit())
{ {
cell->setPort("\\CLK", st.clock); cell->setPort("\\CLK", st.clock);
if (st.ffA) { if (st.ffA) {
SigSpec D = st.ffA->getPort("\\D");
cell->setPort("\\A", D.extend_u0(30));
cell->setParam("\\AREG", State::S1); cell->setParam("\\AREG", State::S1);
cell->setPort("\\CEA2", State::S1); if (st.ffA->type == "$dff")
cell->setPort("\\CEA2", State::S1);
else if (st.ffA->type == "$dffe")
cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
else log_abort();
} }
if (st.ffB) { if (st.ffB) {
SigSpec D = st.ffB->getPort("\\D");
cell->setPort("\\B", D.extend_u0(18));
cell->setParam("\\BREG", State::S1); cell->setParam("\\BREG", State::S1);
cell->setPort("\\CEA2", State::S1); if (st.ffB->type == "$dff")
cell->setPort("\\CEB2", State::S1);
else if (st.ffB->type == "$dffe")
cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
else log_abort();
} }
if (st.ffY) { if (st.ffP) {
cell->setPort("\\PREG", State::S1); SigSpec P = cell->getPort("\\P");
cell->setPort("\\CEP", State::S1); SigSpec Q = st.ffP->getPort("\\Q");
Q.append(P.extract(GetSize(Q), -1));
cell->setPort("\\P", Q);
cell->setParam("\\PREG", State::S1);
if (st.ffP->type == "$dff")
cell->setPort("\\CEP", State::S1);
else if (st.ffP->type == "$dffe")
cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
else log_abort();
} }
log(" clock: %s (%s)", log_signal(st.clock), "posedge"); log(" clock: %s (%s)", log_signal(st.clock), "posedge");
@ -75,15 +89,17 @@ void create_xilinx_dsp(xilinx_dsp_pm &pm)
if (st.ffB) if (st.ffB)
log(" ffB:%s", log_id(st.ffB)); log(" ffB:%s", log_id(st.ffB));
if (st.ffY) if (st.ffP)
log(" ffY:%s", log_id(st.ffY)); log(" ffY:%s", log_id(st.ffP));
log("\n"); log("\n");
} }
// Output Interface pm.autoremove(st.ffA);
pm.autoremove(st.ffB);
pm.autoremove(st.ffY); pm.autoremove(st.ffP);
pm.autoremove(st.muxP);
pm.blacklist(cell);
} }
struct Ice40DspPass : public Pass { struct Ice40DspPass : public Pass {
@ -99,7 +115,7 @@ struct Ice40DspPass : public Pass {
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing ICE40_DSP pass (map multipliers).\n"); log_header(design, "Executing XILINX_DSP pass (pack DSPs).\n");
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -113,7 +129,7 @@ struct Ice40DspPass : public Pass {
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(create_xilinx_dsp); xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(pack_xilinx_dsp);
} }
} Ice40DspPass; } Ice40DspPass;

83
passes/pmgen/xilinx_dsp.pmg
View File

@ -1,44 +1,36 @@
pattern xilinx_dsp pattern xilinx_dsp
state <SigBit> clock state <SigBit> clock
state <SigSpec> sigA sigB sigY sigS state <int> P_WIDTH
state <Cell*> addAB muxAB
match mul match dsp
select mul->type.in($__MUL25X18) select dsp->type.in(\DSP48E1)
endmatch endmatch
match ffA match ffA
select ffA->type.in($dff) /* TODO: $dffe */ select ffA->type.in($dff, $dffe)
// select nusers(port(ffA, \Q)) == 2 // select nusers(port(ffA, \Q)) == 2
index <SigSpec> port(ffA, \Q) === port(mul, \A) index <SigSpec> port(ffA, \Q).extend_u0(30) === port(dsp, \A)
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
index <SigBit> port(ffA, \CLK_POLARITY) === State::S1 index <Const> param(ffA, \CLK_POLARITY).as_bool() === true
optional optional
endmatch endmatch
code sigA clock code clock
sigA = port(mul, \A); if (ffA)
if (ffA) {
sigA = port(ffA, \D);
clock = port(ffA, \CLK).as_bit(); clock = port(ffA, \CLK).as_bit();
}
endcode endcode
match ffB match ffB
select ffB->type.in($dff) select ffB->type.in($dff, $dffe)
// select nusers(port(ffB, \Q)) == 2 // select nusers(port(ffB, \Q)) == 2
index <SigSpec> port(ffB, \Q) === port(mul, \B) index <SigSpec> port(ffB, \Q).extend_u0(18) === port(dsp, \B)
index <SigBit> port(ffB, \CLK_POLARITY) === State::S1 index <Const> param(ffB, \CLK_POLARITY).as_bool() === true
optional optional
endmatch endmatch
code sigB clock code clock
sigB = port(mul, \B);
if (ffB) { if (ffB) {
sigB = port(ffB, \D);
SigBit c = port(ffB, \CLK).as_bit(); SigBit c = port(ffB, \CLK).as_bit();
if (clock != SigBit() && c != clock) if (clock != SigBit() && c != clock)
@ -48,20 +40,51 @@ code sigB clock
} }
endcode endcode
match ffY code P_WIDTH
select ffY->type.in($dff) SigSpec P = port(dsp, \P);
select nusers(port(ffY, \D)) == 2 int i;
index <SigSpec> port(ffY, \D) === port(mul, \Y) for (i = GetSize(P); i > 0; i--)
index <SigBit> port(ffY, \CLK_POLARITY) === State::S1 if (nusers(P[i-1]) > 1)
break;
P_WIDTH = i;
endcode
match ffP
select ffP->type.in($dff, $dffe)
select nusers(port(ffP, \D)) == 2
filter param(ffP, \WIDTH).as_int() == P_WIDTH
filter port(ffP, \D) == port(dsp, \P).extract(0, P_WIDTH)
index <Const> param(ffP, \CLK_POLARITY) === State::S1
optional optional
endmatch endmatch
code sigY clock // $mux cell left behind by dff2dffe
sigY = port(mul, \Y); // would prefer not to run 'opt_expr -mux_undef'
// since that would lose information helpful for
// efficient wide-mux inference
match muxP
if !ffP
select muxP->type.in($mux)
select port(muxP, \A).is_fully_undef()
filter param(muxP, \WIDTH).as_int() == P_WIDTH
filter port(muxP, \B) == port(dsp, \P).extract(0, P_WIDTH)
select nusers(port(muxP, \B)) == 2
optional
endmatch
if (ffY) { match ffY
sigY = port(ffY, \Q); if muxP
SigBit c = port(ffY, \CLK).as_bit(); select ffY->type.in($dff, $dffe)
select nusers(port(ffY, \D)) == 2
index <SigSpec> port(ffY, \D) === port(muxP, \Y)
endmatch
code ffP clock
if (ffY)
ffP = ffY;
if (ffP) {
SigBit c = port(ffP, \CLK).as_bit();
if (clock != SigBit() && c != clock) if (clock != SigBit() && c != clock)
reject; reject;