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Update doc

This commit is contained in:
Eddie Hung 2019-09-26 13:44:41 -07:00
parent 58f31096ab
commit 95f0dd57df
1 changed files with 2 additions and 1 deletions
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3
passes/pmgen/xilinx_dsp.cc
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@ -578,7 +578,8 @@ struct XilinxDspPass : public Pass {
log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n");
log("input to the post-adder -- a pattern common for summing partial products to\n");
log("implement wide multipliers).\n");
log("implement wide multipliers). Initial support also exists for similar cascading\n");
log("for AREG and BREG using '[AB]OUT' -> '[AB]IN'.\n");
log("\n");
log("\n");
log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");