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xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) 

Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-07-16 16:46:41 +01:00
parent 8da4c1ad82
commit 95c8d27b0b
2 changed files with 8 additions and 4 deletions
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6
techlibs/xilinx/cells_map.v
View File

@ -366,7 +366,7 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
endmodule endmodule
`endif `endif
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] OUT);
wire [47:0] P_48; wire [47:0] P_48;
DSP48E1 #( DSP48E1 #(
// Disable all registers // Disable all registers
@ -388,8 +388,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
.PREG(0) .PREG(0)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
//Data path //Data path
.A({5'b0, A}), .A({6'b0, A}),
.B(B), .B({1'b0, B}),
.C(48'b0), .C(48'b0),
.D(24'b0), .D(24'b0),
.P(P_48), .P(P_48),

6
techlibs/xilinx/synth_xilinx.cc
View File

@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
// The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
// Due to current limitations of mul2dsp, we are actually mapping as a 24x17
// unsigned multiply with MSBs set to 1'b0
if (!nodsp || help_mode) if (!nodsp || help_mode)
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18");
run("alumacc"); run("alumacc");
run("share"); run("share");