mirror of https://github.com/YosysHQ/yosys.git
proc_clean: fix fully def check to consider compare/signal length.
Fixes #790.
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@ -82,9 +82,15 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
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{
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{
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if (max_depth != 0)
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if (max_depth != 0)
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proc_clean_case(cs, did_something, count, max_depth-1);
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proc_clean_case(cs, did_something, count, max_depth-1);
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int size = 0;
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for (auto cmp : cs->compare)
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for (auto cmp : cs->compare)
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if (!cmp.is_fully_def())
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{
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size += cmp.size();
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if (cmp.is_fully_def())
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all_fully_def = false;
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all_fully_def = false;
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}
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if (sw->signal.size() != size)
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all_fully_def = false;
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}
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}
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if (all_fully_def)
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if (all_fully_def)
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{
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{
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