From d6bd521487944ded68d8590295581f178d94437a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 21 Nov 2024 13:43:26 +0100 Subject: [PATCH] verific : VHDL assert DFF initial value set on Verific library patch side --- frontends/verific/verific.cc | 6 ------ 1 file changed, 6 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a247bc2eb..bdd3eafa2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma log(" assert condition %s.\n", log_signal(cond)); Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1); - // Initialize FF feeding condition to 1, in case it is not - // used by rest of design logic, to prevent failing on - // initial uninitialized state - if (cond.is_wire() && !cond.wire->name.isPublic()) - cond.wire->attributes[ID::init] = Const(1,1); - import_attributes(cell->attributes, inst); continue; }