From 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b Mon Sep 17 00:00:00 2001 From: Diego H Date: Tue, 26 Nov 2019 17:14:41 -0600 Subject: [PATCH 01/46] Adjusting Vivado's BRAM min bits threshold for RAMB18E1 --- techlibs/xilinx/xc7_xcu_brams.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index f1161114e..ee961fff8 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -81,7 +81,7 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -97,9 +97,12 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp endmatch +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. + From 184c0e796a0e6870c025808b1902da5f3771b721 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 7 Dec 2019 13:04:36 +0000 Subject: [PATCH 02/46] ecp5: Add support for mapping PRLD FFs Signed-off-by: David Shah --- techlibs/ecp5/cells_map.v | 15 +++++++++++++++ techlibs/ecp5/synth_ecp5.cc | 17 +++++++++++++---- 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 71ae9237b..10e89a3e0 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -47,6 +47,21 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), . module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +`ifdef ASYNC_PRLD +module \$_DLATCH_N_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(!E), .DI(1'b0), .M(D), .Q(Q)); endmodule +module \$_DLATCH_P_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(E), .DI(1'b0), .M(D), .Q(Q)); endmodule + +module \$_DFFSR_NNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_NNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule +module \$_DFFSR_NPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_NPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule + +module \$_DFFSR_PNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_PNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule +module \$_DFFSR_PPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_PPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule +`endif + `include "cells_ff.vh" `include "cells_io.vh" diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 4cbb56ea1..b71bb2395 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -79,6 +79,9 @@ struct SynthEcp5Pass : public ScriptPass log(" -nowidelut\n"); log(" do not use PFU muxes to implement LUTs larger than LUT4s\n"); log("\n"); + log(" -asyncprld\n"); + log(" use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)\n"); + log("\n"); log(" -abc2\n"); log(" run two passes of 'abc' for slightly improved logic density\n"); log("\n"); @@ -99,7 +102,7 @@ struct SynthEcp5Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, retime, abc2, abc9, nodsp, vpr; void clear_flags() YS_OVERRIDE { @@ -112,6 +115,7 @@ struct SynthEcp5Pass : public ScriptPass nobram = false; nolutram = false; nowidelut = false; + asyncprld = false; flatten = true; retime = false; abc2 = false; @@ -176,6 +180,10 @@ struct SynthEcp5Pass : public ScriptPass nobram = true; continue; } + if (args[argidx] == "-asyncprld") { + asyncprld = true; + continue; + } if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") { nolutram = true; continue; @@ -292,7 +300,7 @@ struct SynthEcp5Pass : public ScriptPass run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); - run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); + run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : ""))); run("opt_expr -undriven -mux_undef"); run("simplemap"); run("ecp5_ffinit"); @@ -306,10 +314,11 @@ struct SynthEcp5Pass : public ScriptPass if (abc2 || help_mode) { run("abc", " (only if -abc2)"); } - std::string techmap_args = "-map +/ecp5/latches_map.v"; + std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v"; if (abc9) techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1"; - run("techmap " + techmap_args); + if (!asyncprld || abc9) + run("techmap " + techmap_args); if (abc9) { run("read_verilog -icells -lib +/ecp5/abc9_model.v"); From 993a77d19b3fb56ef2da3a6dfafa8a1488039d01 Mon Sep 17 00:00:00 2001 From: Gustavo Romero Date: Wed, 11 Dec 2019 08:09:48 -0300 Subject: [PATCH 03/46] manual: Fix text in Abstract section --- manual/manual.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manual/manual.tex b/manual/manual.tex index 67982cbc8..75f087eca 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -146,7 +146,7 @@ with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or when testing new synthesis algorithms it might be necessary to write a custom HDL -synthesis tool or add new features to an existing one. It this cases the +synthesis tool or add new features to an existing one. In these cases the availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful. From 4c7cda1c8b8a782da90f6bbd00e0a98aa1817f6e Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 12 Dec 2019 16:14:20 +0100 Subject: [PATCH 04/46] add a command to read/modify scratchpad contents --- passes/cmds/Makefile.inc | 1 + passes/cmds/scratchpad.cc | 86 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 passes/cmds/scratchpad.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index c7edc30fb..07a5d3ddc 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -32,3 +32,4 @@ OBJS += passes/cmds/chtype.o OBJS += passes/cmds/blackbox.o OBJS += passes/cmds/ltp.o OBJS += passes/cmds/bugpoint.o +OBJS += passes/cmds/scratchpad.o diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc new file mode 100644 index 000000000..7d53c8a4f --- /dev/null +++ b/passes/cmds/scratchpad.cc @@ -0,0 +1,86 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct ScratchpadPass : public Pass { + ScratchpadPass() : Pass("scratchpad", "get/set values in the scratchpad") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" scratchpad [ -get id | -set id val | -unset id | -copy id1 id2 ]\n"); + log("\n"); + log("This pass allows to read and modify values from the scratchpad of the current\n"); + log("design. Options:\n"); + log(" -get \n"); + log(" -set \n"); + log(" -unset \n"); + log(" -copy \n"); + log("The identifier may not contain whitespace. By convention, it is usually prefixed\n"); + log("by the name of the pass that uses it, e.g. 'opt.did_something'. If the value\n"); + log("contains whitespace, it must be enclosed in double quotes.\n"); + log("\n"); + } + + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-get" && argidx+1 < args.size()) { + string identifier = args[++argidx]; + if (design->scratchpad.count(identifier)){ + log("%s\n", design->scratchpad_get_string(identifier).c_str()); + } else { + log("\"%s\" not set\n", identifier.c_str()); + } + continue; + } + if (args[argidx] == "-set" && argidx+2 < args.size()) { + string identifier = args[++argidx]; + string value = args[++argidx]; + if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2); + design->scratchpad_set_string(identifier, value); + continue; + } + if (args[argidx] == "-unset" && argidx+1 < args.size()) { + string identifier = args[++argidx]; + design->scratchpad_unset(identifier); + continue; + } + if (args[argidx] == "-copy" && argidx+2 < args.size()) { + string identifier_from = args[++argidx]; + string identifier_to = args[++argidx]; + if (design->scratchpad.count(identifier_from) == 0) log_error("\"%s\" not set\n", identifier_from.c_str()); + string value = design->scratchpad_get_string(identifier_from); + design->scratchpad_set_string(identifier_to, value); + continue; + } + log("Unrecognized argument: %s\n", args[argidx].c_str()); + break; + } + } +} ScratchpadPass; +PRIVATE_NAMESPACE_END From 937ec1ee78e5470c148d8c39387c7a80711af8a7 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 13:50:36 -0600 Subject: [PATCH 05/46] Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 --- techlibs/xilinx/xc7_xcu_brams.txt | 4 +-- tests/arch/common/memory_params.v | 45 ++++++++++++++++++++++++++++++ tests/arch/xilinx/memory_params.ys | 45 ++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 tests/arch/common/memory_params.v create mode 100644 tests/arch/xilinx/memory_params.ys diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index ee961fff8..87e659bbc 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -73,7 +73,7 @@ bram $__XILINX_RAMB18_TDP endbram match $__XILINX_RAMB36_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -89,7 +89,7 @@ match $__XILINX_RAMB18_SDP endmatch match $__XILINX_RAMB36_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp diff --git a/tests/arch/common/memory_params.v b/tests/arch/common/memory_params.v new file mode 100644 index 000000000..dbc6ca65c --- /dev/null +++ b/tests/arch/common/memory_params.v @@ -0,0 +1,45 @@ +`default_nettype none +module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sp + + +`default_nettype none +module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r <= memory[address_in_r]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sdp + diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys new file mode 100644 index 000000000..f279a4a6e --- /dev/null +++ b/tests/arch/xilinx/memory_params.ys @@ -0,0 +1,45 @@ +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits and addr <= 36: -> RAMB36E1 +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + From 1187e91c2f2684cb204c555cb3d53b68c7381c40 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 12 Dec 2019 20:51:59 +0100 Subject: [PATCH 06/46] add test and make help message more verbose --- passes/cmds/scratchpad.cc | 7 ++++++- tests/various/scratchpad.sh | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) create mode 100755 tests/various/scratchpad.sh diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index 7d53c8a4f..c11c41caf 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf + * 2019 Nina Engelhardt * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -30,14 +31,18 @@ struct ScratchpadPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" scratchpad [ -get id | -set id val | -unset id | -copy id1 id2 ]\n"); + log(" scratchpad [options]\n"); log("\n"); log("This pass allows to read and modify values from the scratchpad of the current\n"); log("design. Options:\n"); log(" -get \n"); + log(" print the value saved in the scratchpad under the given identifier\n"); log(" -set \n"); + log(" save the given value in the scratchpad under the given identifier\n"); log(" -unset \n"); + log(" remove the entry for the given identifier from the scratchpad\n"); log(" -copy \n"); + log(" copy the value of the first identifier to the second identifier\n"); log("The identifier may not contain whitespace. By convention, it is usually prefixed\n"); log("by the name of the pass that uses it, e.g. 'opt.did_something'. If the value\n"); log("contains whitespace, it must be enclosed in double quotes.\n"); diff --git a/tests/various/scratchpad.sh b/tests/various/scratchpad.sh new file mode 100755 index 000000000..4e92473f8 --- /dev/null +++ b/tests/various/scratchpad.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +trap 'echo "ERROR in scratchpad.sh" >&2; exit 1' ERR + +../../yosys -qp "scratchpad -set foo \"bar baz\"; \ +scratchpad -copy foo oof; scratchpad -unset foo; \ +tee -o scratchpad1.log scratchpad -get oof; \ +tee -o scratchpad2.log scratchpad -get foo" + +test "$(cat scratchpad1.log)" = "bar baz" +test "$(cat scratchpad2.log)" = "\"foo\" not set" + +rm scratchpad1.log +rm scratchpad2.log From e33f407655fa516cb2f6754103973eb156ca90cf Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 16:06:46 -0600 Subject: [PATCH 07/46] Adding a note (TODO) in the memory_params.ys check file --- tests/arch/xilinx/memory_params.ys | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index f279a4a6e..657629e0f 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -1,3 +1,5 @@ +## TODO: Not running equivalence checking because BRAM models does not exists +## currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 read_verilog ../common/memory_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp From 751a18d7e974123352e372c75bb17226e6fabec0 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 17:32:58 -0600 Subject: [PATCH 08/46] Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. --- techlibs/xilinx/xc7_xcu_brams.txt | 10 +++++----- tests/arch/xilinx/memory_params.ys | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 87e659bbc..b7c893ff7 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -1,4 +1,3 @@ - bram $__XILINX_RAMB36_SDP init 1 abits 9 @@ -72,6 +71,11 @@ bram $__XILINX_RAMB18_TDP clkpol 2 3 endbram +# The "min bits" value were taken from: +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. +# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf + match $__XILINX_RAMB36_SDP min bits 1024 min efficiency 5 @@ -102,7 +106,3 @@ match $__XILINX_RAMB18_TDP shuffle_enable B make_transp endmatch - -# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), -# v1.14 ed., p 29-30, July, 2019. - diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index 657629e0f..c1b0ca489 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -37,10 +37,10 @@ cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 select -assert-count 4 t:RAM128X1D -# More than 18K bits and addr <= 36: -> RAMB36E1 +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB36E1 From caab66111e2b5052bd26c8fd64b1324e7e4a4106 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 17:44:37 -0800 Subject: [PATCH 09/46] Rename memory tests to lutram, add more xilinx tests --- tests/arch/anlogic/{memory.ys => lutram.ys} | 6 +- tests/arch/common/lutram.v | 42 +++++++++ tests/arch/common/memory.v | 21 ----- tests/arch/ecp5/{memory.ys => lutram.ys} | 6 +- tests/arch/efinix/{memory.ys => lutram.ys} | 6 +- tests/arch/gowin/{memory.ys => lutram.ys} | 6 +- tests/arch/ice40/{memory.ys => lutram.ys} | 6 +- tests/arch/xilinx/lutram.ys | 99 +++++++++++++++++++++ tests/arch/xilinx/memory.ys | 17 ---- 9 files changed, 156 insertions(+), 53 deletions(-) rename tests/arch/anlogic/{memory.ys => lutram.ys} (90%) create mode 100644 tests/arch/common/lutram.v delete mode 100644 tests/arch/common/memory.v rename tests/arch/ecp5/{memory.ys => lutram.ys} (87%) rename tests/arch/efinix/{memory.ys => lutram.ys} (87%) rename tests/arch/gowin/{memory.ys => lutram.ys} (87%) rename tests/arch/ice40/{memory.ys => lutram.ys} (82%) create mode 100644 tests/arch/xilinx/lutram.ys delete mode 100644 tests/arch/xilinx/memory.ys diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/lutram.ys similarity index 90% rename from tests/arch/anlogic/memory.ys rename to tests/arch/anlogic/lutram.ys index 87b93c2fe..9ebb75443 100644 --- a/tests/arch/anlogic/memory.ys +++ b/tests/arch/anlogic/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic @@ -11,7 +11,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 8 t:AL_MAP_LUT2 select -assert-count 8 t:AL_MAP_LUT4 diff --git a/tests/arch/common/lutram.v b/tests/arch/common/lutram.v new file mode 100644 index 000000000..9534b7619 --- /dev/null +++ b/tests/arch/common/lutram.v @@ -0,0 +1,42 @@ +module lutram_1w1r +#(parameter D_WIDTH=8, A_WIDTH=6) +( + input [D_WIDTH-1:0] data_a, + input [A_WIDTH:1] addr_a, + input we_a, clk, + output reg [D_WIDTH-1:0] q_a +); + // Declare the RAM variable + reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + ram[addr_a] <= data_a; + q_a <= ram[addr_a]; + end +endmodule + + +module lutram_1w3r +#(parameter D_WIDTH=8, A_WIDTH=5) +( + input [D_WIDTH-1:0] data_a, data_b, data_c, + input [A_WIDTH:1] addr_a, addr_b, addr_c, + input we_a, clk, + output reg [D_WIDTH-1:0] q_a, q_b, q_c +); + // Declare the RAM variable + reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + ram[addr_a] <= data_a; + q_a <= ram[addr_a]; + q_b <= ram[addr_b]; + q_c <= ram[addr_c]; + end +endmodule diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/common/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/lutram.ys similarity index 87% rename from tests/arch/ecp5/memory.ys rename to tests/arch/ecp5/lutram.ys index c82b7b405..e1ae7abd5 100644 --- a/tests/arch/ecp5/memory.ys +++ b/tests/arch/ecp5/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 @@ -10,7 +10,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 24 t:L6MUX21 select -assert-count 71 t:LUT4 select -assert-count 32 t:PFUMX diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/lutram.ys similarity index 87% rename from tests/arch/efinix/memory.ys rename to tests/arch/efinix/lutram.ys index 6f6acdcde..dcf647ce0 100644 --- a/tests/arch/efinix/memory.ys +++ b/tests/arch/efinix/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix @@ -12,7 +12,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_RAM_5K select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/lutram.ys similarity index 87% rename from tests/arch/gowin/memory.ys rename to tests/arch/gowin/lutram.ys index 8f88cdd7c..56f69e7c5 100644 --- a/tests/arch/gowin/memory.ys +++ b/tests/arch/gowin/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin @@ -12,7 +12,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 8 t:RAM16S4 # other logic present that is not simple #select -assert-none t:RAM16S4 %% t:* %D diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/lutram.ys similarity index 82% rename from tests/arch/ice40/memory.ys rename to tests/arch/ice40/lutram.ys index c356e67fb..1ba40f8ec 100644 --- a/tests/arch/ice40/memory.ys +++ b/tests/arch/ice40/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 @@ -10,6 +10,6 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys new file mode 100644 index 000000000..9b2c30ba1 --- /dev/null +++ b/tests/arch/xilinx/lutram.ys @@ -0,0 +1,99 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM16X1D +select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 5 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM32X1D +select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM64X1D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w3r +proc +memory -nomap +synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w3r +select -assert-count 1 t:BUFG +select -assert-count 24 t:FDRE +select -assert-count 4 t:RAM32M +select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w3r -chparam A_WIDTH 6 +proc +memory -nomap +synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w3r +select -assert-count 1 t:BUFG +select -assert-count 24 t:FDRE +select -assert-count 8 t:RAM64M +select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys deleted file mode 100644 index da1ed0e49..000000000 --- a/tests/arch/xilinx/memory.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM64X1D -select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D From 7a9d1be97d100c265530270810071e2e9e676b3e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 17:44:59 -0800 Subject: [PATCH 10/46] Add memory rules for RAM16X1D, RAM32M, RAM64M --- techlibs/xilinx/lutrams.txt | 64 +++++++++++++++++++++ techlibs/xilinx/lutrams_map.v | 104 ++++++++++++++++++++++++++++++++++ 2 files changed, 168 insertions(+) diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index 2613c206c..3e260b0d7 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -1,4 +1,17 @@ +bram $__XILINX_RAM16X1D + init 1 + abits 4 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM32X1D init 1 abits 5 @@ -38,6 +51,41 @@ bram $__XILINX_RAM128X1D clkpol 0 2 endbram + +bram $__XILINX_RAM32M + init 1 + abits 5 + dbits 2 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64M + init 1 + abits 6 + dbits 1 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +match $__XILINX_RAM16X1D + min bits 2 + min wports 1 + make_outreg + or_next_if_better +endmatch + match $__XILINX_RAM32X1D min bits 3 min wports 1 @@ -56,5 +104,21 @@ match $__XILINX_RAM128X1D min bits 9 min wports 1 make_outreg + or_next_if_better endmatch + +match $__XILINX_RAM32M + min bits 5 + min rports 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64M + min bits 5 + min rports 3 + min wports 1 + make_outreg +endmatch diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v index 77041ca86..985e53ff4 100644 --- a/techlibs/xilinx/lutrams_map.v +++ b/techlibs/xilinx/lutrams_map.v @@ -1,4 +1,36 @@ +module \$__XILINX_RAM16X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [15:0] INIT = 16'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [3:0] A1ADDR; + output A1DATA; + + input [3:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM16X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA0(A1ADDR[0]), + .DPRA1(A1ADDR[1]), + .DPRA2(A1ADDR[2]), + .DPRA3(A1ADDR[3]), + .DPO(A1DATA), + + .A0(B1ADDR[0]), + .A1(B1ADDR[1]), + .A2(B1ADDR[2]), + .A3(B1ADDR[3]), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); parameter [31:0] INIT = 32'bx; parameter CLKPOL2 = 1; @@ -95,3 +127,75 @@ module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); ); endmodule + +module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); + parameter [31:0] INIT = 32'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [4:0] A1ADDR, A2ADDR, A3ADDR; + output [1:0] A1DATA, A2DATA, A3DATA; + + input [4:0] B1ADDR; + input [1:0] B1DATA; + input B1EN; + + RAM32M #( + .INIT_A(INIT), + .INIT_B(INIT), + .INIT_C(INIT), + .INIT_D(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .ADDRA(A1ADDR), + .ADDRB(A2ADDR), + .ADDRC(A3ADDR), + .DOA(A1DATA), + .DOB(A2DATA), + .DOC(A3DATA), + + .ADDRD(B1ADDR), + .DIA(B1DATA), + .DIB(B1DATA), + .DIC(B1DATA), + .DID(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + +module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 32'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [5:0] A1ADDR, A2ADDR, A3ADDR; + output A1DATA, A2DATA, A3DATA; + + input [5:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM64M #( + .INIT_A(INIT), + .INIT_B(INIT), + .INIT_C(INIT), + .INIT_D(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .ADDRA(A1ADDR), + .ADDRB(A2ADDR), + .ADDRC(A3ADDR), + .DOA(A1DATA), + .DOB(A2DATA), + .DOC(A3DATA), + + .ADDRD(B1ADDR), + .DIA(B1DATA), + .DIB(B1DATA), + .DIC(B1DATA), + .DID(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule From 037d1a03df20b9c445790728bb80e1818d1edafa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 17:49:55 -0800 Subject: [PATCH 11/46] Add #1460 testcase --- tests/arch/xilinx/bug1460.ys | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 tests/arch/xilinx/bug1460.ys diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys new file mode 100644 index 000000000..2018071cc --- /dev/null +++ b/tests/arch/xilinx/bug1460.ys @@ -0,0 +1,34 @@ +read_verilog < Date: Thu, 12 Dec 2019 18:52:03 -0800 Subject: [PATCH 12/46] Fix RAM64M model to have 6 bit address bus --- techlibs/xilinx/cells_sim.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3ed0759db..56eb782c6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1185,10 +1185,10 @@ module RAM64M ( output DOB, output DOC, output DOD, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, input DIA, input DIB, input DIC, From 8925bf4b9639e1604eb3fd9a298d9f1138093a56 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 18:52:28 -0800 Subject: [PATCH 13/46] Add RAM32X6SDP and RAM64X3SDP modes --- techlibs/xilinx/lutrams.txt | 40 ++++++++++++++++ techlibs/xilinx/lutrams_map.v | 88 +++++++++++++++++++++++++++++++---- 2 files changed, 120 insertions(+), 8 deletions(-) diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index 3e260b0d7..be764a63f 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -52,6 +52,32 @@ bram $__XILINX_RAM128X1D endbram +bram $__XILINX_RAM32X6SDP + init 1 + abits 5 + dbits 6 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X3SDP + init 1 + abits 6 + dbits 3 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM32M init 1 abits 5 @@ -108,6 +134,20 @@ match $__XILINX_RAM128X1D endmatch +match $__XILINX_RAM32X6SDP + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X3SDP + min bits 6 + min wports 1 + make_outreg + or_next_if_better +endmatch + match $__XILINX_RAM32M min bits 5 min rports 3 diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v index 985e53ff4..d01508de5 100644 --- a/techlibs/xilinx/lutrams_map.v +++ b/techlibs/xilinx/lutrams_map.v @@ -128,8 +128,80 @@ module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); endmodule +module \$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [32*6-1:0] INIT = {32*6{1'bx}}; + parameter CLKPOL2 = 1; + input CLK1; + + input [4:0] A1ADDR; + output [5:0] A1DATA; + + input [4:0] B1ADDR; + input [5:0] B1DATA; + input B1EN; + + RAM32M #( + .INIT_A({INIT[187:186], INIT[181:180], INIT[175:174], INIT[169:168], INIT[163:162], INIT[157:156], INIT[151:150], INIT[145:144], INIT[139:138], INIT[133:132], INIT[127:126], INIT[121:120], INIT[115:114], INIT[109:108], INIT[103:102], INIT[ 97: 96], INIT[ 91: 90], INIT[ 85: 84], INIT[ 79: 78], INIT[ 73: 72], INIT[ 67: 66], INIT[ 61: 60], INIT[ 55: 54], INIT[ 49: 48], INIT[ 43: 42], INIT[ 37: 36], INIT[ 31: 30], INIT[ 25: 24], INIT[ 19: 18], INIT[ 13: 12], INIT[ 7: 6], INIT[ 1: 0]}), + .INIT_B({INIT[189:188], INIT[183:182], INIT[177:176], INIT[171:170], INIT[165:164], INIT[159:158], INIT[153:152], INIT[147:146], INIT[141:140], INIT[135:134], INIT[129:128], INIT[123:122], INIT[117:116], INIT[111:110], INIT[105:104], INIT[ 99: 98], INIT[ 93: 92], INIT[ 87: 86], INIT[ 81: 80], INIT[ 75: 74], INIT[ 69: 68], INIT[ 63: 62], INIT[ 57: 56], INIT[ 51: 50], INIT[ 45: 44], INIT[ 39: 38], INIT[ 33: 32], INIT[ 27: 26], INIT[ 21: 20], INIT[ 15: 14], INIT[ 9: 8], INIT[ 3: 2]}), + .INIT_C({INIT[191:190], INIT[185:184], INIT[179:178], INIT[173:172], INIT[167:166], INIT[161:160], INIT[155:154], INIT[149:148], INIT[143:142], INIT[137:136], INIT[131:130], INIT[125:124], INIT[119:118], INIT[113:112], INIT[107:106], INIT[101:100], INIT[ 95: 94], INIT[ 89: 88], INIT[ 83: 82], INIT[ 77: 76], INIT[ 71: 70], INIT[ 65: 64], INIT[ 59: 58], INIT[ 53: 52], INIT[ 47: 46], INIT[ 41: 40], INIT[ 35: 34], INIT[ 29: 28], INIT[ 23: 22], INIT[ 17: 16], INIT[ 11: 10], INIT[ 5: 4]}), + .INIT_D(64'bx), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .ADDRA(A1ADDR), + .ADDRB(A1ADDR), + .ADDRC(A1ADDR), + .DOA(A1DATA[1:0]), + .DOB(A1DATA[3:2]), + .DOC(A1DATA[5:4]), + + .ADDRD(B1ADDR), + .DIA(B1DATA[1:0]), + .DIB(B1DATA[3:2]), + .DIC(B1DATA[5:4]), + .DID(), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + +module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [64*3-1:0] INIT = {64*3{1'bx}}; + parameter CLKPOL2 = 1; + input CLK1; + + input [5:0] A1ADDR; + output [2:0] A1DATA; + + input [5:0] B1ADDR; + input [2:0] B1DATA; + input B1EN; + + RAM64M #( + .INIT_A({INIT[189], INIT[186], INIT[183], INIT[180], INIT[177], INIT[174], INIT[171], INIT[168], INIT[165], INIT[162], INIT[159], INIT[156], INIT[153], INIT[150], INIT[147], INIT[144], INIT[141], INIT[138], INIT[135], INIT[132], INIT[129], INIT[126], INIT[123], INIT[120], INIT[117], INIT[114], INIT[111], INIT[108], INIT[105], INIT[102], INIT[ 99], INIT[ 96], INIT[ 93], INIT[ 90], INIT[ 87], INIT[ 84], INIT[ 81], INIT[ 78], INIT[ 75], INIT[ 72], INIT[ 69], INIT[ 66], INIT[ 63], INIT[ 60], INIT[ 57], INIT[ 54], INIT[ 51], INIT[ 48], INIT[ 45], INIT[ 42], INIT[ 39], INIT[ 36], INIT[ 33], INIT[ 30], INIT[ 27], INIT[ 24], INIT[ 21], INIT[ 18], INIT[ 15], INIT[ 12], INIT[ 9], INIT[ 6], INIT[ 3], INIT[ 0]}), + .INIT_B({INIT[190], INIT[187], INIT[184], INIT[181], INIT[178], INIT[175], INIT[172], INIT[169], INIT[166], INIT[163], INIT[160], INIT[157], INIT[154], INIT[151], INIT[148], INIT[145], INIT[142], INIT[139], INIT[136], INIT[133], INIT[130], INIT[127], INIT[124], INIT[121], INIT[118], INIT[115], INIT[112], INIT[109], INIT[106], INIT[103], INIT[100], INIT[ 97], INIT[ 94], INIT[ 91], INIT[ 88], INIT[ 85], INIT[ 82], INIT[ 79], INIT[ 76], INIT[ 73], INIT[ 70], INIT[ 67], INIT[ 64], INIT[ 61], INIT[ 58], INIT[ 55], INIT[ 52], INIT[ 49], INIT[ 46], INIT[ 43], INIT[ 40], INIT[ 37], INIT[ 34], INIT[ 31], INIT[ 28], INIT[ 25], INIT[ 22], INIT[ 19], INIT[ 16], INIT[ 13], INIT[ 10], INIT[ 7], INIT[ 4], INIT[ 1]}), + .INIT_C({INIT[191], INIT[188], INIT[185], INIT[182], INIT[179], INIT[176], INIT[173], INIT[170], INIT[167], INIT[164], INIT[161], INIT[158], INIT[155], INIT[152], INIT[149], INIT[146], INIT[143], INIT[140], INIT[137], INIT[134], INIT[131], INIT[128], INIT[125], INIT[122], INIT[119], INIT[116], INIT[113], INIT[110], INIT[107], INIT[104], INIT[101], INIT[ 98], INIT[ 95], INIT[ 92], INIT[ 89], INIT[ 86], INIT[ 83], INIT[ 80], INIT[ 77], INIT[ 74], INIT[ 71], INIT[ 68], INIT[ 65], INIT[ 62], INIT[ 59], INIT[ 56], INIT[ 53], INIT[ 50], INIT[ 47], INIT[ 44], INIT[ 41], INIT[ 38], INIT[ 35], INIT[ 32], INIT[ 29], INIT[ 26], INIT[ 23], INIT[ 20], INIT[ 17], INIT[ 14], INIT[ 11], INIT[ 8], INIT[ 5], INIT[ 2]}), + .INIT_D(64'bx), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .ADDRA(A1ADDR), + .ADDRB(A1ADDR), + .ADDRC(A1ADDR), + .DOA(A1DATA[0]), + .DOB(A1DATA[1]), + .DOC(A1DATA[2]), + + .ADDRD(B1ADDR), + .DIA(B1DATA[0]), + .DIB(B1DATA[1]), + .DIC(B1DATA[2]), + .DID(), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); - parameter [31:0] INIT = 32'bx; + parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; input CLK1; @@ -150,9 +222,9 @@ module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, .ADDRA(A1ADDR), .ADDRB(A2ADDR), .ADDRC(A3ADDR), - .DOA(A1DATA), - .DOB(A2DATA), - .DOC(A3DATA), + .DOA(A1DATA), + .DOB(A2DATA), + .DOC(A3DATA), .ADDRD(B1ADDR), .DIA(B1DATA), @@ -165,7 +237,7 @@ module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, endmodule module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); - parameter [63:0] INIT = 32'bx; + parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; input CLK1; @@ -186,9 +258,9 @@ module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, .ADDRA(A1ADDR), .ADDRB(A2ADDR), .ADDRC(A3ADDR), - .DOA(A1DATA), - .DOB(A2DATA), - .DOC(A3DATA), + .DOA(A1DATA), + .DOB(A2DATA), + .DOC(A3DATA), .ADDRD(B1ADDR), .DIA(B1DATA), From 01116f0f0a0ace0c676271904222932dd433aae1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 18:52:48 -0800 Subject: [PATCH 14/46] Add tests for these new models --- tests/arch/xilinx/lutram.ys | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 9b2c30ba1..36367eff1 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -97,3 +97,43 @@ select -assert-count 1 t:BUFG select -assert-count 24 t:FDRE select -assert-count 8 t:RAM64M select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 6 t:FDRE +select -assert-count 1 t:RAM32M +select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 6 t:FDRE +select -assert-count 2 t:RAM64M +select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D From d0ee4cd88f1f966c194fdc60e47ef67944882afb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 19:00:26 -0800 Subject: [PATCH 15/46] Remove extraneous synth_xilinx call --- tests/arch/xilinx/lutram.ys | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 36367eff1..a2ede75a5 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -62,7 +62,6 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r proc memory -nomap -synth_xilinx equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full @@ -83,7 +82,6 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r -chparam A_WIDTH 6 proc memory -nomap -synth_xilinx equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full From ce3615b3670b942ae281db425b290023b1395b69 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 13 Dec 2019 10:28:34 +0100 Subject: [PATCH 16/46] add periods and newlines to help message --- passes/cmds/scratchpad.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index c11c41caf..6bf14a6bd 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -34,15 +34,15 @@ struct ScratchpadPass : public Pass { log(" scratchpad [options]\n"); log("\n"); log("This pass allows to read and modify values from the scratchpad of the current\n"); - log("design. Options:\n"); + log("design. Options:\n\n"); log(" -get \n"); - log(" print the value saved in the scratchpad under the given identifier\n"); + log(" print the value saved in the scratchpad under the given identifier.\n\n"); log(" -set \n"); - log(" save the given value in the scratchpad under the given identifier\n"); + log(" save the given value in the scratchpad under the given identifier.\n\n"); log(" -unset \n"); - log(" remove the entry for the given identifier from the scratchpad\n"); + log(" remove the entry for the given identifier from the scratchpad.\n\n"); log(" -copy \n"); - log(" copy the value of the first identifier to the second identifier\n"); + log(" copy the value of the first identifier to the second identifier.\n\n"); log("The identifier may not contain whitespace. By convention, it is usually prefixed\n"); log("by the name of the pass that uses it, e.g. 'opt.did_something'. If the value\n"); log("contains whitespace, it must be enclosed in double quotes.\n"); From e9dc2759c414bdc8ab663fd5c8350b40b099b456 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Fri, 13 Dec 2019 10:17:05 -0300 Subject: [PATCH 17/46] Fixed some missing "verilog_" in documentation --- frontends/verilog/preproc.cc | 2 +- frontends/verilog/verilog_lexer.l | 2 +- manual/CHAPTER_Verilog.tex | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7e107dc26..161253a99 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -28,7 +28,7 @@ * * Ad-hoc implementation of a Verilog preprocessor. The directives `define, * `include, `ifdef, `ifndef, `else and `endif are handled here. All other - * directives are handled by the lexer (see lexer.l). + * directives are handled by the lexer (see verilog_lexer.l). * */ diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index c8984c2c4..ca23df3e8 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -28,7 +28,7 @@ * * A simple lexer for Verilog code. Non-preprocessor compiler directives are * handled here. The preprocessor stuff is handled in preproc.cc. Everything - * else is left to the bison parser (see parser.y). + * else is left to the bison parser (see verilog_parser.y). * */ diff --git a/manual/CHAPTER_Verilog.tex b/manual/CHAPTER_Verilog.tex index e9ca6114e..d4cc55647 100644 --- a/manual/CHAPTER_Verilog.tex +++ b/manual/CHAPTER_Verilog.tex @@ -93,7 +93,7 @@ frontends/verilog/preproc.cc} in the Yosys source tree. \begin{sloppypar} The Verilog Lexer is written using the lexer generator {\it flex} \citeweblink{flex}. Its source code -can be found in {\tt frontends/verilog/lexer.l} in the Yosys source tree. +can be found in {\tt frontends/verilog/verilog\_lexer.l} in the Yosys source tree. The lexer does little more than identifying all keywords and literals recognised by the Yosys Verilog frontend. \end{sloppypar} @@ -115,7 +115,7 @@ whenever possible.) \subsection{The Verilog Parser} The Verilog Parser is written using the parser generator {\it bison} \citeweblink{bison}. Its source code -can be found in {\tt frontends/verilog/parser.y} in the Yosys source tree. +can be found in {\tt frontends/verilog/verilog\_parser.y} in the Yosys source tree. It generates an AST using the \lstinline[language=C++]{AST::AstNode} data structure defined in {\tt frontends/ast/ast.h}. An \lstinline[language=C++]{AST::AstNode} object has From 1c9634558747bf5b92a309b6af013a54034c35d3 Mon Sep 17 00:00:00 2001 From: Diego H Date: Fri, 13 Dec 2019 09:33:18 -0600 Subject: [PATCH 18/46] Renaming BRAM memory tests for the sake of uniformity --- .../common/{memory_params.v => blockram_params.v} | 0 .../xilinx/{memory_params.ys => blockram_params.ys} | 12 ++++++------ 2 files changed, 6 insertions(+), 6 deletions(-) rename tests/arch/common/{memory_params.v => blockram_params.v} (100%) rename tests/arch/xilinx/{memory_params.ys => blockram_params.ys} (84%) diff --git a/tests/arch/common/memory_params.v b/tests/arch/common/blockram_params.v similarity index 100% rename from tests/arch/common/memory_params.v rename to tests/arch/common/blockram_params.v diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/blockram_params.ys similarity index 84% rename from tests/arch/xilinx/memory_params.ys rename to tests/arch/xilinx/blockram_params.ys index c1b0ca489..27a94834e 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/blockram_params.ys @@ -1,28 +1,28 @@ ## TODO: Not running equivalence checking because BRAM models does not exists ## currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp @@ -30,7 +30,7 @@ select -assert-count 1 t:RAMB18E1 # Anything memory bits < 1024 -> LUTRAM design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp @@ -39,7 +39,7 @@ select -assert-count 4 t:RAM128X1D # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp From d6514fc2e13976b15be396f413b046deb6f0c9fa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 08:54:19 -0800 Subject: [PATCH 19/46] RAM64M8 to also have [5:0] for address --- techlibs/xilinx/cells_sim.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 56eb782c6..f9ce496ff 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1230,14 +1230,14 @@ module RAM64M8 ( output DOF, output DOG, output DOH, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, - input [4:0] ADDRE, - input [4:0] ADDRF, - input [4:0] ADDRG, - input [4:0] ADDRH, + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, + input [5:0] ADDRE, + input [5:0] ADDRF, + input [5:0] ADDRG, + input [5:0] ADDRH, input DIA, input DIB, input DIC, From c3262d60752bb20ff5cd54bc4ee6f56e2b772b05 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 08:59:17 -0800 Subject: [PATCH 20/46] Disable RAM16X1D match rule; carry-over from LUT4 arches --- techlibs/xilinx/lutrams.txt | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index be764a63f..ae629bce8 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -105,12 +105,15 @@ bram $__XILINX_RAM64M endbram -match $__XILINX_RAM16X1D - min bits 2 - min wports 1 - make_outreg - or_next_if_better -endmatch +# Disabled for now, pending support for LUT4 arches +# since on LUT6 arches this occupies same area as +# a RAM32X1D +#match $__XILINX_RAM16X1D +# min bits 2 +# min wports 1 +# make_outreg +# or_next_if_better +#endmatch match $__XILINX_RAM32X1D min bits 3 From a5764a12365073768edb822e893aa9c0a957e585 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 10:28:13 -0800 Subject: [PATCH 21/46] Disable RAM16X1D test --- tests/arch/xilinx/lutram.ys | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index a2ede75a5..6c9d1eae1 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -1,20 +1,20 @@ -read_verilog ../common/lutram.v -hierarchy -top lutram_1w1r -chparam A_WIDTH 4 -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd lutram_1w1r -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM16X1D -select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D +#read_verilog ../common/lutram.v +#hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +#proc +#memory -nomap +#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#memory +#opt -full +# +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter +# +#design -load postopt +#cd lutram_1w1r +#select -assert-count 1 t:BUFG +#select -assert-count 8 t:FDRE +#select -assert-count 8 t:RAM16X1D +#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D design -reset From 266993408a2b926ffefcf536feb92b36b11e398e Mon Sep 17 00:00:00 2001 From: Diego H Date: Fri, 13 Dec 2019 15:43:24 -0600 Subject: [PATCH 22/46] Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific --- passes/memory/memory_bram.cc | 77 +++++++++++++++++++++++++++++++ techlibs/xilinx/xc7_xcu_brams.txt | 19 ++++++++ 2 files changed, 96 insertions(+) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index aa8f94149..35cd0647a 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -327,6 +327,20 @@ struct rules_t continue; } + if (GetSize(tokens) >= 2 && tokens[0] == "attribute") { + for (int idx=1; idx<= GetSize(tokens)-1; idx++) { + size_t val = tokens[idx].find_first_of("!="); + if (val != std::string::npos) { + if (val == 0) { + data.attr_unmatch[RTLIL::escape_id(tokens[idx].substr(val+1))]; + } + else { + data.attr_match[RTLIL::escape_id(tokens[idx].substr(0, val))] = tokens[idx].substr(val+1); + } + } + } + continue; + } syntax_error(); } } @@ -813,6 +827,27 @@ grow_read_ports:; return false; } + if (!match.attr_match.empty()) { + for (auto iter: match.attr_match) { + auto it = cell->attributes.find(iter.first); + + if (iter.second.empty()) { + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), iter.first.c_str(), iter.second.decode_string().c_str()); + return false; + } + + if (it != cell->attributes.end()) { + if (it->second == iter.second) + continue; + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), iter.first.c_str(), iter.second.decode_string().c_str()); + return false; + } + continue; + } + } + if (mode == 1) return true; } @@ -997,6 +1032,7 @@ void handle_cell(Cell *cell, const rules_t &rules) log("Processing %s.%s:\n", log_id(cell->module), log_id(cell)); bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef(); + int access = 0; dict match_properties; match_properties["words"] = cell->getParam("\\SIZE").as_int(); @@ -1100,6 +1136,42 @@ void handle_cell(Cell *cell, const rules_t &rules) goto next_match_rule; } + for (auto iter: match.attr_unmatch) { + auto it = cell->attributes.find(iter.first); + + if (it != cell->attributes.end()) { + log(" Rule for bram type %s is rejected: requirement 'attribute %s' is met.\n", + log_id(match.name), iter.first.c_str()); + goto next_match_rule; + } + continue; + } + + if (!match.attr_match.empty()) { + for (auto iter: match.attr_match) { + int len=std::tuple_size::value; + auto it = cell->attributes.find(iter.first); + + if (iter.second.empty()) { + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), iter.first.c_str(), iter.second.decode_string().c_str()); + continue; + } + + if (it != cell->attributes.end()) { + if (it->second == iter.second) + continue; + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), iter.first.c_str(), iter.second.decode_string().c_str()); + } + access ++; + if (access == len) { + access = 0; + goto next_match_rule; + } + } + } + log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, log_id(bram.name), bram.variant); if (or_next_if_better || !best_rule_cache.empty()) @@ -1225,6 +1297,11 @@ struct MemoryBramPass : public Pass { log(" dcells ....... number of cells in 'data-direction'\n"); log(" cells ........ total number of cells (acells*dcells*dups)\n"); log("\n"); + log("A match containing the condition 'attribute' followed by a name and optional\n"); + log("value requires that the memory contains the given attribute name and value\n"); + log("(if specified) or that the attribute is not present (prepending a '!')\n"); + log("or the value is empty (if value is not specified\n)."); + log("\n"); log("The interface for the created bram instances is derived from the bram\n"); log("description. Use 'techmap' to convert the created bram instances into\n"); log("instances of the actual bram cells of your target architecture.\n"); diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index b7c893ff7..a52dd9352 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -81,6 +81,7 @@ match $__XILINX_RAMB36_SDP min efficiency 5 shuffle_enable B make_transp + attribute !ram_style !logic_block or_next_if_better endmatch @@ -89,6 +90,14 @@ match $__XILINX_RAMB18_SDP min efficiency 5 shuffle_enable B make_transp + attribute !ram_style !logic_block + or_next_if_better +endmatch + +match $__XILINX_RAMB18_SDP + shuffle_enable B + make_transp + attribute ram_block=1 ram_style=block or_next_if_better endmatch @@ -97,6 +106,7 @@ match $__XILINX_RAMB36_TDP min efficiency 5 shuffle_enable B make_transp + attribute !ram_style !logic_block or_next_if_better endmatch @@ -105,4 +115,13 @@ match $__XILINX_RAMB18_TDP min efficiency 5 shuffle_enable B make_transp + attribute !ram_style !logic_block + or_next_if_better +endmatch + +match $__XILINX_RAMB18_TDP + min efficiency 5 + shuffle_enable B + make_transp + attribute ram_block=1 ram_style=block endmatch From e709fd3da1c7e3ae36ee43a997fbd413909c764e Mon Sep 17 00:00:00 2001 From: Alyssa Milburn Date: Sun, 15 Dec 2019 20:40:38 +0100 Subject: [PATCH 23/46] Fix opt_expr.eqneq.cmpzero debug print --- passes/opt/opt_expr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 6cf66fb95..4a2f170b8 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -978,7 +978,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell), - log_id(module), "$eq" ? "$logic_not" : "$reduce_bool"); + log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool"); cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool); if (assign_map(cell->getPort(ID::A)).is_fully_zero()) { cell->setPort(ID::A, cell->getPort(ID::B)); From b35559fc335181d7c8f8046fa17bf05550c21ba7 Mon Sep 17 00:00:00 2001 From: Diego H Date: Sun, 15 Dec 2019 23:33:09 -0600 Subject: [PATCH 24/46] Merging attribute rules into a single match block; Adding tests --- passes/memory/memory_bram.cc | 148 +- techlibs/xilinx/xc7_xcu_brams.txt | 30 +- .../memory_attributes/attributes_test.v | 88 + .../memory_attributes/attributes_test.ys | 47 + tests/arch/common/memory_attributes/log | 3238 +++++++++++++++++ 5 files changed, 3465 insertions(+), 86 deletions(-) create mode 100644 tests/arch/common/memory_attributes/attributes_test.v create mode 100644 tests/arch/common/memory_attributes/attributes_test.ys create mode 100644 tests/arch/common/memory_attributes/log diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 35cd0647a..10b48e321 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -134,6 +134,9 @@ struct rules_t dict min_limits, max_limits; bool or_next_if_better, make_transp, make_outreg; char shuffle_enable; + dict>> attr_match; + pair attr_val; + dict attr_unmatch; }; dict> brams; @@ -328,19 +331,31 @@ struct rules_t } if (GetSize(tokens) >= 2 && tokens[0] == "attribute") { - for (int idx=1; idx<= GetSize(tokens)-1; idx++) { - size_t val = tokens[idx].find_first_of("!="); - if (val != std::string::npos) { - if (val == 0) { - data.attr_unmatch[RTLIL::escape_id(tokens[idx].substr(val+1))]; - } - else { - data.attr_match[RTLIL::escape_id(tokens[idx].substr(0, val))] = tokens[idx].substr(val+1); + if (GetSize(tokens) <=2) { + size_t notval = tokens[1].find("!"); + size_t val = tokens[1].find("="); + + if (notval != std::string::npos) { + if (val != std::string::npos) + data.attr_unmatch[RTLIL::escape_id(tokens[1].substr(1, val-1))] = tokens[1].substr(val+1); + else + data.attr_unmatch[RTLIL::escape_id(tokens[1].substr(notval+1))] = RTLIL::Const('1'); + } + continue; + } + + else if (GetSize(tokens) > 2) { + for (int idx=1; idx<= GetSize(tokens)-1; idx++) { + size_t val = tokens[idx].find("="); + if (val != std::string::npos) { + data.attr_val = make_pair(RTLIL::escape_id(tokens[idx].substr(0, val)), tokens[idx].substr(val+1)); + data.attr_match[RTLIL::escape_id(tokens[0])].push_back(data.attr_val); } } + continue; } - continue; } + syntax_error(); } } @@ -738,7 +753,7 @@ grow_read_ports:; if (match.make_transp && wr_ports <= 1) { pi.make_transp = true; if (pi.clocks != 0) { - if (wr_ports == 1 && wr_clkdom != clkdom) { + if (wr_ports == 1 && wr_clkdom != clkdom) { log(" Bram port %c%d.%d cannot have soft transparency logic added as read and write clock domains differ.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1); goto skip_bram_rport; } @@ -806,6 +821,27 @@ grow_read_ports:; log(" Updated properties: dups=%d waste=%d efficiency=%d\n", match_properties["dups"], match_properties["waste"], match_properties["efficiency"]); + for (auto& iter: match.attr_match) { + for (auto& iter: iter.second) { + auto it = cell->attributes.find(iter.first); + + if (iter.second.empty()) { + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); + return false; + } + + if (it != cell->attributes.end()) { + if (it->second == iter.second) + continue; + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); + return false; + } + return true; + } + } + for (auto it : match.min_limits) { if (!match_properties.count(it.first)) log_error("Unknown property '%s' in match rule for bram type %s.\n", @@ -827,27 +863,6 @@ grow_read_ports:; return false; } - if (!match.attr_match.empty()) { - for (auto iter: match.attr_match) { - auto it = cell->attributes.find(iter.first); - - if (iter.second.empty()) { - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), iter.first.c_str(), iter.second.decode_string().c_str()); - return false; - } - - if (it != cell->attributes.end()) { - if (it->second == iter.second) - continue; - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), iter.first.c_str(), iter.second.decode_string().c_str()); - return false; - } - continue; - } - } - if (mode == 1) return true; } @@ -1032,7 +1047,6 @@ void handle_cell(Cell *cell, const rules_t &rules) log("Processing %s.%s:\n", log_id(cell->module), log_id(cell)); bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef(); - int access = 0; dict match_properties; match_properties["words"] = cell->getParam("\\SIZE").as_int(); @@ -1110,6 +1124,39 @@ void handle_cell(Cell *cell, const rules_t &rules) goto next_match_rule; } + for (auto& iter: match.attr_match) { + for (auto& iter: iter.second) { + auto it = cell->attributes.find(iter.first); + + if (it != cell->attributes.end()) { + if (!it->second.empty()) { + if (it->second.decode_string().length() == 1) + it->second = it->second.as_string().back(); + if (!it->second.decode_string().compare(iter.second.decode_string())) + goto attribute_matched; + else + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); + } + } + } + } + + for (auto& iter: match.attr_unmatch) { + auto it = cell->attributes.find(iter.first); + + if (it != cell->attributes.end()) { + if (!it->second.empty()) { + if (it->second.decode_string().length() == 1) + it->second = it->second.as_string().back(); + if (!it->second.decode_string().compare(iter.second.decode_string())) + goto next_match_rule; + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); + } + } + } + for (auto it : match.min_limits) { if (it.first == "waste" || it.first == "dups" || it.first == "acells" || it.first == "dcells" || it.first == "cells") continue; @@ -1136,42 +1183,7 @@ void handle_cell(Cell *cell, const rules_t &rules) goto next_match_rule; } - for (auto iter: match.attr_unmatch) { - auto it = cell->attributes.find(iter.first); - - if (it != cell->attributes.end()) { - log(" Rule for bram type %s is rejected: requirement 'attribute %s' is met.\n", - log_id(match.name), iter.first.c_str()); - goto next_match_rule; - } - continue; - } - - if (!match.attr_match.empty()) { - for (auto iter: match.attr_match) { - int len=std::tuple_size::value; - auto it = cell->attributes.find(iter.first); - - if (iter.second.empty()) { - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), iter.first.c_str(), iter.second.decode_string().c_str()); - continue; - } - - if (it != cell->attributes.end()) { - if (it->second == iter.second) - continue; - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), iter.first.c_str(), iter.second.decode_string().c_str()); - } - access ++; - if (access == len) { - access = 0; - goto next_match_rule; - } - } - } - + attribute_matched: log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, log_id(bram.name), bram.variant); if (or_next_if_better || !best_rule_cache.empty()) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index a52dd9352..2d94ac4a8 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -77,51 +77,45 @@ endbram # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf match $__XILINX_RAMB36_SDP + attribute ram_style=block ram_block=1 + attribute !ram_style=distributed + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp - attribute !ram_style !logic_block or_next_if_better endmatch match $__XILINX_RAMB18_SDP + attribute ram_style=block ram_block=1 + attribute !ram_style=distributed + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp - attribute !ram_style !logic_block - or_next_if_better -endmatch - -match $__XILINX_RAMB18_SDP - shuffle_enable B - make_transp - attribute ram_block=1 ram_style=block or_next_if_better endmatch match $__XILINX_RAMB36_TDP + attribute ram_style=block ram_block=1 + attribute !ram_style=distributed + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp - attribute !ram_style !logic_block or_next_if_better endmatch match $__XILINX_RAMB18_TDP + attribute ram_style=block ram_block=1 + attribute !ram_style=distributed + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp - attribute !ram_style !logic_block - or_next_if_better endmatch -match $__XILINX_RAMB18_TDP - min efficiency 5 - shuffle_enable B - make_transp - attribute ram_block=1 ram_style=block -endmatch diff --git a/tests/arch/common/memory_attributes/attributes_test.v b/tests/arch/common/memory_attributes/attributes_test.v new file mode 100644 index 000000000..275800dd0 --- /dev/null +++ b/tests/arch/common/memory_attributes/attributes_test.v @@ -0,0 +1,88 @@ +`default_nettype none +module block_ram #(parameter DATA_WIDTH=4, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // block_ram + +`default_nettype none +module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + +`default_nettype none +module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + (* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + +`default_nettype none +module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + (* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + diff --git a/tests/arch/common/memory_attributes/attributes_test.ys b/tests/arch/common/memory_attributes/attributes_test.ys new file mode 100644 index 000000000..4e06a35e7 --- /dev/null +++ b/tests/arch/common/memory_attributes/attributes_test.ys @@ -0,0 +1,47 @@ +# Check that blockram memory without parameters is not modified +read_verilog attributes_test.v +hierarchy -top block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Check that distributed memory without parameters is not modified +design -reset +read_verilog attributes_test.v +hierarchy -top distributed_ram +synth_xilinx -top distributed_ram +cd distributed_ram # Constrain all select calls below inside the top module +select -assert-count 8 t:RAM32X1D + +# Set ram_style distributed to blockram memory; will be implemented as distributed +design -reset +read_verilog attributes_test.v +prep +setattr -mod -set ram_style "distributed" block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 32 t:RAM128X1D + +# Set synthesis, logic_block to blockram memory; will be implemented as distributed +design -reset +read_verilog attributes_test.v +prep +setattr -mod -set logic_block 1 block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 0 t:RAMB18E1 +select -assert-count 32 t:RAM128X1D + +# Set ram_style block to a distributed memory; will be implemented as blockram +design -reset +read_verilog attributes_test.v +synth_xilinx -top distributed_ram_manual +cd distributed_ram_manual # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram +design -reset +read_verilog attributes_test.v +synth_xilinx -top distributed_ram_manual_syn +cd distributed_ram_manual_syn # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/common/memory_attributes/log b/tests/arch/common/memory_attributes/log new file mode 100644 index 000000000..5d526e661 --- /dev/null +++ b/tests/arch/common/memory_attributes/log @@ -0,0 +1,3238 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2019 Clifford Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.9+932 (git sha1 26699340, clang 6.0.0-1ubuntu2 -fPIC -Os) + + +-- Executing script file `attributes_test.ys' -- + +1. Executing Verilog-2005 frontend: attributes_test.v +Parsing Verilog input from `attributes_test.v' to AST representation. +Generating RTLIL representation for module `\block_ram'. +Generating RTLIL representation for module `\distributed_ram'. +Generating RTLIL representation for module `\distributed_ram_manual'. +Generating RTLIL representation for module `\distributed_ram_manual_syn'. +Successfully finished Verilog frontend. + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. +Top module: \block_ram + +2.2. Analyzing design hierarchy.. +Top module: \block_ram +Removing unused module `\distributed_ram_manual_syn'. +Removing unused module `\distributed_ram_manual'. +Removing unused module `\distributed_ram'. +Removed 3 unused modules. + +3. Executing SYNTH_XILINX pass. + +3.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\VCC'. +Generating RTLIL representation for module `\GND'. +Generating RTLIL representation for module `\IBUF'. +Generating RTLIL representation for module `\IBUFG'. +Generating RTLIL representation for module `\OBUF'. +Generating RTLIL representation for module `\IOBUF'. +Generating RTLIL representation for module `\OBUFT'. +Generating RTLIL representation for module `\BUFG'. +Generating RTLIL representation for module `\BUFGCTRL'. +Generating RTLIL representation for module `\BUFHCE'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\LUT6_2'. +Generating RTLIL representation for module `\MUXCY'. +Generating RTLIL representation for module `\MUXF7'. +Generating RTLIL representation for module `\MUXF8'. +Generating RTLIL representation for module `\XORCY'. +Generating RTLIL representation for module `\CARRY4'. +Generating RTLIL representation for module `\FDRE'. +Generating RTLIL representation for module `\FDSE'. +Generating RTLIL representation for module `\FDCE'. +Generating RTLIL representation for module `\FDPE'. +Generating RTLIL representation for module `\FDRE_1'. +Generating RTLIL representation for module `\FDSE_1'. +Generating RTLIL representation for module `\FDCE_1'. +Generating RTLIL representation for module `\FDPE_1'. +Generating RTLIL representation for module `\LDCE'. +Generating RTLIL representation for module `\LDPE'. +Generating RTLIL representation for module `\RAM16X1S'. +Generating RTLIL representation for module `\RAM16X1S_1'. +Generating RTLIL representation for module `\RAM32X1S'. +Generating RTLIL representation for module `\RAM32X1S_1'. +Generating RTLIL representation for module `\RAM64X1S'. +Generating RTLIL representation for module `\RAM64X1S_1'. +Generating RTLIL representation for module `\RAM128X1S'. +Generating RTLIL representation for module `\RAM128X1S_1'. +Generating RTLIL representation for module `\RAM256X1S'. +Generating RTLIL representation for module `\RAM512X1S'. +Generating RTLIL representation for module `\RAM16X2S'. +Generating RTLIL representation for module `\RAM32X2S'. +Generating RTLIL representation for module `\RAM64X2S'. +Generating RTLIL representation for module `\RAM16X4S'. +Generating RTLIL representation for module `\RAM32X4S'. +Generating RTLIL representation for module `\RAM16X8S'. +Generating RTLIL representation for module `\RAM32X8S'. +Generating RTLIL representation for module `\RAM16X1D'. +Generating RTLIL representation for module `\RAM16X1D_1'. +Generating RTLIL representation for module `\RAM32X1D'. +Generating RTLIL representation for module `\RAM32X1D_1'. +Generating RTLIL representation for module `\RAM64X1D'. +Generating RTLIL representation for module `\RAM64X1D_1'. +Generating RTLIL representation for module `\RAM128X1D'. +Generating RTLIL representation for module `\RAM256X1D'. +Generating RTLIL representation for module `\RAM32M'. +Generating RTLIL representation for module `\RAM32M16'. +Generating RTLIL representation for module `\RAM64M'. +Generating RTLIL representation for module `\RAM64M8'. +Generating RTLIL representation for module `\ROM16X1'. +Generating RTLIL representation for module `\ROM32X1'. +Generating RTLIL representation for module `\ROM64X1'. +Generating RTLIL representation for module `\ROM128X1'. +Generating RTLIL representation for module `\ROM256X1'. +Generating RTLIL representation for module `\SRL16E'. +Generating RTLIL representation for module `\SRLC16E'. +Generating RTLIL representation for module `\SRLC32E'. +Generating RTLIL representation for module `\MULT18X18'. +Generating RTLIL representation for module `\MULT18X18S'. +Generating RTLIL representation for module `\MULT18X18SIO'. +Generating RTLIL representation for module `\DSP48A'. +Generating RTLIL representation for module `\DSP48A1'. +Generating RTLIL representation for module `\DSP48E1'. +Successfully finished Verilog frontend. + +3.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. +Generating RTLIL representation for module `\FDCPE'. +Generating RTLIL representation for module `\FDRSE'. +Generating RTLIL representation for module `\LDCPE'. +Generating RTLIL representation for module `\AND2B1L'. +Generating RTLIL representation for module `\OR2L'. +Generating RTLIL representation for module `\MUXF5'. +Generating RTLIL representation for module `\MUXF6'. +Generating RTLIL representation for module `\MUXF9'. +Generating RTLIL representation for module `\CARRY8'. +Generating RTLIL representation for module `\ORCY'. +Generating RTLIL representation for module `\MULT_AND'. +Generating RTLIL representation for module `\SRL16'. +Generating RTLIL representation for module `\SRLC16'. +Generating RTLIL representation for module `\CFGLUT5'. +Generating RTLIL representation for module `\RAMB16_S1'. +Generating RTLIL representation for module `\RAMB16_S2'. +Generating RTLIL representation for module `\RAMB16_S4'. +Generating RTLIL representation for module `\RAMB16_S9'. +Generating RTLIL representation for module `\RAMB16_S18'. +Generating RTLIL representation for module `\RAMB16_S36'. +Generating RTLIL representation for module `\RAMB16_S1_S1'. +Generating RTLIL representation for module `\RAMB16_S1_S2'. +Generating RTLIL representation for module `\RAMB16_S1_S4'. +Generating RTLIL representation for module `\RAMB16_S1_S9'. +Generating RTLIL representation for module `\RAMB16_S1_S18'. +Generating RTLIL representation for module `\RAMB16_S1_S36'. +Generating RTLIL representation for module `\RAMB16_S2_S2'. +Generating RTLIL representation for module `\RAMB16_S2_S4'. +Generating RTLIL representation for module `\RAMB16_S2_S9'. +Generating RTLIL representation for module `\RAMB16_S2_S18'. +Generating RTLIL representation for module `\RAMB16_S2_S36'. +Generating RTLIL representation for module `\RAMB16_S4_S4'. +Generating RTLIL representation for module `\RAMB16_S4_S9'. +Generating RTLIL representation for module `\RAMB16_S4_S18'. +Generating RTLIL representation for module `\RAMB16_S4_S36'. +Generating RTLIL representation for module `\RAMB16_S9_S9'. +Generating RTLIL representation for module `\RAMB16_S9_S18'. +Generating RTLIL representation for module `\RAMB16_S9_S36'. +Generating RTLIL representation for module `\RAMB16_S18_S18'. +Generating RTLIL representation for module `\RAMB16_S18_S36'. +Generating RTLIL representation for module `\RAMB16_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWER'. +Generating RTLIL representation for module `\RAMB8BWER'. +Generating RTLIL representation for module `\FIFO16'. +Generating RTLIL representation for module `\RAMB16'. +Generating RTLIL representation for module `\RAMB32_S64_ECC'. +Generating RTLIL representation for module `\FIFO18'. +Generating RTLIL representation for module `\FIFO18_36'. +Generating RTLIL representation for module `\FIFO36'. +Generating RTLIL representation for module `\FIFO36_72'. +Generating RTLIL representation for module `\RAMB18'. +Generating RTLIL representation for module `\RAMB36'. +Generating RTLIL representation for module `\RAMB18SDP'. +Generating RTLIL representation for module `\RAMB36SDP'. +Generating RTLIL representation for module `\FIFO18E1'. +Generating RTLIL representation for module `\FIFO36E1'. +Generating RTLIL representation for module `\RAMB18E1'. +Generating RTLIL representation for module `\RAMB36E1'. +Generating RTLIL representation for module `\FIFO18E2'. +Generating RTLIL representation for module `\FIFO36E2'. +Generating RTLIL representation for module `\RAMB18E2'. +Generating RTLIL representation for module `\RAMB36E2'. +Generating RTLIL representation for module `\URAM288'. +Generating RTLIL representation for module `\URAM288_BASE'. +Generating RTLIL representation for module `\DSP48'. +Generating RTLIL representation for module `\DSP48E'. +Generating RTLIL representation for module `\DSP48E2'. +Generating RTLIL representation for module `\IFDDRCPE'. +Generating RTLIL representation for module `\IFDDRRSE'. +Generating RTLIL representation for module `\OFDDRCPE'. +Generating RTLIL representation for module `\OFDDRRSE'. +Generating RTLIL representation for module `\OFDDRTCPE'. +Generating RTLIL representation for module `\OFDDRTRSE'. +Generating RTLIL representation for module `\IDDR2'. +Generating RTLIL representation for module `\ODDR2'. +Generating RTLIL representation for module `\IDDR'. +Generating RTLIL representation for module `\IDDR_2CLK'. +Generating RTLIL representation for module `\ODDR'. +Generating RTLIL representation for module `\IDELAYCTRL'. +Generating RTLIL representation for module `\IDELAY'. +Generating RTLIL representation for module `\ISERDES'. +Generating RTLIL representation for module `\OSERDES'. +Generating RTLIL representation for module `\IODELAY'. +Generating RTLIL representation for module `\ISERDES_NODELAY'. +Generating RTLIL representation for module `\IODELAYE1'. +Generating RTLIL representation for module `\ISERDESE1'. +Generating RTLIL representation for module `\OSERDESE1'. +Generating RTLIL representation for module `\IDELAYE2'. +Generating RTLIL representation for module `\ODELAYE2'. +Generating RTLIL representation for module `\ISERDESE2'. +Generating RTLIL representation for module `\OSERDESE2'. +Generating RTLIL representation for module `\PHASER_IN'. +Generating RTLIL representation for module `\PHASER_IN_PHY'. +Generating RTLIL representation for module `\PHASER_OUT'. +Generating RTLIL representation for module `\PHASER_OUT_PHY'. +Generating RTLIL representation for module `\PHASER_REF'. +Generating RTLIL representation for module `\PHY_CONTROL'. +Generating RTLIL representation for module `\IDDRE1'. +Generating RTLIL representation for module `\ODDRE1'. +Generating RTLIL representation for module `\IDELAYE3'. +Generating RTLIL representation for module `\ODELAYE3'. +Generating RTLIL representation for module `\ISERDESE3'. +Generating RTLIL representation for module `\OSERDESE3'. +Generating RTLIL representation for module `\BITSLICE_CONTROL'. +Generating RTLIL representation for module `\RIU_OR'. +Generating RTLIL representation for module `\RX_BITSLICE'. +Generating RTLIL representation for module `\RXTX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE_TRI'. +Generating RTLIL representation for module `\IODELAY2'. +Generating RTLIL representation for module `\IODRP2'. +Generating RTLIL representation for module `\IODRP2_MCB'. +Generating RTLIL representation for module `\ISERDES2'. +Generating RTLIL representation for module `\OSERDES2'. +Generating RTLIL representation for module `\IBUF_DLY_ADJ'. +Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUF_ANALOG'. +Generating RTLIL representation for module `\IBUFE3'. +Generating RTLIL representation for module `\IBUFDS'. +Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. +Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDSE3'. +Generating RTLIL representation for module `\IBUFDS_DPHY'. +Generating RTLIL representation for module `\IBUFGDS'. +Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUF_DCIEN'. +Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFE3'. +Generating RTLIL representation for module `\IOBUFDS'. +Generating RTLIL representation for module `\IOBUFDS_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDSE3'. +Generating RTLIL representation for module `\OBUFDS'. +Generating RTLIL representation for module `\OBUFDS_DPHY'. +Generating RTLIL representation for module `\OBUFTDS'. +Generating RTLIL representation for module `\KEEPER'. +Generating RTLIL representation for module `\PULLDOWN'. +Generating RTLIL representation for module `\PULLUP'. +Generating RTLIL representation for module `\DCIRESET'. +Generating RTLIL representation for module `\HPIO_VREF'. +Generating RTLIL representation for module `\BUFGCE'. +Generating RTLIL representation for module `\BUFGCE_1'. +Generating RTLIL representation for module `\BUFGMUX'. +Generating RTLIL representation for module `\BUFGMUX_1'. +Generating RTLIL representation for module `\BUFGMUX_CTRL'. +Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. +Generating RTLIL representation for module `\BUFG_GT'. +Generating RTLIL representation for module `\BUFG_GT_SYNC'. +Generating RTLIL representation for module `\BUFG_PS'. +Generating RTLIL representation for module `\BUFGCE_DIV'. +Generating RTLIL representation for module `\BUFH'. +Generating RTLIL representation for module `\BUFIO2'. +Generating RTLIL representation for module `\BUFIO2_2CLK'. +Generating RTLIL representation for module `\BUFIO2FB'. +Generating RTLIL representation for module `\BUFPLL'. +Generating RTLIL representation for module `\BUFPLL_MCB'. +Generating RTLIL representation for module `\BUFIO'. +Generating RTLIL representation for module `\BUFIODQS'. +Generating RTLIL representation for module `\BUFR'. +Generating RTLIL representation for module `\BUFMR'. +Generating RTLIL representation for module `\BUFMRCE'. +Generating RTLIL representation for module `\DCM'. +Generating RTLIL representation for module `\DCM_SP'. +Generating RTLIL representation for module `\DCM_CLKGEN'. +Generating RTLIL representation for module `\DCM_ADV'. +Generating RTLIL representation for module `\DCM_BASE'. +Generating RTLIL representation for module `\DCM_PS'. +Generating RTLIL representation for module `\PMCD'. +Generating RTLIL representation for module `\PLL_ADV'. +Generating RTLIL representation for module `\PLL_BASE'. +Generating RTLIL representation for module `\MMCM_ADV'. +Generating RTLIL representation for module `\MMCM_BASE'. +Generating RTLIL representation for module `\MMCME2_ADV'. +Generating RTLIL representation for module `\MMCME2_BASE'. +Generating RTLIL representation for module `\PLLE2_ADV'. +Generating RTLIL representation for module `\PLLE2_BASE'. +Generating RTLIL representation for module `\MMCME3_ADV'. +Generating RTLIL representation for module `\MMCME3_BASE'. +Generating RTLIL representation for module `\PLLE3_ADV'. +Generating RTLIL representation for module `\PLLE3_BASE'. +Generating RTLIL representation for module `\MMCME4_ADV'. +Generating RTLIL representation for module `\MMCME4_BASE'. +Generating RTLIL representation for module `\PLLE4_ADV'. +Generating RTLIL representation for module `\PLLE4_BASE'. +Generating RTLIL representation for module `\BUFT'. +Generating RTLIL representation for module `\IN_FIFO'. +Generating RTLIL representation for module `\OUT_FIFO'. +Generating RTLIL representation for module `\HARD_SYNC'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. +Generating RTLIL representation for module `\STARTUP_SPARTAN6'. +Generating RTLIL representation for module `\STARTUP_VIRTEX4'. +Generating RTLIL representation for module `\STARTUP_VIRTEX5'. +Generating RTLIL representation for module `\STARTUP_VIRTEX6'. +Generating RTLIL representation for module `\STARTUPE2'. +Generating RTLIL representation for module `\STARTUPE3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. +Generating RTLIL representation for module `\CAPTUREE2'. +Generating RTLIL representation for module `\ICAP_SPARTAN3A'. +Generating RTLIL representation for module `\ICAP_SPARTAN6'. +Generating RTLIL representation for module `\ICAP_VIRTEX4'. +Generating RTLIL representation for module `\ICAP_VIRTEX5'. +Generating RTLIL representation for module `\ICAP_VIRTEX6'. +Generating RTLIL representation for module `\ICAPE2'. +Generating RTLIL representation for module `\ICAPE3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. +Generating RTLIL representation for module `\BSCAN_SPARTAN6'. +Generating RTLIL representation for module `\BSCAN_VIRTEX4'. +Generating RTLIL representation for module `\BSCAN_VIRTEX5'. +Generating RTLIL representation for module `\BSCAN_VIRTEX6'. +Generating RTLIL representation for module `\BSCANE2'. +Generating RTLIL representation for module `\DNA_PORT'. +Generating RTLIL representation for module `\DNA_PORTE2'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. +Generating RTLIL representation for module `\FRAME_ECCE2'. +Generating RTLIL representation for module `\FRAME_ECCE3'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. +Generating RTLIL representation for module `\USR_ACCESSE2'. +Generating RTLIL representation for module `\POST_CRC_INTERNAL'. +Generating RTLIL representation for module `\SUSPEND_SYNC'. +Generating RTLIL representation for module `\KEY_CLEAR'. +Generating RTLIL representation for module `\MASTER_JTAG'. +Generating RTLIL representation for module `\SPI_ACCESS'. +Generating RTLIL representation for module `\EFUSE_USR'. +Generating RTLIL representation for module `\SYSMON'. +Generating RTLIL representation for module `\XADC'. +Generating RTLIL representation for module `\SYSMONE1'. +Generating RTLIL representation for module `\SYSMONE4'. +Generating RTLIL representation for module `\GTPA1_DUAL'. +Generating RTLIL representation for module `\GT11_CUSTOM'. +Generating RTLIL representation for module `\GT11_DUAL'. +Generating RTLIL representation for module `\GT11CLK'. +Generating RTLIL representation for module `\GT11CLK_MGT'. +Generating RTLIL representation for module `\GTP_DUAL'. +Generating RTLIL representation for module `\GTX_DUAL'. +Generating RTLIL representation for module `\CRC32'. +Generating RTLIL representation for module `\CRC64'. +Generating RTLIL representation for module `\GTHE1_QUAD'. +Generating RTLIL representation for module `\GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTHE1'. +Generating RTLIL representation for module `\GTHE2_CHANNEL'. +Generating RTLIL representation for module `\GTHE2_COMMON'. +Generating RTLIL representation for module `\GTPE2_CHANNEL'. +Generating RTLIL representation for module `\GTPE2_COMMON'. +Generating RTLIL representation for module `\GTXE2_CHANNEL'. +Generating RTLIL representation for module `\GTXE2_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE2'. +Generating RTLIL representation for module `\GTHE3_CHANNEL'. +Generating RTLIL representation for module `\GTHE3_COMMON'. +Generating RTLIL representation for module `\GTHE4_CHANNEL'. +Generating RTLIL representation for module `\GTHE4_COMMON'. +Generating RTLIL representation for module `\GTYE3_CHANNEL'. +Generating RTLIL representation for module `\GTYE3_COMMON'. +Generating RTLIL representation for module `\GTYE4_CHANNEL'. +Generating RTLIL representation for module `\GTYE4_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE3'. +Generating RTLIL representation for module `\IBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE3'. +Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. +Generating RTLIL representation for module `\OBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. +Generating RTLIL representation for module `\PCIE_A1'. +Generating RTLIL representation for module `\PCIE_EP'. +Generating RTLIL representation for module `\PCIE_2_0'. +Generating RTLIL representation for module `\PCIE_2_1'. +Generating RTLIL representation for module `\PCIE_3_0'. +Generating RTLIL representation for module `\PCIE_3_1'. +Generating RTLIL representation for module `\PCIE40E4'. +Generating RTLIL representation for module `\EMAC'. +Generating RTLIL representation for module `\TEMAC'. +Generating RTLIL representation for module `\TEMAC_SINGLE'. +Generating RTLIL representation for module `\CMAC'. +Generating RTLIL representation for module `\CMACE4'. +Generating RTLIL representation for module `\PPC405_ADV'. +Generating RTLIL representation for module `\PPC440'. +Generating RTLIL representation for module `\MCB'. +Generating RTLIL representation for module `\PS7'. +Generating RTLIL representation for module `\PS8'. +Generating RTLIL representation for module `\ILKN'. +Generating RTLIL representation for module `\ILKNE4'. +Successfully finished Verilog frontend. + +3.3. Executing HIERARCHY pass (managing design hierarchy). + +3.3.1. Analyzing design hierarchy.. +Top module: \block_ram + +3.3.2. Analyzing design hierarchy.. +Top module: \block_ram +Removed 0 unused modules. + +3.4. Executing PROC pass (convert processes to netlists). + +3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 1 assignment to connection. + +3.4.4. Executing PROC_INIT pass (extract init attributes). + +3.4.5. Executing PROC_ARST pass (detect async resets in processes). + +3.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\block_ram.$proc$attributes_test.v:14$2'. + 1/3: $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 + 2/3: $0$memwr$\memory$attributes_test.v:16$1_DATA[3:0]$4 + 3/3: $0$memwr$\memory$attributes_test.v:16$1_ADDR[9:0]$3 + +3.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.4.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\block_ram.\data_out_r' using process `\block_ram.$proc$attributes_test.v:14$2'. + created $dff cell `$procdff$48' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_ADDR' using process `\block_ram.$proc$attributes_test.v:14$2'. + created $dff cell `$procdff$49' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_DATA' using process `\block_ram.$proc$attributes_test.v:14$2'. + created $dff cell `$procdff$50' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_EN' using process `\block_ram.$proc$attributes_test.v:14$2'. + created $dff cell `$procdff$51' with positive edge clock. + +3.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\block_ram.$proc$attributes_test.v:14$2'. +Removing empty process `block_ram.$proc$attributes_test.v:14$2'. +Cleaned up 1 empty switch. + +3.5. Executing TRIBUF pass. + +3.6. Executing DEMINOUT pass (demote inout ports to input or output). + +3.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 7 unused wires. + + +3.9. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +found and reported 0 problems. + +3.10. Executing OPT pass (performing simple optimizations). + +3.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. + Consolidated identical input bits for $mux cell $procmux$42: + Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] + New connections: $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [3:1] = { $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] } + Optimizing cells in module \block_ram. +Performed a total of 1 changes. + +3.10.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.10.6. Executing OPT_RMDFF pass (remove dff with constant values). + +3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.10.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.10.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +3.10.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.10.13. Executing OPT_RMDFF pass (remove dff with constant values). + +3.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.10.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.10.16. Finished OPT passes. (There is nothing left to do.) + +3.11. Executing WREDUCE pass (reducing word size of cells). +Removed cell block_ram.$procmux$44 ($mux). +Removed cell block_ram.$procmux$46 ($mux). +Removed top 3 bits (of 4) from FF cell block_ram.$procdff$51 ($dff). + +3.12. Executing PEEPOPT pass (run peephole optimizers). + +3.13. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 2 unused wires. + + +3.14. Executing PMUX2SHIFTX pass. + +3.15. Executing TECHMAP pass (map to technology primitives). + +3.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +3.15.2. Continuing TECHMAP pass. +No more expansions possible. + +3.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). +Checking cell `$memwr$\memory$attributes_test.v:16$7' in module `\block_ram': merged $dff to cell. +Checking cell `$memrd$\memory$attributes_test.v:17$6' in module `\block_ram': merged data $dff to cell. + +3.17. Executing TECHMAP pass (map to technology primitives). + +3.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +3.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL25X18'. +Successfully finished Verilog frontend. + +3.17.3. Continuing TECHMAP pass. +No more expansions possible. + +3.18. Executing OPT_EXPR pass (perform const folding). + +3.19. Executing WREDUCE pass (reducing word size of cells). + +3.20. Executing XILINX_DSP pass (pack resources into DSPs). + +3.21. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module block_ram: + created 0 $alu and 0 $macc cells. + +3.22. Executing SHARE pass (SAT-based resource sharing). + +3.23. Executing OPT pass (performing simple optimizations). + +3.23.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.23.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +3.23.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.23.6. Executing OPT_RMDFF pass (remove dff with constant values). + +3.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 4 unused cells and 5 unused wires. + + +3.23.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.23.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +3.23.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.23.13. Executing OPT_RMDFF pass (remove dff with constant values). + +3.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.23.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.23.16. Finished OPT passes. (There is nothing left to do.) + +3.24. Executing FSM pass (extract and optimize FSM). + +3.24.1. Executing FSM_DETECT pass (finding FSMs in design). + +3.24.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +3.24.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.24.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +3.24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +3.24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +3.25. Executing OPT pass (performing simple optimizations). + +3.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.25.3. Executing OPT_RMDFF pass (remove dff with constant values). + +3.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.25.5. Finished fast OPT passes. + +3.26. Executing MEMORY pass. + +3.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +3.26.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). + +3.26.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.26.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +3.26.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.26.6. Executing MEMORY_COLLECT pass (generating $mem cells). +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\block_ram': + $memwr$\memory$attributes_test.v:16$7 ($memwr) + $memrd$\memory$attributes_test.v:17$6 ($memrd) + +3.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing block_ram.memory: + Properties: ports=2 bits=4096 rports=1 wports=1 dbits=4 abits=10 words=1024 + Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): + Bram geometry: abits=9 dbits=72 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_SDP: awaste=0 dwaste=68 bwaste=34816 waste=34816 efficiency=5 + Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) accepted. + Mapping to bram type $__XILINX_RAMB36_SDP (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=34816 efficiency=5 + Storing for later selection. + Checking rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_SDP: awaste=0 dwaste=32 bwaste=16384 waste=16384 efficiency=11 + Rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1) accepted. + Mapping to bram type $__XILINX_RAMB18_SDP (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=16384 efficiency=11 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1): + Bram geometry: abits=10 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=0 dwaste=32 bwaste=32768 waste=32768 efficiency=11 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=32768 efficiency=11 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2): + Bram geometry: abits=11 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=1024 dwaste=14 bwaste=32768 waste=32768 efficiency=11 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=32768 efficiency=11 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3): + Bram geometry: abits=12 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=3072 dwaste=5 bwaste=32768 waste=32768 efficiency=11 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 3): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=32768 efficiency=11 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4): + Bram geometry: abits=13 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=7168 dwaste=0 bwaste=28672 waste=28672 efficiency=12 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 4): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=28672 efficiency=12 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5): + Bram geometry: abits=14 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=15360 dwaste=0 bwaste=30720 waste=30720 efficiency=6 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 5): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=30720 efficiency=6 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6): + Bram geometry: abits=15 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=31744 dwaste=0 bwaste=31744 waste=31744 efficiency=3 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=0 dwaste=14 bwaste=14336 waste=14336 efficiency=22 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=1024 dwaste=5 bwaste=14336 waste=14336 efficiency=22 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=12288 efficiency=25 + Storing for later selection. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=14336 efficiency=12 + Storing for later selection. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 5): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=15360 efficiency=6 + Storing for later selection. + Selecting best of 12 rules: + Efficiency for rule 4.5: efficiency=6, cells=4, acells=1 + Efficiency for rule 4.4: efficiency=12, cells=2, acells=1 + Efficiency for rule 4.3: efficiency=25, cells=1, acells=1 + Efficiency for rule 4.2: efficiency=22, cells=1, acells=1 + Efficiency for rule 4.1: efficiency=22, cells=1, acells=1 + Efficiency for rule 3.5: efficiency=6, cells=2, acells=1 + Efficiency for rule 3.4: efficiency=12, cells=1, acells=1 + Efficiency for rule 3.3: efficiency=11, cells=1, acells=1 + Efficiency for rule 3.2: efficiency=11, cells=1, acells=1 + Efficiency for rule 3.1: efficiency=11, cells=1, acells=1 + Efficiency for rule 2.1: efficiency=11, cells=2, acells=2 + Efficiency for rule 1.1: efficiency=5, cells=2, acells=2 + Selected rule 4.3 with efficiency 25. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Creating $__XILINX_RAMB18_TDP cell at grid position <0 0 0>: memory.0.0.0 + +3.29. Executing TECHMAP pass (map to technology primitives). + +3.29.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. +Successfully finished Verilog frontend. + +3.29.2. Continuing TECHMAP pass. +Using template $paramod\$__XILINX_RAMB18_TDP\CFG_ABITS=12\CFG_DBITS=4\CFG_ENABLE_B=1\CLKPOL2=1\CLKPOL3=1 for cells of type $__XILINX_RAMB18_TDP. +No more expansions possible. + + +3.30. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). + +3.31. Executing TECHMAP pass (map to technology primitives). + +3.31.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v' to AST representation. +Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. +Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. +Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. +Successfully finished Verilog frontend. + +3.31.2. Continuing TECHMAP pass. +No more expansions possible. + +3.32. Executing OPT pass (performing simple optimizations). + +3.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + + +3.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.32.3. Executing OPT_RMDFF pass (remove dff with constant values). + +3.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 17 unused wires. + + +3.32.5. Finished fast OPT passes. + +3.33. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). + +3.34. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). + +3.35. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). +Transforming FF to FF+Enable cells in module block_ram: + +3.36. Executing OPT pass (performing simple optimizations). + +3.36.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.36.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +3.36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +3.36.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.36.6. Executing OPT_SHARE pass. + +3.36.7. Executing OPT_RMDFF pass (remove dff with constant values). + +3.36.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.36.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.36.10. Finished OPT passes. (There is nothing left to do.) + +3.37. Executing XILINX_SRL pass (Xilinx shift register extraction). + +3.38. Executing TECHMAP pass (map to technology primitives). + +3.38.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +3.38.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_xilinx_lcu'. +Generating RTLIL representation for module `\_80_xilinx_alu'. +Successfully finished Verilog frontend. + +3.38.3. Continuing TECHMAP pass. +No more expansions possible. + +3.39. Executing OPT pass (performing simple optimizations). + +3.39.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.39.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.39.3. Executing OPT_RMDFF pass (remove dff with constant values). + +3.39.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.39.5. Finished fast OPT passes. + +3.40. Executing TECHMAP pass (map to technology primitives). + +3.40.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +3.40.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. +Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. +Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. +Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. +Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. +Generating RTLIL representation for module `\$__SHREG_'. +Generating RTLIL representation for module `\$__XILINX_SHREG_'. +Generating RTLIL representation for module `\$__XILINX_MUXF78'. +Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. +Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. +Successfully finished Verilog frontend. + +3.40.3. Continuing TECHMAP pass. +No more expansions possible. + +3.41. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.42. Executing ABC pass (technology mapping using ABC). + +3.42.1. Extracting gate netlist of module `\block_ram' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. +Don't call ABC as there is nothing to map. +Removing temp directory. + +3.43. Executing XILINX_SRL pass (Xilinx shift register extraction). + +3.44. Executing TECHMAP pass (map to technology primitives). + +3.44.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +3.44.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. +Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. +Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. +Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. +Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. +Generating RTLIL representation for module `\$__SHREG_'. +Generating RTLIL representation for module `\$__XILINX_SHREG_'. +Generating RTLIL representation for module `\$__XILINX_MUXF78'. +Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. +Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. +Successfully finished Verilog frontend. + +3.44.3. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +3.44.4. Continuing TECHMAP pass. +No more expansions possible. + +3.45. Executing CLKBUFMAP pass (inserting global clock buffers). +Inserting BUFG on block_ram.clk[0]. + +3.46. Executing HIERARCHY pass (managing design hierarchy). + +3.46.1. Analyzing design hierarchy.. +Top module: \block_ram + +3.46.2. Analyzing design hierarchy.. +Top module: \block_ram +Removed 0 unused modules. + +3.47. Printing statistics. + +=== block_ram === + + Number of wires: 12 + Number of wire bits: 62 + Number of public wires: 6 + Number of public wire bits: 24 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + BUFG 1 + RAMB18E1 1 + + Estimated number of LCs: 0 + +3.48. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +found and reported 0 problems. + +4. Executing Verilog-2005 frontend: attributes_test.v +Parsing Verilog input from `attributes_test.v' to AST representation. +Generating RTLIL representation for module `\block_ram'. +Generating RTLIL representation for module `\distributed_ram'. +Generating RTLIL representation for module `\distributed_ram_manual'. +Generating RTLIL representation for module `\distributed_ram_manual_syn'. +Successfully finished Verilog frontend. + +5. Executing HIERARCHY pass (managing design hierarchy). + +5.1. Analyzing design hierarchy.. +Top module: \distributed_ram + +5.2. Analyzing design hierarchy.. +Top module: \distributed_ram +Removing unused module `\distributed_ram_manual_syn'. +Removing unused module `\distributed_ram_manual'. +Removing unused module `\block_ram'. +Removed 3 unused modules. + +6. Executing SYNTH_XILINX pass. + +6.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\VCC'. +Generating RTLIL representation for module `\GND'. +Generating RTLIL representation for module `\IBUF'. +Generating RTLIL representation for module `\IBUFG'. +Generating RTLIL representation for module `\OBUF'. +Generating RTLIL representation for module `\IOBUF'. +Generating RTLIL representation for module `\OBUFT'. +Generating RTLIL representation for module `\BUFG'. +Generating RTLIL representation for module `\BUFGCTRL'. +Generating RTLIL representation for module `\BUFHCE'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\LUT6_2'. +Generating RTLIL representation for module `\MUXCY'. +Generating RTLIL representation for module `\MUXF7'. +Generating RTLIL representation for module `\MUXF8'. +Generating RTLIL representation for module `\XORCY'. +Generating RTLIL representation for module `\CARRY4'. +Generating RTLIL representation for module `\FDRE'. +Generating RTLIL representation for module `\FDSE'. +Generating RTLIL representation for module `\FDCE'. +Generating RTLIL representation for module `\FDPE'. +Generating RTLIL representation for module `\FDRE_1'. +Generating RTLIL representation for module `\FDSE_1'. +Generating RTLIL representation for module `\FDCE_1'. +Generating RTLIL representation for module `\FDPE_1'. +Generating RTLIL representation for module `\LDCE'. +Generating RTLIL representation for module `\LDPE'. +Generating RTLIL representation for module `\RAM16X1S'. +Generating RTLIL representation for module `\RAM16X1S_1'. +Generating RTLIL representation for module `\RAM32X1S'. +Generating RTLIL representation for module `\RAM32X1S_1'. +Generating RTLIL representation for module `\RAM64X1S'. +Generating RTLIL representation for module `\RAM64X1S_1'. +Generating RTLIL representation for module `\RAM128X1S'. +Generating RTLIL representation for module `\RAM128X1S_1'. +Generating RTLIL representation for module `\RAM256X1S'. +Generating RTLIL representation for module `\RAM512X1S'. +Generating RTLIL representation for module `\RAM16X2S'. +Generating RTLIL representation for module `\RAM32X2S'. +Generating RTLIL representation for module `\RAM64X2S'. +Generating RTLIL representation for module `\RAM16X4S'. +Generating RTLIL representation for module `\RAM32X4S'. +Generating RTLIL representation for module `\RAM16X8S'. +Generating RTLIL representation for module `\RAM32X8S'. +Generating RTLIL representation for module `\RAM16X1D'. +Generating RTLIL representation for module `\RAM16X1D_1'. +Generating RTLIL representation for module `\RAM32X1D'. +Generating RTLIL representation for module `\RAM32X1D_1'. +Generating RTLIL representation for module `\RAM64X1D'. +Generating RTLIL representation for module `\RAM64X1D_1'. +Generating RTLIL representation for module `\RAM128X1D'. +Generating RTLIL representation for module `\RAM256X1D'. +Generating RTLIL representation for module `\RAM32M'. +Generating RTLIL representation for module `\RAM32M16'. +Generating RTLIL representation for module `\RAM64M'. +Generating RTLIL representation for module `\RAM64M8'. +Generating RTLIL representation for module `\ROM16X1'. +Generating RTLIL representation for module `\ROM32X1'. +Generating RTLIL representation for module `\ROM64X1'. +Generating RTLIL representation for module `\ROM128X1'. +Generating RTLIL representation for module `\ROM256X1'. +Generating RTLIL representation for module `\SRL16E'. +Generating RTLIL representation for module `\SRLC16E'. +Generating RTLIL representation for module `\SRLC32E'. +Generating RTLIL representation for module `\MULT18X18'. +Generating RTLIL representation for module `\MULT18X18S'. +Generating RTLIL representation for module `\MULT18X18SIO'. +Generating RTLIL representation for module `\DSP48A'. +Generating RTLIL representation for module `\DSP48A1'. +Generating RTLIL representation for module `\DSP48E1'. +Successfully finished Verilog frontend. + +6.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. +Generating RTLIL representation for module `\FDCPE'. +Generating RTLIL representation for module `\FDRSE'. +Generating RTLIL representation for module `\LDCPE'. +Generating RTLIL representation for module `\AND2B1L'. +Generating RTLIL representation for module `\OR2L'. +Generating RTLIL representation for module `\MUXF5'. +Generating RTLIL representation for module `\MUXF6'. +Generating RTLIL representation for module `\MUXF9'. +Generating RTLIL representation for module `\CARRY8'. +Generating RTLIL representation for module `\ORCY'. +Generating RTLIL representation for module `\MULT_AND'. +Generating RTLIL representation for module `\SRL16'. +Generating RTLIL representation for module `\SRLC16'. +Generating RTLIL representation for module `\CFGLUT5'. +Generating RTLIL representation for module `\RAMB16_S1'. +Generating RTLIL representation for module `\RAMB16_S2'. +Generating RTLIL representation for module `\RAMB16_S4'. +Generating RTLIL representation for module `\RAMB16_S9'. +Generating RTLIL representation for module `\RAMB16_S18'. +Generating RTLIL representation for module `\RAMB16_S36'. +Generating RTLIL representation for module `\RAMB16_S1_S1'. +Generating RTLIL representation for module `\RAMB16_S1_S2'. +Generating RTLIL representation for module `\RAMB16_S1_S4'. +Generating RTLIL representation for module `\RAMB16_S1_S9'. +Generating RTLIL representation for module `\RAMB16_S1_S18'. +Generating RTLIL representation for module `\RAMB16_S1_S36'. +Generating RTLIL representation for module `\RAMB16_S2_S2'. +Generating RTLIL representation for module `\RAMB16_S2_S4'. +Generating RTLIL representation for module `\RAMB16_S2_S9'. +Generating RTLIL representation for module `\RAMB16_S2_S18'. +Generating RTLIL representation for module `\RAMB16_S2_S36'. +Generating RTLIL representation for module `\RAMB16_S4_S4'. +Generating RTLIL representation for module `\RAMB16_S4_S9'. +Generating RTLIL representation for module `\RAMB16_S4_S18'. +Generating RTLIL representation for module `\RAMB16_S4_S36'. +Generating RTLIL representation for module `\RAMB16_S9_S9'. +Generating RTLIL representation for module `\RAMB16_S9_S18'. +Generating RTLIL representation for module `\RAMB16_S9_S36'. +Generating RTLIL representation for module `\RAMB16_S18_S18'. +Generating RTLIL representation for module `\RAMB16_S18_S36'. +Generating RTLIL representation for module `\RAMB16_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWER'. +Generating RTLIL representation for module `\RAMB8BWER'. +Generating RTLIL representation for module `\FIFO16'. +Generating RTLIL representation for module `\RAMB16'. +Generating RTLIL representation for module `\RAMB32_S64_ECC'. +Generating RTLIL representation for module `\FIFO18'. +Generating RTLIL representation for module `\FIFO18_36'. +Generating RTLIL representation for module `\FIFO36'. +Generating RTLIL representation for module `\FIFO36_72'. +Generating RTLIL representation for module `\RAMB18'. +Generating RTLIL representation for module `\RAMB36'. +Generating RTLIL representation for module `\RAMB18SDP'. +Generating RTLIL representation for module `\RAMB36SDP'. +Generating RTLIL representation for module `\FIFO18E1'. +Generating RTLIL representation for module `\FIFO36E1'. +Generating RTLIL representation for module `\RAMB18E1'. +Generating RTLIL representation for module `\RAMB36E1'. +Generating RTLIL representation for module `\FIFO18E2'. +Generating RTLIL representation for module `\FIFO36E2'. +Generating RTLIL representation for module `\RAMB18E2'. +Generating RTLIL representation for module `\RAMB36E2'. +Generating RTLIL representation for module `\URAM288'. +Generating RTLIL representation for module `\URAM288_BASE'. +Generating RTLIL representation for module `\DSP48'. +Generating RTLIL representation for module `\DSP48E'. +Generating RTLIL representation for module `\DSP48E2'. +Generating RTLIL representation for module `\IFDDRCPE'. +Generating RTLIL representation for module `\IFDDRRSE'. +Generating RTLIL representation for module `\OFDDRCPE'. +Generating RTLIL representation for module `\OFDDRRSE'. +Generating RTLIL representation for module `\OFDDRTCPE'. +Generating RTLIL representation for module `\OFDDRTRSE'. +Generating RTLIL representation for module `\IDDR2'. +Generating RTLIL representation for module `\ODDR2'. +Generating RTLIL representation for module `\IDDR'. +Generating RTLIL representation for module `\IDDR_2CLK'. +Generating RTLIL representation for module `\ODDR'. +Generating RTLIL representation for module `\IDELAYCTRL'. +Generating RTLIL representation for module `\IDELAY'. +Generating RTLIL representation for module `\ISERDES'. +Generating RTLIL representation for module `\OSERDES'. +Generating RTLIL representation for module `\IODELAY'. +Generating RTLIL representation for module `\ISERDES_NODELAY'. +Generating RTLIL representation for module `\IODELAYE1'. +Generating RTLIL representation for module `\ISERDESE1'. +Generating RTLIL representation for module `\OSERDESE1'. +Generating RTLIL representation for module `\IDELAYE2'. +Generating RTLIL representation for module `\ODELAYE2'. +Generating RTLIL representation for module `\ISERDESE2'. +Generating RTLIL representation for module `\OSERDESE2'. +Generating RTLIL representation for module `\PHASER_IN'. +Generating RTLIL representation for module `\PHASER_IN_PHY'. +Generating RTLIL representation for module `\PHASER_OUT'. +Generating RTLIL representation for module `\PHASER_OUT_PHY'. +Generating RTLIL representation for module `\PHASER_REF'. +Generating RTLIL representation for module `\PHY_CONTROL'. +Generating RTLIL representation for module `\IDDRE1'. +Generating RTLIL representation for module `\ODDRE1'. +Generating RTLIL representation for module `\IDELAYE3'. +Generating RTLIL representation for module `\ODELAYE3'. +Generating RTLIL representation for module `\ISERDESE3'. +Generating RTLIL representation for module `\OSERDESE3'. +Generating RTLIL representation for module `\BITSLICE_CONTROL'. +Generating RTLIL representation for module `\RIU_OR'. +Generating RTLIL representation for module `\RX_BITSLICE'. +Generating RTLIL representation for module `\RXTX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE_TRI'. +Generating RTLIL representation for module `\IODELAY2'. +Generating RTLIL representation for module `\IODRP2'. +Generating RTLIL representation for module `\IODRP2_MCB'. +Generating RTLIL representation for module `\ISERDES2'. +Generating RTLIL representation for module `\OSERDES2'. +Generating RTLIL representation for module `\IBUF_DLY_ADJ'. +Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUF_ANALOG'. +Generating RTLIL representation for module `\IBUFE3'. +Generating RTLIL representation for module `\IBUFDS'. +Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. +Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDSE3'. +Generating RTLIL representation for module `\IBUFDS_DPHY'. +Generating RTLIL representation for module `\IBUFGDS'. +Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUF_DCIEN'. +Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFE3'. +Generating RTLIL representation for module `\IOBUFDS'. +Generating RTLIL representation for module `\IOBUFDS_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDSE3'. +Generating RTLIL representation for module `\OBUFDS'. +Generating RTLIL representation for module `\OBUFDS_DPHY'. +Generating RTLIL representation for module `\OBUFTDS'. +Generating RTLIL representation for module `\KEEPER'. +Generating RTLIL representation for module `\PULLDOWN'. +Generating RTLIL representation for module `\PULLUP'. +Generating RTLIL representation for module `\DCIRESET'. +Generating RTLIL representation for module `\HPIO_VREF'. +Generating RTLIL representation for module `\BUFGCE'. +Generating RTLIL representation for module `\BUFGCE_1'. +Generating RTLIL representation for module `\BUFGMUX'. +Generating RTLIL representation for module `\BUFGMUX_1'. +Generating RTLIL representation for module `\BUFGMUX_CTRL'. +Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. +Generating RTLIL representation for module `\BUFG_GT'. +Generating RTLIL representation for module `\BUFG_GT_SYNC'. +Generating RTLIL representation for module `\BUFG_PS'. +Generating RTLIL representation for module `\BUFGCE_DIV'. +Generating RTLIL representation for module `\BUFH'. +Generating RTLIL representation for module `\BUFIO2'. +Generating RTLIL representation for module `\BUFIO2_2CLK'. +Generating RTLIL representation for module `\BUFIO2FB'. +Generating RTLIL representation for module `\BUFPLL'. +Generating RTLIL representation for module `\BUFPLL_MCB'. +Generating RTLIL representation for module `\BUFIO'. +Generating RTLIL representation for module `\BUFIODQS'. +Generating RTLIL representation for module `\BUFR'. +Generating RTLIL representation for module `\BUFMR'. +Generating RTLIL representation for module `\BUFMRCE'. +Generating RTLIL representation for module `\DCM'. +Generating RTLIL representation for module `\DCM_SP'. +Generating RTLIL representation for module `\DCM_CLKGEN'. +Generating RTLIL representation for module `\DCM_ADV'. +Generating RTLIL representation for module `\DCM_BASE'. +Generating RTLIL representation for module `\DCM_PS'. +Generating RTLIL representation for module `\PMCD'. +Generating RTLIL representation for module `\PLL_ADV'. +Generating RTLIL representation for module `\PLL_BASE'. +Generating RTLIL representation for module `\MMCM_ADV'. +Generating RTLIL representation for module `\MMCM_BASE'. +Generating RTLIL representation for module `\MMCME2_ADV'. +Generating RTLIL representation for module `\MMCME2_BASE'. +Generating RTLIL representation for module `\PLLE2_ADV'. +Generating RTLIL representation for module `\PLLE2_BASE'. +Generating RTLIL representation for module `\MMCME3_ADV'. +Generating RTLIL representation for module `\MMCME3_BASE'. +Generating RTLIL representation for module `\PLLE3_ADV'. +Generating RTLIL representation for module `\PLLE3_BASE'. +Generating RTLIL representation for module `\MMCME4_ADV'. +Generating RTLIL representation for module `\MMCME4_BASE'. +Generating RTLIL representation for module `\PLLE4_ADV'. +Generating RTLIL representation for module `\PLLE4_BASE'. +Generating RTLIL representation for module `\BUFT'. +Generating RTLIL representation for module `\IN_FIFO'. +Generating RTLIL representation for module `\OUT_FIFO'. +Generating RTLIL representation for module `\HARD_SYNC'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. +Generating RTLIL representation for module `\STARTUP_SPARTAN6'. +Generating RTLIL representation for module `\STARTUP_VIRTEX4'. +Generating RTLIL representation for module `\STARTUP_VIRTEX5'. +Generating RTLIL representation for module `\STARTUP_VIRTEX6'. +Generating RTLIL representation for module `\STARTUPE2'. +Generating RTLIL representation for module `\STARTUPE3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. +Generating RTLIL representation for module `\CAPTUREE2'. +Generating RTLIL representation for module `\ICAP_SPARTAN3A'. +Generating RTLIL representation for module `\ICAP_SPARTAN6'. +Generating RTLIL representation for module `\ICAP_VIRTEX4'. +Generating RTLIL representation for module `\ICAP_VIRTEX5'. +Generating RTLIL representation for module `\ICAP_VIRTEX6'. +Generating RTLIL representation for module `\ICAPE2'. +Generating RTLIL representation for module `\ICAPE3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. +Generating RTLIL representation for module `\BSCAN_SPARTAN6'. +Generating RTLIL representation for module `\BSCAN_VIRTEX4'. +Generating RTLIL representation for module `\BSCAN_VIRTEX5'. +Generating RTLIL representation for module `\BSCAN_VIRTEX6'. +Generating RTLIL representation for module `\BSCANE2'. +Generating RTLIL representation for module `\DNA_PORT'. +Generating RTLIL representation for module `\DNA_PORTE2'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. +Generating RTLIL representation for module `\FRAME_ECCE2'. +Generating RTLIL representation for module `\FRAME_ECCE3'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. +Generating RTLIL representation for module `\USR_ACCESSE2'. +Generating RTLIL representation for module `\POST_CRC_INTERNAL'. +Generating RTLIL representation for module `\SUSPEND_SYNC'. +Generating RTLIL representation for module `\KEY_CLEAR'. +Generating RTLIL representation for module `\MASTER_JTAG'. +Generating RTLIL representation for module `\SPI_ACCESS'. +Generating RTLIL representation for module `\EFUSE_USR'. +Generating RTLIL representation for module `\SYSMON'. +Generating RTLIL representation for module `\XADC'. +Generating RTLIL representation for module `\SYSMONE1'. +Generating RTLIL representation for module `\SYSMONE4'. +Generating RTLIL representation for module `\GTPA1_DUAL'. +Generating RTLIL representation for module `\GT11_CUSTOM'. +Generating RTLIL representation for module `\GT11_DUAL'. +Generating RTLIL representation for module `\GT11CLK'. +Generating RTLIL representation for module `\GT11CLK_MGT'. +Generating RTLIL representation for module `\GTP_DUAL'. +Generating RTLIL representation for module `\GTX_DUAL'. +Generating RTLIL representation for module `\CRC32'. +Generating RTLIL representation for module `\CRC64'. +Generating RTLIL representation for module `\GTHE1_QUAD'. +Generating RTLIL representation for module `\GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTHE1'. +Generating RTLIL representation for module `\GTHE2_CHANNEL'. +Generating RTLIL representation for module `\GTHE2_COMMON'. +Generating RTLIL representation for module `\GTPE2_CHANNEL'. +Generating RTLIL representation for module `\GTPE2_COMMON'. +Generating RTLIL representation for module `\GTXE2_CHANNEL'. +Generating RTLIL representation for module `\GTXE2_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE2'. +Generating RTLIL representation for module `\GTHE3_CHANNEL'. +Generating RTLIL representation for module `\GTHE3_COMMON'. +Generating RTLIL representation for module `\GTHE4_CHANNEL'. +Generating RTLIL representation for module `\GTHE4_COMMON'. +Generating RTLIL representation for module `\GTYE3_CHANNEL'. +Generating RTLIL representation for module `\GTYE3_COMMON'. +Generating RTLIL representation for module `\GTYE4_CHANNEL'. +Generating RTLIL representation for module `\GTYE4_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE3'. +Generating RTLIL representation for module `\IBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE3'. +Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. +Generating RTLIL representation for module `\OBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. +Generating RTLIL representation for module `\PCIE_A1'. +Generating RTLIL representation for module `\PCIE_EP'. +Generating RTLIL representation for module `\PCIE_2_0'. +Generating RTLIL representation for module `\PCIE_2_1'. +Generating RTLIL representation for module `\PCIE_3_0'. +Generating RTLIL representation for module `\PCIE_3_1'. +Generating RTLIL representation for module `\PCIE40E4'. +Generating RTLIL representation for module `\EMAC'. +Generating RTLIL representation for module `\TEMAC'. +Generating RTLIL representation for module `\TEMAC_SINGLE'. +Generating RTLIL representation for module `\CMAC'. +Generating RTLIL representation for module `\CMACE4'. +Generating RTLIL representation for module `\PPC405_ADV'. +Generating RTLIL representation for module `\PPC440'. +Generating RTLIL representation for module `\MCB'. +Generating RTLIL representation for module `\PS7'. +Generating RTLIL representation for module `\PS8'. +Generating RTLIL representation for module `\ILKN'. +Generating RTLIL representation for module `\ILKNE4'. +Successfully finished Verilog frontend. + +6.3. Executing HIERARCHY pass (managing design hierarchy). + +6.3.1. Analyzing design hierarchy.. +Top module: \distributed_ram + +6.3.2. Analyzing design hierarchy.. +Top module: \distributed_ram +Removed 0 unused modules. + +6.4. Executing PROC pass (convert processes to netlists). + +6.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +6.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +6.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 1 assignment to connection. + +6.4.4. Executing PROC_INIT pass (extract init attributes). + +6.4.5. Executing PROC_ARST pass (detect async resets in processes). + +6.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\distributed_ram.$proc$attributes_test.v:36$188'. + 1/3: $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 + 2/3: $0$memwr$\memory$attributes_test.v:38$187_DATA[7:0]$190 + 3/3: $0$memwr$\memory$attributes_test.v:38$187_ADDR[3:0]$189 + +6.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +6.4.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\distributed_ram.\data_out_r' using process `\distributed_ram.$proc$attributes_test.v:36$188'. + created $dff cell `$procdff$227' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_ADDR' using process `\distributed_ram.$proc$attributes_test.v:36$188'. + created $dff cell `$procdff$228' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_DATA' using process `\distributed_ram.$proc$attributes_test.v:36$188'. + created $dff cell `$procdff$229' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_EN' using process `\distributed_ram.$proc$attributes_test.v:36$188'. + created $dff cell `$procdff$230' with positive edge clock. + +6.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\distributed_ram.$proc$attributes_test.v:36$188'. +Removing empty process `distributed_ram.$proc$attributes_test.v:36$188'. +Cleaned up 1 empty switch. + +6.5. Executing TRIBUF pass. + +6.6. Executing DEMINOUT pass (demote inout ports to input or output). + +6.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. +Removed 0 unused cells and 7 unused wires. + + +6.9. Executing CHECK pass (checking for obvious problems). +checking module distributed_ram.. +found and reported 0 problems. + +6.10. Executing OPT pass (performing simple optimizations). + +6.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. + Consolidated identical input bits for $mux cell $procmux$221: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] + New connections: $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [7:1] = { $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] } + Optimizing cells in module \distributed_ram. +Performed a total of 1 changes. + +6.10.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.10.6. Executing OPT_RMDFF pass (remove dff with constant values). + +6.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.10.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.10.9. Rerunning OPT passes. (Maybe there is more to do..) + +6.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. +Performed a total of 0 changes. + +6.10.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.10.13. Executing OPT_RMDFF pass (remove dff with constant values). + +6.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.10.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.10.16. Finished OPT passes. (There is nothing left to do.) + +6.11. Executing WREDUCE pass (reducing word size of cells). +Removed cell distributed_ram.$procmux$223 ($mux). +Removed cell distributed_ram.$procmux$225 ($mux). +Removed top 7 bits (of 8) from FF cell distributed_ram.$procdff$230 ($dff). + +6.12. Executing PEEPOPT pass (run peephole optimizers). + +6.13. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. +Removed 0 unused cells and 2 unused wires. + + +6.14. Executing PMUX2SHIFTX pass. + +6.15. Executing TECHMAP pass (map to technology primitives). + +6.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +6.15.2. Continuing TECHMAP pass. +No more expansions possible. + +6.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). +Checking cell `$memwr$\memory$attributes_test.v:38$193' in module `\distributed_ram': merged $dff to cell. +Checking cell `$memrd$\memory$attributes_test.v:39$192' in module `\distributed_ram': merged data $dff to cell. + +6.17. Executing TECHMAP pass (map to technology primitives). + +6.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +6.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL25X18'. +Successfully finished Verilog frontend. + +6.17.3. Continuing TECHMAP pass. +No more expansions possible. + +6.18. Executing OPT_EXPR pass (perform const folding). + +6.19. Executing WREDUCE pass (reducing word size of cells). + +6.20. Executing XILINX_DSP pass (pack resources into DSPs). + +6.21. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module distributed_ram: + created 0 $alu and 0 $macc cells. + +6.22. Executing SHARE pass (SAT-based resource sharing). + +6.23. Executing OPT pass (performing simple optimizations). + +6.23.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.23.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. +Performed a total of 0 changes. + +6.23.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.23.6. Executing OPT_RMDFF pass (remove dff with constant values). + +6.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. +Removed 4 unused cells and 5 unused wires. + + +6.23.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.23.9. Rerunning OPT passes. (Maybe there is more to do..) + +6.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. +Performed a total of 0 changes. + +6.23.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.23.13. Executing OPT_RMDFF pass (remove dff with constant values). + +6.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.23.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.23.16. Finished OPT passes. (There is nothing left to do.) + +6.24. Executing FSM pass (extract and optimize FSM). + +6.24.1. Executing FSM_DETECT pass (finding FSMs in design). + +6.24.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +6.24.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.24.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +6.24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +6.24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +6.24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +6.25. Executing OPT pass (performing simple optimizations). + +6.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.25.3. Executing OPT_RMDFF pass (remove dff with constant values). + +6.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.25.5. Finished fast OPT passes. + +6.26. Executing MEMORY pass. + +6.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +6.26.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). + +6.26.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.26.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +6.26.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.26.6. Executing MEMORY_COLLECT pass (generating $mem cells). +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram': + $memwr$\memory$attributes_test.v:38$193 ($memwr) + $memrd$\memory$attributes_test.v:39$192 ($memrd) + +6.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing distributed_ram.memory: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): + Bram geometry: abits=9 dbits=72 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_SDP: awaste=496 dwaste=64 bwaste=36736 waste=36736 efficiency=0 + Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_SDP: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1): + Bram geometry: abits=10 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=1008 dwaste=28 bwaste=36736 waste=36736 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2): + Bram geometry: abits=11 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=2032 dwaste=10 bwaste=36736 waste=36736 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3): + Bram geometry: abits=12 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=4080 dwaste=1 bwaste=36736 waste=36736 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4): + Bram geometry: abits=13 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=8176 dwaste=0 bwaste=32704 waste=32704 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5): + Bram geometry: abits=14 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=16368 dwaste=0 bwaste=32736 waste=32736 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6): + Bram geometry: abits=15 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=32752 dwaste=0 bwaste=32752 waste=32752 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. + No acceptable bram resources found. + +6.29. Executing TECHMAP pass (map to technology primitives). + +6.29.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. +Successfully finished Verilog frontend. + +6.29.2. Continuing TECHMAP pass. +No more expansions possible. + +6.30. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing distributed_ram.memory: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__XILINX_RAM32X1D (variant 1): + Bram geometry: abits=5 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAM32X1D: awaste=16 dwaste=0 bwaste=16 waste=16 efficiency=50 + Rule #1 for bram type $__XILINX_RAM32X1D (variant 1) accepted. + Mapping to bram type $__XILINX_RAM32X1D (variant 1): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=16 efficiency=50 + Storing for later selection. + Checking rule #2 for bram type $__XILINX_RAM64X1D (variant 1): + Bram geometry: abits=6 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAM64X1D: awaste=48 dwaste=0 bwaste=48 waste=48 efficiency=25 + Rule #2 for bram type $__XILINX_RAM64X1D (variant 1) accepted. + Mapping to bram type $__XILINX_RAM64X1D (variant 1): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=48 efficiency=25 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAM128X1D (variant 1): + Bram geometry: abits=7 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAM128X1D: awaste=112 dwaste=0 bwaste=112 waste=112 efficiency=12 + Rule #3 for bram type $__XILINX_RAM128X1D (variant 1) accepted. + Mapping to bram type $__XILINX_RAM128X1D (variant 1): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=112 efficiency=12 + Storing for later selection. + Selecting best of 3 rules: + Efficiency for rule 3.1: efficiency=12, cells=8, acells=1 + Efficiency for rule 2.1: efficiency=25, cells=8, acells=1 + Efficiency for rule 1.1: efficiency=50, cells=8, acells=1 + Selected rule 1.1 with efficiency 50. + Mapping to bram type $__XILINX_RAM32X1D (variant 1): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Creating $__XILINX_RAM32X1D cell at grid position <0 0 0>: memory.0.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <1 0 0>: memory.1.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <2 0 0>: memory.2.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <3 0 0>: memory.3.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <4 0 0>: memory.4.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <5 0 0>: memory.5.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <6 0 0>: memory.6.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <7 0 0>: memory.7.0.0 + +6.31. Executing TECHMAP pass (map to technology primitives). + +6.31.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v' to AST representation. +Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. +Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. +Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. +Successfully finished Verilog frontend. + +6.31.2. Continuing TECHMAP pass. +Using template $paramod\$__XILINX_RAM32X1D\CLKPOL2=1 for cells of type $__XILINX_RAM32X1D. +No more expansions possible. + + +6.32. Executing OPT pass (performing simple optimizations). + +6.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + + +6.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.32.3. Executing OPT_RMDFF pass (remove dff with constant values). + +6.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. +Removed 0 unused cells and 65 unused wires. + + +6.32.5. Finished fast OPT passes. + +6.33. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). + +6.34. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). + +6.35. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). +Transforming FF to FF+Enable cells in module distributed_ram: + +6.36. Executing OPT pass (performing simple optimizations). + +6.36.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.36.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +6.36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. +Performed a total of 0 changes. + +6.36.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.36.6. Executing OPT_SHARE pass. + +6.36.7. Executing OPT_RMDFF pass (remove dff with constant values). + +6.36.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.36.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.36.10. Finished OPT passes. (There is nothing left to do.) + +6.37. Executing XILINX_SRL pass (Xilinx shift register extraction). + +6.38. Executing TECHMAP pass (map to technology primitives). + +6.38.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.38.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_xilinx_lcu'. +Generating RTLIL representation for module `\_80_xilinx_alu'. +Successfully finished Verilog frontend. + +6.38.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +No more expansions possible. + + +6.39. Executing OPT pass (performing simple optimizations). + +6.39.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.39.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.39.3. Executing OPT_RMDFF pass (remove dff with constant values). + +6.39.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.39.5. Finished fast OPT passes. + +6.40. Executing TECHMAP pass (map to technology primitives). + +6.40.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.40.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. +Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. +Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. +Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. +Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. +Generating RTLIL representation for module `\$__SHREG_'. +Generating RTLIL representation for module `\$__XILINX_SHREG_'. +Generating RTLIL representation for module `\$__XILINX_MUXF78'. +Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. +Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. +Successfully finished Verilog frontend. + +6.40.3. Continuing TECHMAP pass. +No more expansions possible. + +6.41. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.42. Executing ABC pass (technology mapping using ABC). + +6.42.1. Extracting gate netlist of module `\distributed_ram' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. +Don't call ABC as there is nothing to map. +Removing temp directory. + +6.43. Executing XILINX_SRL pass (Xilinx shift register extraction). + +6.44. Executing TECHMAP pass (map to technology primitives). + +6.44.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +6.44.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. +Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. +Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. +Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. +Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. +Generating RTLIL representation for module `\$__SHREG_'. +Generating RTLIL representation for module `\$__XILINX_SHREG_'. +Generating RTLIL representation for module `\$__XILINX_MUXF78'. +Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. +Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. +Successfully finished Verilog frontend. + +6.44.3. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +6.44.4. Continuing TECHMAP pass. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + +Removed 0 unused cells and 32 unused wires. + +6.45. Executing CLKBUFMAP pass (inserting global clock buffers). +Inserting BUFG on distributed_ram.clk[0]. + +6.46. Executing HIERARCHY pass (managing design hierarchy). + +6.46.1. Analyzing design hierarchy.. +Top module: \distributed_ram + +6.46.2. Analyzing design hierarchy.. +Top module: \distributed_ram +Removed 0 unused modules. + +6.47. Printing statistics. + +=== distributed_ram === + + Number of wires: 16 + Number of wire bits: 40 + Number of public wires: 6 + Number of public wire bits: 30 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + BUFG 1 + FDRE 8 + RAM32X1D 8 + + Estimated number of LCs: 0 + +6.48. Executing CHECK pass (checking for obvious problems). +checking module distributed_ram.. +found and reported 0 problems. + +7. Executing Verilog-2005 frontend: attributes_test.v +Parsing Verilog input from `attributes_test.v' to AST representation. +Generating RTLIL representation for module `\block_ram'. +Generating RTLIL representation for module `\distributed_ram'. +Generating RTLIL representation for module `\distributed_ram_manual'. +Generating RTLIL representation for module `\distributed_ram_manual_syn'. +Successfully finished Verilog frontend. + +8. Executing PREP pass. + +8.1. Executing HIERARCHY pass (managing design hierarchy). + +8.2. Executing PROC pass (convert processes to netlists). + +8.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +8.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +8.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +8.2.4. Executing PROC_INIT pass (extract init attributes). + +8.2.5. Executing PROC_ARST pass (detect async resets in processes). + +8.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + 1/3: $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 + 2/3: $0$memwr$\memory$attributes_test.v:82$440_DATA[7:0]$444 + 3/3: $0$memwr$\memory$attributes_test.v:82$440_ADDR[3:0]$442 +Creating decoders for process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + 1/3: $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 + 2/3: $0$memwr$\memory$attributes_test.v:60$433_DATA[7:0]$437 + 3/3: $0$memwr$\memory$attributes_test.v:60$433_ADDR[3:0]$436 +Creating decoders for process `\distributed_ram.$proc$attributes_test.v:36$427'. + 1/3: $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 + 2/3: $0$memwr$\memory$attributes_test.v:38$426_DATA[7:0]$429 + 3/3: $0$memwr$\memory$attributes_test.v:38$426_ADDR[3:0]$428 +Creating decoders for process `\block_ram.$proc$attributes_test.v:14$420'. + 1/3: $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 + 2/3: $0$memwr$\memory$attributes_test.v:16$419_DATA[3:0]$422 + 3/3: $0$memwr$\memory$attributes_test.v:16$419_ADDR[9:0]$421 + +8.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +8.2.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_ADDR' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + created $dff cell `$procdff$471' with positive edge clock. +Creating register for signal `\distributed_ram_manual_syn.\data_out_r' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + created $dff cell `$procdff$472' with positive edge clock. +Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_EN' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + created $dff cell `$procdff$473' with positive edge clock. +Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_DATA' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + created $dff cell `$procdff$474' with positive edge clock. +Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_EN' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + created $dff cell `$procdff$475' with positive edge clock. +Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_ADDR' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + created $dff cell `$procdff$476' with positive edge clock. +Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_DATA' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + created $dff cell `$procdff$477' with positive edge clock. +Creating register for signal `\distributed_ram_manual.\data_out_r' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + created $dff cell `$procdff$478' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_ADDR' using process `\distributed_ram.$proc$attributes_test.v:36$427'. + created $dff cell `$procdff$479' with positive edge clock. +Creating register for signal `\distributed_ram.\data_out_r' using process `\distributed_ram.$proc$attributes_test.v:36$427'. + created $dff cell `$procdff$480' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_DATA' using process `\distributed_ram.$proc$attributes_test.v:36$427'. + created $dff cell `$procdff$481' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_EN' using process `\distributed_ram.$proc$attributes_test.v:36$427'. + created $dff cell `$procdff$482' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_ADDR' using process `\block_ram.$proc$attributes_test.v:14$420'. + created $dff cell `$procdff$483' with positive edge clock. +Creating register for signal `\block_ram.\data_out_r' using process `\block_ram.$proc$attributes_test.v:14$420'. + created $dff cell `$procdff$484' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_DATA' using process `\block_ram.$proc$attributes_test.v:14$420'. + created $dff cell `$procdff$485' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_EN' using process `\block_ram.$proc$attributes_test.v:14$420'. + created $dff cell `$procdff$486' with positive edge clock. + +8.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. +Removing empty process `distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. +Found and cleaned up 1 empty switch in `\distributed_ram_manual.$proc$attributes_test.v:58$434'. +Removing empty process `distributed_ram_manual.$proc$attributes_test.v:58$434'. +Found and cleaned up 1 empty switch in `\distributed_ram.$proc$attributes_test.v:36$427'. +Removing empty process `distributed_ram.$proc$attributes_test.v:36$427'. +Found and cleaned up 1 empty switch in `\block_ram.$proc$attributes_test.v:14$420'. +Removing empty process `block_ram.$proc$attributes_test.v:14$420'. +Cleaned up 4 empty switches. + +8.3. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram_manual_syn. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram. +Optimizing module block_ram. + +8.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram_manual_syn.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 28 unused wires. + + +8.5. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +checking module distributed_ram.. +checking module distributed_ram_manual.. +checking module distributed_ram_manual_syn.. +found and reported 0 problems. + +8.6. Executing OPT pass (performing simple optimizations). + +8.6.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. +Optimizing module distributed_ram. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram_manual_syn. + +8.6.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Finding identical cells in module `\distributed_ram'. +Finding identical cells in module `\distributed_ram_manual'. +Finding identical cells in module `\distributed_ram_manual_syn'. +Removed a total of 0 cells. + +8.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram_manual.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram_manual_syn.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +8.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. + Consolidated identical input bits for $mux cell $procmux$465: + Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] + New connections: $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [3:1] = { $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] } + Optimizing cells in module \block_ram. + Optimizing cells in module \distributed_ram. + Consolidated identical input bits for $mux cell $procmux$459: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] + New connections: $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [7:1] = { $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] } + Optimizing cells in module \distributed_ram. + Optimizing cells in module \distributed_ram_manual. + Consolidated identical input bits for $mux cell $procmux$453: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] + New connections: $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [7:1] = { $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] } + Optimizing cells in module \distributed_ram_manual. + Optimizing cells in module \distributed_ram_manual_syn. + Consolidated identical input bits for $mux cell $procmux$447: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] + New connections: $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [7:1] = { $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] } + Optimizing cells in module \distributed_ram_manual_syn. +Performed a total of 4 changes. + +8.6.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Finding identical cells in module `\distributed_ram'. +Finding identical cells in module `\distributed_ram_manual'. +Finding identical cells in module `\distributed_ram_manual_syn'. +Removed a total of 0 cells. + +8.6.6. Executing OPT_RMDFF pass (remove dff with constant values). + +8.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram_manual_syn.. + +8.6.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. +Optimizing module distributed_ram. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram_manual_syn. + +8.6.9. Rerunning OPT passes. (Maybe there is more to do..) + +8.6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram_manual.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram_manual_syn.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +8.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. + Optimizing cells in module \distributed_ram. + Optimizing cells in module \distributed_ram_manual. + Optimizing cells in module \distributed_ram_manual_syn. +Performed a total of 0 changes. + +8.6.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Finding identical cells in module `\distributed_ram'. +Finding identical cells in module `\distributed_ram_manual'. +Finding identical cells in module `\distributed_ram_manual_syn'. +Removed a total of 0 cells. + +8.6.13. Executing OPT_RMDFF pass (remove dff with constant values). + +8.6.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram_manual_syn.. + +8.6.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. +Optimizing module distributed_ram. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram_manual_syn. + +8.6.16. Finished OPT passes. (There is nothing left to do.) + +8.7. Executing WREDUCE pass (reducing word size of cells). +Removed top 3 bits (of 4) from FF cell block_ram.$procdff$486 ($dff). +Removed top 7 bits (of 8) from FF cell distributed_ram.$procdff$482 ($dff). +Removed top 7 bits (of 8) from FF cell distributed_ram_manual.$procdff$475 ($dff). +Removed top 7 bits (of 8) from FF cell distributed_ram_manual_syn.$procdff$473 ($dff). + +8.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). +Checking cell `$memwr$\memory$attributes_test.v:16$425' in module `\block_ram': merged $dff to cell. +Checking cell `$memwr$\memory$attributes_test.v:38$432' in module `\distributed_ram': merged $dff to cell. +Checking cell `$memwr$\memory$attributes_test.v:60$439' in module `\distributed_ram_manual': merged $dff to cell. +Checking cell `$memwr$\memory$attributes_test.v:82$446' in module `\distributed_ram_manual_syn': merged $dff to cell. + +8.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram_manual_syn.. +Removed 12 unused cells and 12 unused wires. + + +8.10. Executing MEMORY_COLLECT pass (generating $mem cells). +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\block_ram': + $memwr$\memory$attributes_test.v:16$425 ($memwr) + $memrd$\memory$attributes_test.v:17$424 ($memrd) +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram': + $memwr$\memory$attributes_test.v:38$432 ($memwr) + $memrd$\memory$attributes_test.v:39$431 ($memrd) +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram_manual': + $memwr$\memory$attributes_test.v:60$439 ($memwr) + $memrd$\memory$attributes_test.v:61$438 ($memrd) +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram_manual_syn': + $memwr$\memory$attributes_test.v:82$446 ($memwr) + $memrd$\memory$attributes_test.v:83$445 ($memrd) + +8.11. Executing OPT pass (performing simple optimizations). + +8.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. +Optimizing module distributed_ram. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram_manual_syn. + +8.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Finding identical cells in module `\distributed_ram'. +Finding identical cells in module `\distributed_ram_manual'. +Finding identical cells in module `\distributed_ram_manual_syn'. +Removed a total of 0 cells. + +8.11.3. Executing OPT_RMDFF pass (remove dff with constant values). + +8.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram_manual_syn.. + +8.11.5. Finished fast OPT passes. + +8.12. Printing statistics. + +=== block_ram === + + Number of wires: 10 + Number of wire bits: 46 + Number of public wires: 6 + Number of public wire bits: 24 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $dff 1 + $mem 1 + $mux 3 + +=== distributed_ram === + + Number of wires: 10 + Number of wire bits: 58 + Number of public wires: 6 + Number of public wire bits: 30 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $dff 1 + $mem 1 + $mux 3 + +=== distributed_ram_manual === + + Number of wires: 10 + Number of wire bits: 58 + Number of public wires: 6 + Number of public wire bits: 30 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $dff 1 + $mem 1 + $mux 3 + +=== distributed_ram_manual_syn === + + Number of wires: 10 + Number of wire bits: 58 + Number of public wires: 6 + Number of public wire bits: 30 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $dff 1 + $mem 1 + $mux 3 + +8.13. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +checking module distributed_ram.. +checking module distributed_ram_manual.. +checking module distributed_ram_manual_syn.. +found and reported 0 problems. + +9. Executing SYNTH_XILINX pass. + +9.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\VCC'. +Generating RTLIL representation for module `\GND'. +Generating RTLIL representation for module `\IBUF'. +Generating RTLIL representation for module `\IBUFG'. +Generating RTLIL representation for module `\OBUF'. +Generating RTLIL representation for module `\IOBUF'. +Generating RTLIL representation for module `\OBUFT'. +Generating RTLIL representation for module `\BUFG'. +Generating RTLIL representation for module `\BUFGCTRL'. +Generating RTLIL representation for module `\BUFHCE'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\LUT6_2'. +Generating RTLIL representation for module `\MUXCY'. +Generating RTLIL representation for module `\MUXF7'. +Generating RTLIL representation for module `\MUXF8'. +Generating RTLIL representation for module `\XORCY'. +Generating RTLIL representation for module `\CARRY4'. +Generating RTLIL representation for module `\FDRE'. +Generating RTLIL representation for module `\FDSE'. +Generating RTLIL representation for module `\FDCE'. +Generating RTLIL representation for module `\FDPE'. +Generating RTLIL representation for module `\FDRE_1'. +Generating RTLIL representation for module `\FDSE_1'. +Generating RTLIL representation for module `\FDCE_1'. +Generating RTLIL representation for module `\FDPE_1'. +Generating RTLIL representation for module `\LDCE'. +Generating RTLIL representation for module `\LDPE'. +Generating RTLIL representation for module `\RAM16X1S'. +Generating RTLIL representation for module `\RAM16X1S_1'. +Generating RTLIL representation for module `\RAM32X1S'. +Generating RTLIL representation for module `\RAM32X1S_1'. +Generating RTLIL representation for module `\RAM64X1S'. +Generating RTLIL representation for module `\RAM64X1S_1'. +Generating RTLIL representation for module `\RAM128X1S'. +Generating RTLIL representation for module `\RAM128X1S_1'. +Generating RTLIL representation for module `\RAM256X1S'. +Generating RTLIL representation for module `\RAM512X1S'. +Generating RTLIL representation for module `\RAM16X2S'. +Generating RTLIL representation for module `\RAM32X2S'. +Generating RTLIL representation for module `\RAM64X2S'. +Generating RTLIL representation for module `\RAM16X4S'. +Generating RTLIL representation for module `\RAM32X4S'. +Generating RTLIL representation for module `\RAM16X8S'. +Generating RTLIL representation for module `\RAM32X8S'. +Generating RTLIL representation for module `\RAM16X1D'. +Generating RTLIL representation for module `\RAM16X1D_1'. +Generating RTLIL representation for module `\RAM32X1D'. +Generating RTLIL representation for module `\RAM32X1D_1'. +Generating RTLIL representation for module `\RAM64X1D'. +Generating RTLIL representation for module `\RAM64X1D_1'. +Generating RTLIL representation for module `\RAM128X1D'. +Generating RTLIL representation for module `\RAM256X1D'. +Generating RTLIL representation for module `\RAM32M'. +Generating RTLIL representation for module `\RAM32M16'. +Generating RTLIL representation for module `\RAM64M'. +Generating RTLIL representation for module `\RAM64M8'. +Generating RTLIL representation for module `\ROM16X1'. +Generating RTLIL representation for module `\ROM32X1'. +Generating RTLIL representation for module `\ROM64X1'. +Generating RTLIL representation for module `\ROM128X1'. +Generating RTLIL representation for module `\ROM256X1'. +Generating RTLIL representation for module `\SRL16E'. +Generating RTLIL representation for module `\SRLC16E'. +Generating RTLIL representation for module `\SRLC32E'. +Generating RTLIL representation for module `\MULT18X18'. +Generating RTLIL representation for module `\MULT18X18S'. +Generating RTLIL representation for module `\MULT18X18SIO'. +Generating RTLIL representation for module `\DSP48A'. +Generating RTLIL representation for module `\DSP48A1'. +Generating RTLIL representation for module `\DSP48E1'. +Successfully finished Verilog frontend. + +9.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. +Generating RTLIL representation for module `\FDCPE'. +Generating RTLIL representation for module `\FDRSE'. +Generating RTLIL representation for module `\LDCPE'. +Generating RTLIL representation for module `\AND2B1L'. +Generating RTLIL representation for module `\OR2L'. +Generating RTLIL representation for module `\MUXF5'. +Generating RTLIL representation for module `\MUXF6'. +Generating RTLIL representation for module `\MUXF9'. +Generating RTLIL representation for module `\CARRY8'. +Generating RTLIL representation for module `\ORCY'. +Generating RTLIL representation for module `\MULT_AND'. +Generating RTLIL representation for module `\SRL16'. +Generating RTLIL representation for module `\SRLC16'. +Generating RTLIL representation for module `\CFGLUT5'. +Generating RTLIL representation for module `\RAMB16_S1'. +Generating RTLIL representation for module `\RAMB16_S2'. +Generating RTLIL representation for module `\RAMB16_S4'. +Generating RTLIL representation for module `\RAMB16_S9'. +Generating RTLIL representation for module `\RAMB16_S18'. +Generating RTLIL representation for module `\RAMB16_S36'. +Generating RTLIL representation for module `\RAMB16_S1_S1'. +Generating RTLIL representation for module `\RAMB16_S1_S2'. +Generating RTLIL representation for module `\RAMB16_S1_S4'. +Generating RTLIL representation for module `\RAMB16_S1_S9'. +Generating RTLIL representation for module `\RAMB16_S1_S18'. +Generating RTLIL representation for module `\RAMB16_S1_S36'. +Generating RTLIL representation for module `\RAMB16_S2_S2'. +Generating RTLIL representation for module `\RAMB16_S2_S4'. +Generating RTLIL representation for module `\RAMB16_S2_S9'. +Generating RTLIL representation for module `\RAMB16_S2_S18'. +Generating RTLIL representation for module `\RAMB16_S2_S36'. +Generating RTLIL representation for module `\RAMB16_S4_S4'. +Generating RTLIL representation for module `\RAMB16_S4_S9'. +Generating RTLIL representation for module `\RAMB16_S4_S18'. +Generating RTLIL representation for module `\RAMB16_S4_S36'. +Generating RTLIL representation for module `\RAMB16_S9_S9'. +Generating RTLIL representation for module `\RAMB16_S9_S18'. +Generating RTLIL representation for module `\RAMB16_S9_S36'. +Generating RTLIL representation for module `\RAMB16_S18_S18'. +Generating RTLIL representation for module `\RAMB16_S18_S36'. +Generating RTLIL representation for module `\RAMB16_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWER'. +Generating RTLIL representation for module `\RAMB8BWER'. +Generating RTLIL representation for module `\FIFO16'. +Generating RTLIL representation for module `\RAMB16'. +Generating RTLIL representation for module `\RAMB32_S64_ECC'. +Generating RTLIL representation for module `\FIFO18'. +Generating RTLIL representation for module `\FIFO18_36'. +Generating RTLIL representation for module `\FIFO36'. +Generating RTLIL representation for module `\FIFO36_72'. +Generating RTLIL representation for module `\RAMB18'. +Generating RTLIL representation for module `\RAMB36'. +Generating RTLIL representation for module `\RAMB18SDP'. +Generating RTLIL representation for module `\RAMB36SDP'. +Generating RTLIL representation for module `\FIFO18E1'. +Generating RTLIL representation for module `\FIFO36E1'. +Generating RTLIL representation for module `\RAMB18E1'. +Generating RTLIL representation for module `\RAMB36E1'. +Generating RTLIL representation for module `\FIFO18E2'. +Generating RTLIL representation for module `\FIFO36E2'. +Generating RTLIL representation for module `\RAMB18E2'. +Generating RTLIL representation for module `\RAMB36E2'. +Generating RTLIL representation for module `\URAM288'. +Generating RTLIL representation for module `\URAM288_BASE'. +Generating RTLIL representation for module `\DSP48'. +Generating RTLIL representation for module `\DSP48E'. +Generating RTLIL representation for module `\DSP48E2'. +Generating RTLIL representation for module `\IFDDRCPE'. +Generating RTLIL representation for module `\IFDDRRSE'. +Generating RTLIL representation for module `\OFDDRCPE'. +Generating RTLIL representation for module `\OFDDRRSE'. +Generating RTLIL representation for module `\OFDDRTCPE'. +Generating RTLIL representation for module `\OFDDRTRSE'. +Generating RTLIL representation for module `\IDDR2'. +Generating RTLIL representation for module `\ODDR2'. +Generating RTLIL representation for module `\IDDR'. +Generating RTLIL representation for module `\IDDR_2CLK'. +Generating RTLIL representation for module `\ODDR'. +Generating RTLIL representation for module `\IDELAYCTRL'. +Generating RTLIL representation for module `\IDELAY'. +Generating RTLIL representation for module `\ISERDES'. +Generating RTLIL representation for module `\OSERDES'. +Generating RTLIL representation for module `\IODELAY'. +Generating RTLIL representation for module `\ISERDES_NODELAY'. +Generating RTLIL representation for module `\IODELAYE1'. +Generating RTLIL representation for module `\ISERDESE1'. +Generating RTLIL representation for module `\OSERDESE1'. +Generating RTLIL representation for module `\IDELAYE2'. +Generating RTLIL representation for module `\ODELAYE2'. +Generating RTLIL representation for module `\ISERDESE2'. +Generating RTLIL representation for module `\OSERDESE2'. +Generating RTLIL representation for module `\PHASER_IN'. +Generating RTLIL representation for module `\PHASER_IN_PHY'. +Generating RTLIL representation for module `\PHASER_OUT'. +Generating RTLIL representation for module `\PHASER_OUT_PHY'. +Generating RTLIL representation for module `\PHASER_REF'. +Generating RTLIL representation for module `\PHY_CONTROL'. +Generating RTLIL representation for module `\IDDRE1'. +Generating RTLIL representation for module `\ODDRE1'. +Generating RTLIL representation for module `\IDELAYE3'. +Generating RTLIL representation for module `\ODELAYE3'. +Generating RTLIL representation for module `\ISERDESE3'. +Generating RTLIL representation for module `\OSERDESE3'. +Generating RTLIL representation for module `\BITSLICE_CONTROL'. +Generating RTLIL representation for module `\RIU_OR'. +Generating RTLIL representation for module `\RX_BITSLICE'. +Generating RTLIL representation for module `\RXTX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE_TRI'. +Generating RTLIL representation for module `\IODELAY2'. +Generating RTLIL representation for module `\IODRP2'. +Generating RTLIL representation for module `\IODRP2_MCB'. +Generating RTLIL representation for module `\ISERDES2'. +Generating RTLIL representation for module `\OSERDES2'. +Generating RTLIL representation for module `\IBUF_DLY_ADJ'. +Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUF_ANALOG'. +Generating RTLIL representation for module `\IBUFE3'. +Generating RTLIL representation for module `\IBUFDS'. +Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. +Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDSE3'. +Generating RTLIL representation for module `\IBUFDS_DPHY'. +Generating RTLIL representation for module `\IBUFGDS'. +Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUF_DCIEN'. +Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFE3'. +Generating RTLIL representation for module `\IOBUFDS'. +Generating RTLIL representation for module `\IOBUFDS_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDSE3'. +Generating RTLIL representation for module `\OBUFDS'. +Generating RTLIL representation for module `\OBUFDS_DPHY'. +Generating RTLIL representation for module `\OBUFTDS'. +Generating RTLIL representation for module `\KEEPER'. +Generating RTLIL representation for module `\PULLDOWN'. +Generating RTLIL representation for module `\PULLUP'. +Generating RTLIL representation for module `\DCIRESET'. +Generating RTLIL representation for module `\HPIO_VREF'. +Generating RTLIL representation for module `\BUFGCE'. +Generating RTLIL representation for module `\BUFGCE_1'. +Generating RTLIL representation for module `\BUFGMUX'. +Generating RTLIL representation for module `\BUFGMUX_1'. +Generating RTLIL representation for module `\BUFGMUX_CTRL'. +Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. +Generating RTLIL representation for module `\BUFG_GT'. +Generating RTLIL representation for module `\BUFG_GT_SYNC'. +Generating RTLIL representation for module `\BUFG_PS'. +Generating RTLIL representation for module `\BUFGCE_DIV'. +Generating RTLIL representation for module `\BUFH'. +Generating RTLIL representation for module `\BUFIO2'. +Generating RTLIL representation for module `\BUFIO2_2CLK'. +Generating RTLIL representation for module `\BUFIO2FB'. +Generating RTLIL representation for module `\BUFPLL'. +Generating RTLIL representation for module `\BUFPLL_MCB'. +Generating RTLIL representation for module `\BUFIO'. +Generating RTLIL representation for module `\BUFIODQS'. +Generating RTLIL representation for module `\BUFR'. +Generating RTLIL representation for module `\BUFMR'. +Generating RTLIL representation for module `\BUFMRCE'. +Generating RTLIL representation for module `\DCM'. +Generating RTLIL representation for module `\DCM_SP'. +Generating RTLIL representation for module `\DCM_CLKGEN'. +Generating RTLIL representation for module `\DCM_ADV'. +Generating RTLIL representation for module `\DCM_BASE'. +Generating RTLIL representation for module `\DCM_PS'. +Generating RTLIL representation for module `\PMCD'. +Generating RTLIL representation for module `\PLL_ADV'. +Generating RTLIL representation for module `\PLL_BASE'. +Generating RTLIL representation for module `\MMCM_ADV'. +Generating RTLIL representation for module `\MMCM_BASE'. +Generating RTLIL representation for module `\MMCME2_ADV'. +Generating RTLIL representation for module `\MMCME2_BASE'. +Generating RTLIL representation for module `\PLLE2_ADV'. +Generating RTLIL representation for module `\PLLE2_BASE'. +Generating RTLIL representation for module `\MMCME3_ADV'. +Generating RTLIL representation for module `\MMCME3_BASE'. +Generating RTLIL representation for module `\PLLE3_ADV'. +Generating RTLIL representation for module `\PLLE3_BASE'. +Generating RTLIL representation for module `\MMCME4_ADV'. +Generating RTLIL representation for module `\MMCME4_BASE'. +Generating RTLIL representation for module `\PLLE4_ADV'. +Generating RTLIL representation for module `\PLLE4_BASE'. +Generating RTLIL representation for module `\BUFT'. +Generating RTLIL representation for module `\IN_FIFO'. +Generating RTLIL representation for module `\OUT_FIFO'. +Generating RTLIL representation for module `\HARD_SYNC'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. +Generating RTLIL representation for module `\STARTUP_SPARTAN6'. +Generating RTLIL representation for module `\STARTUP_VIRTEX4'. +Generating RTLIL representation for module `\STARTUP_VIRTEX5'. +Generating RTLIL representation for module `\STARTUP_VIRTEX6'. +Generating RTLIL representation for module `\STARTUPE2'. +Generating RTLIL representation for module `\STARTUPE3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. +Generating RTLIL representation for module `\CAPTUREE2'. +Generating RTLIL representation for module `\ICAP_SPARTAN3A'. +Generating RTLIL representation for module `\ICAP_SPARTAN6'. +Generating RTLIL representation for module `\ICAP_VIRTEX4'. +Generating RTLIL representation for module `\ICAP_VIRTEX5'. +Generating RTLIL representation for module `\ICAP_VIRTEX6'. +Generating RTLIL representation for module `\ICAPE2'. +Generating RTLIL representation for module `\ICAPE3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. +Generating RTLIL representation for module `\BSCAN_SPARTAN6'. +Generating RTLIL representation for module `\BSCAN_VIRTEX4'. +Generating RTLIL representation for module `\BSCAN_VIRTEX5'. +Generating RTLIL representation for module `\BSCAN_VIRTEX6'. +Generating RTLIL representation for module `\BSCANE2'. +Generating RTLIL representation for module `\DNA_PORT'. +Generating RTLIL representation for module `\DNA_PORTE2'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. +Generating RTLIL representation for module `\FRAME_ECCE2'. +Generating RTLIL representation for module `\FRAME_ECCE3'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. +Generating RTLIL representation for module `\USR_ACCESSE2'. +Generating RTLIL representation for module `\POST_CRC_INTERNAL'. +Generating RTLIL representation for module `\SUSPEND_SYNC'. +Generating RTLIL representation for module `\KEY_CLEAR'. +Generating RTLIL representation for module `\MASTER_JTAG'. +Generating RTLIL representation for module `\SPI_ACCESS'. +Generating RTLIL representation for module `\EFUSE_USR'. +Generating RTLIL representation for module `\SYSMON'. +Generating RTLIL representation for module `\XADC'. +Generating RTLIL representation for module `\SYSMONE1'. +Generating RTLIL representation for module `\SYSMONE4'. +Generating RTLIL representation for module `\GTPA1_DUAL'. +Generating RTLIL representation for module `\GT11_CUSTOM'. +Generating RTLIL representation for module `\GT11_DUAL'. +Generating RTLIL representation for module `\GT11CLK'. +Generating RTLIL representation for module `\GT11CLK_MGT'. +Generating RTLIL representation for module `\GTP_DUAL'. +Generating RTLIL representation for module `\GTX_DUAL'. +Generating RTLIL representation for module `\CRC32'. +Generating RTLIL representation for module `\CRC64'. +Generating RTLIL representation for module `\GTHE1_QUAD'. +Generating RTLIL representation for module `\GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTHE1'. +Generating RTLIL representation for module `\GTHE2_CHANNEL'. +Generating RTLIL representation for module `\GTHE2_COMMON'. +Generating RTLIL representation for module `\GTPE2_CHANNEL'. +Generating RTLIL representation for module `\GTPE2_COMMON'. +Generating RTLIL representation for module `\GTXE2_CHANNEL'. +Generating RTLIL representation for module `\GTXE2_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE2'. +Generating RTLIL representation for module `\GTHE3_CHANNEL'. +Generating RTLIL representation for module `\GTHE3_COMMON'. +Generating RTLIL representation for module `\GTHE4_CHANNEL'. +Generating RTLIL representation for module `\GTHE4_COMMON'. +Generating RTLIL representation for module `\GTYE3_CHANNEL'. +Generating RTLIL representation for module `\GTYE3_COMMON'. +Generating RTLIL representation for module `\GTYE4_CHANNEL'. +Generating RTLIL representation for module `\GTYE4_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE3'. +Generating RTLIL representation for module `\IBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE3'. +Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. +Generating RTLIL representation for module `\OBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. +Generating RTLIL representation for module `\PCIE_A1'. +Generating RTLIL representation for module `\PCIE_EP'. +Generating RTLIL representation for module `\PCIE_2_0'. +Generating RTLIL representation for module `\PCIE_2_1'. +Generating RTLIL representation for module `\PCIE_3_0'. +Generating RTLIL representation for module `\PCIE_3_1'. +Generating RTLIL representation for module `\PCIE40E4'. +Generating RTLIL representation for module `\EMAC'. +Generating RTLIL representation for module `\TEMAC'. +Generating RTLIL representation for module `\TEMAC_SINGLE'. +Generating RTLIL representation for module `\CMAC'. +Generating RTLIL representation for module `\CMACE4'. +Generating RTLIL representation for module `\PPC405_ADV'. +Generating RTLIL representation for module `\PPC440'. +Generating RTLIL representation for module `\MCB'. +Generating RTLIL representation for module `\PS7'. +Generating RTLIL representation for module `\PS8'. +Generating RTLIL representation for module `\ILKN'. +Generating RTLIL representation for module `\ILKNE4'. +Successfully finished Verilog frontend. + +9.3. Executing HIERARCHY pass (managing design hierarchy). + +9.3.1. Analyzing design hierarchy.. +Top module: \block_ram + +9.3.2. Analyzing design hierarchy.. +Top module: \block_ram +Removing unused module `\distributed_ram'. +Removing unused module `\distributed_ram_manual'. +Removing unused module `\distributed_ram_manual_syn'. +Removed 3 unused modules. + +9.4. Executing PROC pass (convert processes to netlists). + +9.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +9.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +9.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +9.4.4. Executing PROC_INIT pass (extract init attributes). + +9.4.5. Executing PROC_ARST pass (detect async resets in processes). + +9.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). + +9.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +9.4.8. Executing PROC_DFF pass (convert process syncs to FFs). + +9.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +9.5. Executing TRIBUF pass. + +9.6. Executing DEMINOUT pass (demote inout ports to input or output). + +9.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +9.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +9.9. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +found and reported 0 problems. + +9.10. Executing OPT pass (performing simple optimizations). + +9.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +9.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +9.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +9.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +9.10.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +9.10.6. Executing OPT_RMDFF pass (remove dff with constant values). + +9.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +9.10.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +9.10.9. Finished OPT passes. (There is nothing left to do.) + +9.11. Executing WREDUCE pass (reducing word size of cells). +Removed cell block_ram.$procmux$469 ($mux). +Removed cell block_ram.$procmux$467 ($mux). + +9.12. Executing PEEPOPT pass (run peephole optimizers). + +9.13. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 2 unused wires. + + +9.14. Executing PMUX2SHIFTX pass. + +9.15. Executing TECHMAP pass (map to technology primitives). + +9.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +9.15.2. Continuing TECHMAP pass. +No more expansions possible. + +9.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). + +9.17. Executing TECHMAP pass (map to technology primitives). + +9.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +9.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL25X18'. +Successfully finished Verilog frontend. + +9.17.3. Continuing TECHMAP pass. +No more expansions possible. + +9.18. Executing OPT_EXPR pass (perform const folding). + +9.19. Executing WREDUCE pass (reducing word size of cells). + +9.20. Executing XILINX_DSP pass (pack resources into DSPs). + +9.21. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module block_ram: + created 0 $alu and 0 $macc cells. + +9.22. Executing SHARE pass (SAT-based resource sharing). From f3f59910eb06bf74a2a4b8157797a327dd097451 Mon Sep 17 00:00:00 2001 From: Diego H Date: Sun, 15 Dec 2019 23:51:58 -0600 Subject: [PATCH 25/46] Removing fixed attribute value to !ramstyle rules --- techlibs/xilinx/xc7_xcu_brams.txt | 8 +- tests/arch/common/memory_attributes/log | 3238 ----------------------- 2 files changed, 4 insertions(+), 3242 deletions(-) delete mode 100644 tests/arch/common/memory_attributes/log diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 2d94ac4a8..1374a0a36 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -78,7 +78,7 @@ endbram match $__XILINX_RAMB36_SDP attribute ram_style=block ram_block=1 - attribute !ram_style=distributed + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -89,7 +89,7 @@ endmatch match $__XILINX_RAMB18_SDP attribute ram_style=block ram_block=1 - attribute !ram_style=distributed + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -100,7 +100,7 @@ endmatch match $__XILINX_RAMB36_TDP attribute ram_style=block ram_block=1 - attribute !ram_style=distributed + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -111,7 +111,7 @@ endmatch match $__XILINX_RAMB18_TDP attribute ram_style=block ram_block=1 - attribute !ram_style=distributed + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 diff --git a/tests/arch/common/memory_attributes/log b/tests/arch/common/memory_attributes/log deleted file mode 100644 index 5d526e661..000000000 --- a/tests/arch/common/memory_attributes/log +++ /dev/null @@ -1,3238 +0,0 @@ - - /----------------------------------------------------------------------------\ - | | - | yosys -- Yosys Open SYnthesis Suite | - | | - | Copyright (C) 2012 - 2019 Clifford Wolf | - | | - | Permission to use, copy, modify, and/or distribute this software for any | - | purpose with or without fee is hereby granted, provided that the above | - | copyright notice and this permission notice appear in all copies. | - | | - | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | - | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | - | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | - | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | - | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | - | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | - | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | - | | - \----------------------------------------------------------------------------/ - - Yosys 0.9+932 (git sha1 26699340, clang 6.0.0-1ubuntu2 -fPIC -Os) - - --- Executing script file `attributes_test.ys' -- - -1. Executing Verilog-2005 frontend: attributes_test.v -Parsing Verilog input from `attributes_test.v' to AST representation. -Generating RTLIL representation for module `\block_ram'. -Generating RTLIL representation for module `\distributed_ram'. -Generating RTLIL representation for module `\distributed_ram_manual'. -Generating RTLIL representation for module `\distributed_ram_manual_syn'. -Successfully finished Verilog frontend. - -2. Executing HIERARCHY pass (managing design hierarchy). - -2.1. Analyzing design hierarchy.. -Top module: \block_ram - -2.2. Analyzing design hierarchy.. -Top module: \block_ram -Removing unused module `\distributed_ram_manual_syn'. -Removing unused module `\distributed_ram_manual'. -Removing unused module `\distributed_ram'. -Removed 3 unused modules. - -3. Executing SYNTH_XILINX pass. - -3.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. -Generating RTLIL representation for module `\VCC'. -Generating RTLIL representation for module `\GND'. -Generating RTLIL representation for module `\IBUF'. -Generating RTLIL representation for module `\IBUFG'. -Generating RTLIL representation for module `\OBUF'. -Generating RTLIL representation for module `\IOBUF'. -Generating RTLIL representation for module `\OBUFT'. -Generating RTLIL representation for module `\BUFG'. -Generating RTLIL representation for module `\BUFGCTRL'. -Generating RTLIL representation for module `\BUFHCE'. -Generating RTLIL representation for module `\INV'. -Generating RTLIL representation for module `\LUT1'. -Generating RTLIL representation for module `\LUT2'. -Generating RTLIL representation for module `\LUT3'. -Generating RTLIL representation for module `\LUT4'. -Generating RTLIL representation for module `\LUT5'. -Generating RTLIL representation for module `\LUT6'. -Generating RTLIL representation for module `\LUT6_2'. -Generating RTLIL representation for module `\MUXCY'. -Generating RTLIL representation for module `\MUXF7'. -Generating RTLIL representation for module `\MUXF8'. -Generating RTLIL representation for module `\XORCY'. -Generating RTLIL representation for module `\CARRY4'. -Generating RTLIL representation for module `\FDRE'. -Generating RTLIL representation for module `\FDSE'. -Generating RTLIL representation for module `\FDCE'. -Generating RTLIL representation for module `\FDPE'. -Generating RTLIL representation for module `\FDRE_1'. -Generating RTLIL representation for module `\FDSE_1'. -Generating RTLIL representation for module `\FDCE_1'. -Generating RTLIL representation for module `\FDPE_1'. -Generating RTLIL representation for module `\LDCE'. -Generating RTLIL representation for module `\LDPE'. -Generating RTLIL representation for module `\RAM16X1S'. -Generating RTLIL representation for module `\RAM16X1S_1'. -Generating RTLIL representation for module `\RAM32X1S'. -Generating RTLIL representation for module `\RAM32X1S_1'. -Generating RTLIL representation for module `\RAM64X1S'. -Generating RTLIL representation for module `\RAM64X1S_1'. -Generating RTLIL representation for module `\RAM128X1S'. -Generating RTLIL representation for module `\RAM128X1S_1'. -Generating RTLIL representation for module `\RAM256X1S'. -Generating RTLIL representation for module `\RAM512X1S'. -Generating RTLIL representation for module `\RAM16X2S'. -Generating RTLIL representation for module `\RAM32X2S'. -Generating RTLIL representation for module `\RAM64X2S'. -Generating RTLIL representation for module `\RAM16X4S'. -Generating RTLIL representation for module `\RAM32X4S'. -Generating RTLIL representation for module `\RAM16X8S'. -Generating RTLIL representation for module `\RAM32X8S'. -Generating RTLIL representation for module `\RAM16X1D'. -Generating RTLIL representation for module `\RAM16X1D_1'. -Generating RTLIL representation for module `\RAM32X1D'. -Generating RTLIL representation for module `\RAM32X1D_1'. -Generating RTLIL representation for module `\RAM64X1D'. -Generating RTLIL representation for module `\RAM64X1D_1'. -Generating RTLIL representation for module `\RAM128X1D'. -Generating RTLIL representation for module `\RAM256X1D'. -Generating RTLIL representation for module `\RAM32M'. -Generating RTLIL representation for module `\RAM32M16'. -Generating RTLIL representation for module `\RAM64M'. -Generating RTLIL representation for module `\RAM64M8'. -Generating RTLIL representation for module `\ROM16X1'. -Generating RTLIL representation for module `\ROM32X1'. -Generating RTLIL representation for module `\ROM64X1'. -Generating RTLIL representation for module `\ROM128X1'. -Generating RTLIL representation for module `\ROM256X1'. -Generating RTLIL representation for module `\SRL16E'. -Generating RTLIL representation for module `\SRLC16E'. -Generating RTLIL representation for module `\SRLC32E'. -Generating RTLIL representation for module `\MULT18X18'. -Generating RTLIL representation for module `\MULT18X18S'. -Generating RTLIL representation for module `\MULT18X18SIO'. -Generating RTLIL representation for module `\DSP48A'. -Generating RTLIL representation for module `\DSP48A1'. -Generating RTLIL representation for module `\DSP48E1'. -Successfully finished Verilog frontend. - -3.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. -Generating RTLIL representation for module `\FDCPE'. -Generating RTLIL representation for module `\FDRSE'. -Generating RTLIL representation for module `\LDCPE'. -Generating RTLIL representation for module `\AND2B1L'. -Generating RTLIL representation for module `\OR2L'. -Generating RTLIL representation for module `\MUXF5'. -Generating RTLIL representation for module `\MUXF6'. -Generating RTLIL representation for module `\MUXF9'. -Generating RTLIL representation for module `\CARRY8'. -Generating RTLIL representation for module `\ORCY'. -Generating RTLIL representation for module `\MULT_AND'. -Generating RTLIL representation for module `\SRL16'. -Generating RTLIL representation for module `\SRLC16'. -Generating RTLIL representation for module `\CFGLUT5'. -Generating RTLIL representation for module `\RAMB16_S1'. -Generating RTLIL representation for module `\RAMB16_S2'. -Generating RTLIL representation for module `\RAMB16_S4'. -Generating RTLIL representation for module `\RAMB16_S9'. -Generating RTLIL representation for module `\RAMB16_S18'. -Generating RTLIL representation for module `\RAMB16_S36'. -Generating RTLIL representation for module `\RAMB16_S1_S1'. -Generating RTLIL representation for module `\RAMB16_S1_S2'. -Generating RTLIL representation for module `\RAMB16_S1_S4'. -Generating RTLIL representation for module `\RAMB16_S1_S9'. -Generating RTLIL representation for module `\RAMB16_S1_S18'. -Generating RTLIL representation for module `\RAMB16_S1_S36'. -Generating RTLIL representation for module `\RAMB16_S2_S2'. -Generating RTLIL representation for module `\RAMB16_S2_S4'. -Generating RTLIL representation for module `\RAMB16_S2_S9'. -Generating RTLIL representation for module `\RAMB16_S2_S18'. -Generating RTLIL representation for module `\RAMB16_S2_S36'. -Generating RTLIL representation for module `\RAMB16_S4_S4'. -Generating RTLIL representation for module `\RAMB16_S4_S9'. -Generating RTLIL representation for module `\RAMB16_S4_S18'. -Generating RTLIL representation for module `\RAMB16_S4_S36'. -Generating RTLIL representation for module `\RAMB16_S9_S9'. -Generating RTLIL representation for module `\RAMB16_S9_S18'. -Generating RTLIL representation for module `\RAMB16_S9_S36'. -Generating RTLIL representation for module `\RAMB16_S18_S18'. -Generating RTLIL representation for module `\RAMB16_S18_S36'. -Generating RTLIL representation for module `\RAMB16_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWER'. -Generating RTLIL representation for module `\RAMB8BWER'. -Generating RTLIL representation for module `\FIFO16'. -Generating RTLIL representation for module `\RAMB16'. -Generating RTLIL representation for module `\RAMB32_S64_ECC'. -Generating RTLIL representation for module `\FIFO18'. -Generating RTLIL representation for module `\FIFO18_36'. -Generating RTLIL representation for module `\FIFO36'. -Generating RTLIL representation for module `\FIFO36_72'. -Generating RTLIL representation for module `\RAMB18'. -Generating RTLIL representation for module `\RAMB36'. -Generating RTLIL representation for module `\RAMB18SDP'. -Generating RTLIL representation for module `\RAMB36SDP'. -Generating RTLIL representation for module `\FIFO18E1'. -Generating RTLIL representation for module `\FIFO36E1'. -Generating RTLIL representation for module `\RAMB18E1'. -Generating RTLIL representation for module `\RAMB36E1'. -Generating RTLIL representation for module `\FIFO18E2'. -Generating RTLIL representation for module `\FIFO36E2'. -Generating RTLIL representation for module `\RAMB18E2'. -Generating RTLIL representation for module `\RAMB36E2'. -Generating RTLIL representation for module `\URAM288'. -Generating RTLIL representation for module `\URAM288_BASE'. -Generating RTLIL representation for module `\DSP48'. -Generating RTLIL representation for module `\DSP48E'. -Generating RTLIL representation for module `\DSP48E2'. -Generating RTLIL representation for module `\IFDDRCPE'. -Generating RTLIL representation for module `\IFDDRRSE'. -Generating RTLIL representation for module `\OFDDRCPE'. -Generating RTLIL representation for module `\OFDDRRSE'. -Generating RTLIL representation for module `\OFDDRTCPE'. -Generating RTLIL representation for module `\OFDDRTRSE'. -Generating RTLIL representation for module `\IDDR2'. -Generating RTLIL representation for module `\ODDR2'. -Generating RTLIL representation for module `\IDDR'. -Generating RTLIL representation for module `\IDDR_2CLK'. -Generating RTLIL representation for module `\ODDR'. -Generating RTLIL representation for module `\IDELAYCTRL'. -Generating RTLIL representation for module `\IDELAY'. -Generating RTLIL representation for module `\ISERDES'. -Generating RTLIL representation for module `\OSERDES'. -Generating RTLIL representation for module `\IODELAY'. -Generating RTLIL representation for module `\ISERDES_NODELAY'. -Generating RTLIL representation for module `\IODELAYE1'. -Generating RTLIL representation for module `\ISERDESE1'. -Generating RTLIL representation for module `\OSERDESE1'. -Generating RTLIL representation for module `\IDELAYE2'. -Generating RTLIL representation for module `\ODELAYE2'. -Generating RTLIL representation for module `\ISERDESE2'. -Generating RTLIL representation for module `\OSERDESE2'. -Generating RTLIL representation for module `\PHASER_IN'. -Generating RTLIL representation for module `\PHASER_IN_PHY'. -Generating RTLIL representation for module `\PHASER_OUT'. -Generating RTLIL representation for module `\PHASER_OUT_PHY'. -Generating RTLIL representation for module `\PHASER_REF'. -Generating RTLIL representation for module `\PHY_CONTROL'. -Generating RTLIL representation for module `\IDDRE1'. -Generating RTLIL representation for module `\ODDRE1'. -Generating RTLIL representation for module `\IDELAYE3'. -Generating RTLIL representation for module `\ODELAYE3'. -Generating RTLIL representation for module `\ISERDESE3'. -Generating RTLIL representation for module `\OSERDESE3'. -Generating RTLIL representation for module `\BITSLICE_CONTROL'. -Generating RTLIL representation for module `\RIU_OR'. -Generating RTLIL representation for module `\RX_BITSLICE'. -Generating RTLIL representation for module `\RXTX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE_TRI'. -Generating RTLIL representation for module `\IODELAY2'. -Generating RTLIL representation for module `\IODRP2'. -Generating RTLIL representation for module `\IODRP2_MCB'. -Generating RTLIL representation for module `\ISERDES2'. -Generating RTLIL representation for module `\OSERDES2'. -Generating RTLIL representation for module `\IBUF_DLY_ADJ'. -Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUF_ANALOG'. -Generating RTLIL representation for module `\IBUFE3'. -Generating RTLIL representation for module `\IBUFDS'. -Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. -Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDSE3'. -Generating RTLIL representation for module `\IBUFDS_DPHY'. -Generating RTLIL representation for module `\IBUFGDS'. -Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUF_DCIEN'. -Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFE3'. -Generating RTLIL representation for module `\IOBUFDS'. -Generating RTLIL representation for module `\IOBUFDS_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDSE3'. -Generating RTLIL representation for module `\OBUFDS'. -Generating RTLIL representation for module `\OBUFDS_DPHY'. -Generating RTLIL representation for module `\OBUFTDS'. -Generating RTLIL representation for module `\KEEPER'. -Generating RTLIL representation for module `\PULLDOWN'. -Generating RTLIL representation for module `\PULLUP'. -Generating RTLIL representation for module `\DCIRESET'. -Generating RTLIL representation for module `\HPIO_VREF'. -Generating RTLIL representation for module `\BUFGCE'. -Generating RTLIL representation for module `\BUFGCE_1'. -Generating RTLIL representation for module `\BUFGMUX'. -Generating RTLIL representation for module `\BUFGMUX_1'. -Generating RTLIL representation for module `\BUFGMUX_CTRL'. -Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. -Generating RTLIL representation for module `\BUFG_GT'. -Generating RTLIL representation for module `\BUFG_GT_SYNC'. -Generating RTLIL representation for module `\BUFG_PS'. -Generating RTLIL representation for module `\BUFGCE_DIV'. -Generating RTLIL representation for module `\BUFH'. -Generating RTLIL representation for module `\BUFIO2'. -Generating RTLIL representation for module `\BUFIO2_2CLK'. -Generating RTLIL representation for module `\BUFIO2FB'. -Generating RTLIL representation for module `\BUFPLL'. -Generating RTLIL representation for module `\BUFPLL_MCB'. -Generating RTLIL representation for module `\BUFIO'. -Generating RTLIL representation for module `\BUFIODQS'. -Generating RTLIL representation for module `\BUFR'. -Generating RTLIL representation for module `\BUFMR'. -Generating RTLIL representation for module `\BUFMRCE'. -Generating RTLIL representation for module `\DCM'. -Generating RTLIL representation for module `\DCM_SP'. -Generating RTLIL representation for module `\DCM_CLKGEN'. -Generating RTLIL representation for module `\DCM_ADV'. -Generating RTLIL representation for module `\DCM_BASE'. -Generating RTLIL representation for module `\DCM_PS'. -Generating RTLIL representation for module `\PMCD'. -Generating RTLIL representation for module `\PLL_ADV'. -Generating RTLIL representation for module `\PLL_BASE'. -Generating RTLIL representation for module `\MMCM_ADV'. -Generating RTLIL representation for module `\MMCM_BASE'. -Generating RTLIL representation for module `\MMCME2_ADV'. -Generating RTLIL representation for module `\MMCME2_BASE'. -Generating RTLIL representation for module `\PLLE2_ADV'. -Generating RTLIL representation for module `\PLLE2_BASE'. -Generating RTLIL representation for module `\MMCME3_ADV'. -Generating RTLIL representation for module `\MMCME3_BASE'. -Generating RTLIL representation for module `\PLLE3_ADV'. -Generating RTLIL representation for module `\PLLE3_BASE'. -Generating RTLIL representation for module `\MMCME4_ADV'. -Generating RTLIL representation for module `\MMCME4_BASE'. -Generating RTLIL representation for module `\PLLE4_ADV'. -Generating RTLIL representation for module `\PLLE4_BASE'. -Generating RTLIL representation for module `\BUFT'. -Generating RTLIL representation for module `\IN_FIFO'. -Generating RTLIL representation for module `\OUT_FIFO'. -Generating RTLIL representation for module `\HARD_SYNC'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. -Generating RTLIL representation for module `\STARTUP_SPARTAN6'. -Generating RTLIL representation for module `\STARTUP_VIRTEX4'. -Generating RTLIL representation for module `\STARTUP_VIRTEX5'. -Generating RTLIL representation for module `\STARTUP_VIRTEX6'. -Generating RTLIL representation for module `\STARTUPE2'. -Generating RTLIL representation for module `\STARTUPE3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. -Generating RTLIL representation for module `\CAPTUREE2'. -Generating RTLIL representation for module `\ICAP_SPARTAN3A'. -Generating RTLIL representation for module `\ICAP_SPARTAN6'. -Generating RTLIL representation for module `\ICAP_VIRTEX4'. -Generating RTLIL representation for module `\ICAP_VIRTEX5'. -Generating RTLIL representation for module `\ICAP_VIRTEX6'. -Generating RTLIL representation for module `\ICAPE2'. -Generating RTLIL representation for module `\ICAPE3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. -Generating RTLIL representation for module `\BSCAN_SPARTAN6'. -Generating RTLIL representation for module `\BSCAN_VIRTEX4'. -Generating RTLIL representation for module `\BSCAN_VIRTEX5'. -Generating RTLIL representation for module `\BSCAN_VIRTEX6'. -Generating RTLIL representation for module `\BSCANE2'. -Generating RTLIL representation for module `\DNA_PORT'. -Generating RTLIL representation for module `\DNA_PORTE2'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. -Generating RTLIL representation for module `\FRAME_ECCE2'. -Generating RTLIL representation for module `\FRAME_ECCE3'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. -Generating RTLIL representation for module `\USR_ACCESSE2'. -Generating RTLIL representation for module `\POST_CRC_INTERNAL'. -Generating RTLIL representation for module `\SUSPEND_SYNC'. -Generating RTLIL representation for module `\KEY_CLEAR'. -Generating RTLIL representation for module `\MASTER_JTAG'. -Generating RTLIL representation for module `\SPI_ACCESS'. -Generating RTLIL representation for module `\EFUSE_USR'. -Generating RTLIL representation for module `\SYSMON'. -Generating RTLIL representation for module `\XADC'. -Generating RTLIL representation for module `\SYSMONE1'. -Generating RTLIL representation for module `\SYSMONE4'. -Generating RTLIL representation for module `\GTPA1_DUAL'. -Generating RTLIL representation for module `\GT11_CUSTOM'. -Generating RTLIL representation for module `\GT11_DUAL'. -Generating RTLIL representation for module `\GT11CLK'. -Generating RTLIL representation for module `\GT11CLK_MGT'. -Generating RTLIL representation for module `\GTP_DUAL'. -Generating RTLIL representation for module `\GTX_DUAL'. -Generating RTLIL representation for module `\CRC32'. -Generating RTLIL representation for module `\CRC64'. -Generating RTLIL representation for module `\GTHE1_QUAD'. -Generating RTLIL representation for module `\GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTHE1'. -Generating RTLIL representation for module `\GTHE2_CHANNEL'. -Generating RTLIL representation for module `\GTHE2_COMMON'. -Generating RTLIL representation for module `\GTPE2_CHANNEL'. -Generating RTLIL representation for module `\GTPE2_COMMON'. -Generating RTLIL representation for module `\GTXE2_CHANNEL'. -Generating RTLIL representation for module `\GTXE2_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE2'. -Generating RTLIL representation for module `\GTHE3_CHANNEL'. -Generating RTLIL representation for module `\GTHE3_COMMON'. -Generating RTLIL representation for module `\GTHE4_CHANNEL'. -Generating RTLIL representation for module `\GTHE4_COMMON'. -Generating RTLIL representation for module `\GTYE3_CHANNEL'. -Generating RTLIL representation for module `\GTYE3_COMMON'. -Generating RTLIL representation for module `\GTYE4_CHANNEL'. -Generating RTLIL representation for module `\GTYE4_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE3'. -Generating RTLIL representation for module `\IBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE3'. -Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. -Generating RTLIL representation for module `\OBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. -Generating RTLIL representation for module `\PCIE_A1'. -Generating RTLIL representation for module `\PCIE_EP'. -Generating RTLIL representation for module `\PCIE_2_0'. -Generating RTLIL representation for module `\PCIE_2_1'. -Generating RTLIL representation for module `\PCIE_3_0'. -Generating RTLIL representation for module `\PCIE_3_1'. -Generating RTLIL representation for module `\PCIE40E4'. -Generating RTLIL representation for module `\EMAC'. -Generating RTLIL representation for module `\TEMAC'. -Generating RTLIL representation for module `\TEMAC_SINGLE'. -Generating RTLIL representation for module `\CMAC'. -Generating RTLIL representation for module `\CMACE4'. -Generating RTLIL representation for module `\PPC405_ADV'. -Generating RTLIL representation for module `\PPC440'. -Generating RTLIL representation for module `\MCB'. -Generating RTLIL representation for module `\PS7'. -Generating RTLIL representation for module `\PS8'. -Generating RTLIL representation for module `\ILKN'. -Generating RTLIL representation for module `\ILKNE4'. -Successfully finished Verilog frontend. - -3.3. Executing HIERARCHY pass (managing design hierarchy). - -3.3.1. Analyzing design hierarchy.. -Top module: \block_ram - -3.3.2. Analyzing design hierarchy.. -Top module: \block_ram -Removed 0 unused modules. - -3.4. Executing PROC pass (convert processes to netlists). - -3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 1 assignment to connection. - -3.4.4. Executing PROC_INIT pass (extract init attributes). - -3.4.5. Executing PROC_ARST pass (detect async resets in processes). - -3.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\block_ram.$proc$attributes_test.v:14$2'. - 1/3: $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 - 2/3: $0$memwr$\memory$attributes_test.v:16$1_DATA[3:0]$4 - 3/3: $0$memwr$\memory$attributes_test.v:16$1_ADDR[9:0]$3 - -3.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). - -3.4.8. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\block_ram.\data_out_r' using process `\block_ram.$proc$attributes_test.v:14$2'. - created $dff cell `$procdff$48' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_ADDR' using process `\block_ram.$proc$attributes_test.v:14$2'. - created $dff cell `$procdff$49' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_DATA' using process `\block_ram.$proc$attributes_test.v:14$2'. - created $dff cell `$procdff$50' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_EN' using process `\block_ram.$proc$attributes_test.v:14$2'. - created $dff cell `$procdff$51' with positive edge clock. - -3.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\block_ram.$proc$attributes_test.v:14$2'. -Removing empty process `block_ram.$proc$attributes_test.v:14$2'. -Cleaned up 1 empty switch. - -3.5. Executing TRIBUF pass. - -3.6. Executing DEMINOUT pass (demote inout ports to input or output). - -3.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 7 unused wires. - - -3.9. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -found and reported 0 problems. - -3.10. Executing OPT pass (performing simple optimizations). - -3.10.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.10.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. - Consolidated identical input bits for $mux cell $procmux$42: - Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] - New connections: $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [3:1] = { $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] } - Optimizing cells in module \block_ram. -Performed a total of 1 changes. - -3.10.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.10.6. Executing OPT_RMDFF pass (remove dff with constant values). - -3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.10.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.10.9. Rerunning OPT passes. (Maybe there is more to do..) - -3.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -3.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -3.10.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.10.13. Executing OPT_RMDFF pass (remove dff with constant values). - -3.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.10.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.10.16. Finished OPT passes. (There is nothing left to do.) - -3.11. Executing WREDUCE pass (reducing word size of cells). -Removed cell block_ram.$procmux$44 ($mux). -Removed cell block_ram.$procmux$46 ($mux). -Removed top 3 bits (of 4) from FF cell block_ram.$procdff$51 ($dff). - -3.12. Executing PEEPOPT pass (run peephole optimizers). - -3.13. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 2 unused wires. - - -3.14. Executing PMUX2SHIFTX pass. - -3.15. Executing TECHMAP pass (map to technology primitives). - -3.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. -Generating RTLIL representation for module `\_90_lut_cmp_'. -Successfully finished Verilog frontend. - -3.15.2. Continuing TECHMAP pass. -No more expansions possible. - -3.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). -Checking cell `$memwr$\memory$attributes_test.v:16$7' in module `\block_ram': merged $dff to cell. -Checking cell `$memrd$\memory$attributes_test.v:17$6' in module `\block_ram': merged data $dff to cell. - -3.17. Executing TECHMAP pass (map to technology primitives). - -3.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. -Generating RTLIL representation for module `\_80_mul'. -Generating RTLIL representation for module `\_90_soft_mul'. -Successfully finished Verilog frontend. - -3.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. -Generating RTLIL representation for module `\$__MUL25X18'. -Successfully finished Verilog frontend. - -3.17.3. Continuing TECHMAP pass. -No more expansions possible. - -3.18. Executing OPT_EXPR pass (perform const folding). - -3.19. Executing WREDUCE pass (reducing word size of cells). - -3.20. Executing XILINX_DSP pass (pack resources into DSPs). - -3.21. Executing ALUMACC pass (create $alu and $macc cells). -Extracting $alu and $macc cells in module block_ram: - created 0 $alu and 0 $macc cells. - -3.22. Executing SHARE pass (SAT-based resource sharing). - -3.23. Executing OPT pass (performing simple optimizations). - -3.23.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.23.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -3.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -3.23.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.23.6. Executing OPT_RMDFF pass (remove dff with constant values). - -3.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 4 unused cells and 5 unused wires. - - -3.23.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.23.9. Rerunning OPT passes. (Maybe there is more to do..) - -3.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -3.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -3.23.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.23.13. Executing OPT_RMDFF pass (remove dff with constant values). - -3.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.23.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.23.16. Finished OPT passes. (There is nothing left to do.) - -3.24. Executing FSM pass (extract and optimize FSM). - -3.24.1. Executing FSM_DETECT pass (finding FSMs in design). - -3.24.2. Executing FSM_EXTRACT pass (extracting FSM from design). - -3.24.3. Executing FSM_OPT pass (simple optimizations of FSMs). - -3.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.24.5. Executing FSM_OPT pass (simple optimizations of FSMs). - -3.24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). - -3.24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). - -3.24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). - -3.25. Executing OPT pass (performing simple optimizations). - -3.25.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.25.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.25.3. Executing OPT_RMDFF pass (remove dff with constant values). - -3.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.25.5. Finished fast OPT passes. - -3.26. Executing MEMORY pass. - -3.26.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. - -3.26.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). - -3.26.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.26.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). - -3.26.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.26.6. Executing MEMORY_COLLECT pass (generating $mem cells). -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\block_ram': - $memwr$\memory$attributes_test.v:16$7 ($memwr) - $memrd$\memory$attributes_test.v:17$6 ($memrd) - -3.27. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). -Processing block_ram.memory: - Properties: ports=2 bits=4096 rports=1 wports=1 dbits=4 abits=10 words=1024 - Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): - Bram geometry: abits=9 dbits=72 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_SDP: awaste=0 dwaste=68 bwaste=34816 waste=34816 efficiency=5 - Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) accepted. - Mapping to bram type $__XILINX_RAMB36_SDP (variant 1): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=34816 efficiency=5 - Storing for later selection. - Checking rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1): - Bram geometry: abits=9 dbits=36 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_SDP: awaste=0 dwaste=32 bwaste=16384 waste=16384 efficiency=11 - Rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1) accepted. - Mapping to bram type $__XILINX_RAMB18_SDP (variant 1): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=16384 efficiency=11 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1): - Bram geometry: abits=10 dbits=36 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=0 dwaste=32 bwaste=32768 waste=32768 efficiency=11 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 1): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=32768 efficiency=11 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2): - Bram geometry: abits=11 dbits=18 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=1024 dwaste=14 bwaste=32768 waste=32768 efficiency=11 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 2): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=32768 efficiency=11 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3): - Bram geometry: abits=12 dbits=9 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=3072 dwaste=5 bwaste=32768 waste=32768 efficiency=11 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 3): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=32768 efficiency=11 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4): - Bram geometry: abits=13 dbits=4 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=7168 dwaste=0 bwaste=28672 waste=28672 efficiency=12 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 4): - Shuffle bit order to accommodate enable buckets of size 4.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=28672 efficiency=12 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5): - Bram geometry: abits=14 dbits=2 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=15360 dwaste=0 bwaste=30720 waste=30720 efficiency=6 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 5): - Shuffle bit order to accommodate enable buckets of size 2.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=30720 efficiency=6 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6): - Bram geometry: abits=15 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=31744 dwaste=0 bwaste=31744 waste=31744 efficiency=3 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1): - Bram geometry: abits=10 dbits=18 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=0 dwaste=14 bwaste=14336 waste=14336 efficiency=22 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 1): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=14336 efficiency=22 - Storing for later selection. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2): - Bram geometry: abits=11 dbits=9 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=1024 dwaste=5 bwaste=14336 waste=14336 efficiency=22 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 2): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=14336 efficiency=22 - Storing for later selection. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3): - Bram geometry: abits=12 dbits=4 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 3): - Shuffle bit order to accommodate enable buckets of size 4.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=12288 efficiency=25 - Storing for later selection. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4): - Bram geometry: abits=13 dbits=2 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 4): - Shuffle bit order to accommodate enable buckets of size 2.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=14336 efficiency=12 - Storing for later selection. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5): - Bram geometry: abits=14 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 5): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=15360 efficiency=6 - Storing for later selection. - Selecting best of 12 rules: - Efficiency for rule 4.5: efficiency=6, cells=4, acells=1 - Efficiency for rule 4.4: efficiency=12, cells=2, acells=1 - Efficiency for rule 4.3: efficiency=25, cells=1, acells=1 - Efficiency for rule 4.2: efficiency=22, cells=1, acells=1 - Efficiency for rule 4.1: efficiency=22, cells=1, acells=1 - Efficiency for rule 3.5: efficiency=6, cells=2, acells=1 - Efficiency for rule 3.4: efficiency=12, cells=1, acells=1 - Efficiency for rule 3.3: efficiency=11, cells=1, acells=1 - Efficiency for rule 3.2: efficiency=11, cells=1, acells=1 - Efficiency for rule 3.1: efficiency=11, cells=1, acells=1 - Efficiency for rule 2.1: efficiency=11, cells=2, acells=2 - Efficiency for rule 1.1: efficiency=5, cells=2, acells=2 - Selected rule 4.3 with efficiency 25. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 3): - Shuffle bit order to accommodate enable buckets of size 4.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Creating $__XILINX_RAMB18_TDP cell at grid position <0 0 0>: memory.0.0.0 - -3.29. Executing TECHMAP pass (map to technology primitives). - -3.29.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v' to AST representation. -Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. -Successfully finished Verilog frontend. - -3.29.2. Continuing TECHMAP pass. -Using template $paramod\$__XILINX_RAMB18_TDP\CFG_ABITS=12\CFG_DBITS=4\CFG_ENABLE_B=1\CLKPOL2=1\CLKPOL3=1 for cells of type $__XILINX_RAMB18_TDP. -No more expansions possible. - - -3.30. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). - -3.31. Executing TECHMAP pass (map to technology primitives). - -3.31.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v' to AST representation. -Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. -Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. -Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. -Successfully finished Verilog frontend. - -3.31.2. Continuing TECHMAP pass. -No more expansions possible. - -3.32. Executing OPT pass (performing simple optimizations). - -3.32.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - - -3.32.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.32.3. Executing OPT_RMDFF pass (remove dff with constant values). - -3.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 17 unused wires. - - -3.32.5. Finished fast OPT passes. - -3.33. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). - -3.34. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). - -3.35. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). -Transforming FF to FF+Enable cells in module block_ram: - -3.36. Executing OPT pass (performing simple optimizations). - -3.36.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.36.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -3.36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -3.36.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.36.6. Executing OPT_SHARE pass. - -3.36.7. Executing OPT_RMDFF pass (remove dff with constant values). - -3.36.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.36.9. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.36.10. Finished OPT passes. (There is nothing left to do.) - -3.37. Executing XILINX_SRL pass (Xilinx shift register extraction). - -3.38. Executing TECHMAP pass (map to technology primitives). - -3.38.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -3.38.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v' to AST representation. -Generating RTLIL representation for module `\_80_xilinx_lcu'. -Generating RTLIL representation for module `\_80_xilinx_alu'. -Successfully finished Verilog frontend. - -3.38.3. Continuing TECHMAP pass. -No more expansions possible. - -3.39. Executing OPT pass (performing simple optimizations). - -3.39.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.39.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.39.3. Executing OPT_RMDFF pass (remove dff with constant values). - -3.39.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.39.5. Finished fast OPT passes. - -3.40. Executing TECHMAP pass (map to technology primitives). - -3.40.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -3.40.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. -Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. -Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. -Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. -Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. -Generating RTLIL representation for module `\$__SHREG_'. -Generating RTLIL representation for module `\$__XILINX_SHREG_'. -Generating RTLIL representation for module `\$__XILINX_MUXF78'. -Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. -Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. -Successfully finished Verilog frontend. - -3.40.3. Continuing TECHMAP pass. -No more expansions possible. - -3.41. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.42. Executing ABC pass (technology mapping using ABC). - -3.42.1. Extracting gate netlist of module `\block_ram' to `/input.blif'.. -Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. -Don't call ABC as there is nothing to map. -Removing temp directory. - -3.43. Executing XILINX_SRL pass (Xilinx shift register extraction). - -3.44. Executing TECHMAP pass (map to technology primitives). - -3.44.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v' to AST representation. -Generating RTLIL representation for module `\$lut'. -Successfully finished Verilog frontend. - -3.44.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. -Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. -Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. -Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. -Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. -Generating RTLIL representation for module `\$__SHREG_'. -Generating RTLIL representation for module `\$__XILINX_SHREG_'. -Generating RTLIL representation for module `\$__XILINX_MUXF78'. -Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. -Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. -Successfully finished Verilog frontend. - -3.44.3. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v' to AST representation. -Generating RTLIL representation for module `\$_DFF_N_'. -Generating RTLIL representation for module `\$_DFF_P_'. -Generating RTLIL representation for module `\$_DFFE_NP_'. -Generating RTLIL representation for module `\$_DFFE_PP_'. -Generating RTLIL representation for module `\$_DFF_NN0_'. -Generating RTLIL representation for module `\$_DFF_NP0_'. -Generating RTLIL representation for module `\$_DFF_PN0_'. -Generating RTLIL representation for module `\$_DFF_PP0_'. -Generating RTLIL representation for module `\$_DFF_NN1_'. -Generating RTLIL representation for module `\$_DFF_NP1_'. -Generating RTLIL representation for module `\$_DFF_PN1_'. -Generating RTLIL representation for module `\$_DFF_PP1_'. -Generating RTLIL representation for module `\$_DLATCH_N_'. -Generating RTLIL representation for module `\$_DLATCH_P_'. -Successfully finished Verilog frontend. - -3.44.4. Continuing TECHMAP pass. -No more expansions possible. - -3.45. Executing CLKBUFMAP pass (inserting global clock buffers). -Inserting BUFG on block_ram.clk[0]. - -3.46. Executing HIERARCHY pass (managing design hierarchy). - -3.46.1. Analyzing design hierarchy.. -Top module: \block_ram - -3.46.2. Analyzing design hierarchy.. -Top module: \block_ram -Removed 0 unused modules. - -3.47. Printing statistics. - -=== block_ram === - - Number of wires: 12 - Number of wire bits: 62 - Number of public wires: 6 - Number of public wire bits: 24 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 2 - BUFG 1 - RAMB18E1 1 - - Estimated number of LCs: 0 - -3.48. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -found and reported 0 problems. - -4. Executing Verilog-2005 frontend: attributes_test.v -Parsing Verilog input from `attributes_test.v' to AST representation. -Generating RTLIL representation for module `\block_ram'. -Generating RTLIL representation for module `\distributed_ram'. -Generating RTLIL representation for module `\distributed_ram_manual'. -Generating RTLIL representation for module `\distributed_ram_manual_syn'. -Successfully finished Verilog frontend. - -5. Executing HIERARCHY pass (managing design hierarchy). - -5.1. Analyzing design hierarchy.. -Top module: \distributed_ram - -5.2. Analyzing design hierarchy.. -Top module: \distributed_ram -Removing unused module `\distributed_ram_manual_syn'. -Removing unused module `\distributed_ram_manual'. -Removing unused module `\block_ram'. -Removed 3 unused modules. - -6. Executing SYNTH_XILINX pass. - -6.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. -Generating RTLIL representation for module `\VCC'. -Generating RTLIL representation for module `\GND'. -Generating RTLIL representation for module `\IBUF'. -Generating RTLIL representation for module `\IBUFG'. -Generating RTLIL representation for module `\OBUF'. -Generating RTLIL representation for module `\IOBUF'. -Generating RTLIL representation for module `\OBUFT'. -Generating RTLIL representation for module `\BUFG'. -Generating RTLIL representation for module `\BUFGCTRL'. -Generating RTLIL representation for module `\BUFHCE'. -Generating RTLIL representation for module `\INV'. -Generating RTLIL representation for module `\LUT1'. -Generating RTLIL representation for module `\LUT2'. -Generating RTLIL representation for module `\LUT3'. -Generating RTLIL representation for module `\LUT4'. -Generating RTLIL representation for module `\LUT5'. -Generating RTLIL representation for module `\LUT6'. -Generating RTLIL representation for module `\LUT6_2'. -Generating RTLIL representation for module `\MUXCY'. -Generating RTLIL representation for module `\MUXF7'. -Generating RTLIL representation for module `\MUXF8'. -Generating RTLIL representation for module `\XORCY'. -Generating RTLIL representation for module `\CARRY4'. -Generating RTLIL representation for module `\FDRE'. -Generating RTLIL representation for module `\FDSE'. -Generating RTLIL representation for module `\FDCE'. -Generating RTLIL representation for module `\FDPE'. -Generating RTLIL representation for module `\FDRE_1'. -Generating RTLIL representation for module `\FDSE_1'. -Generating RTLIL representation for module `\FDCE_1'. -Generating RTLIL representation for module `\FDPE_1'. -Generating RTLIL representation for module `\LDCE'. -Generating RTLIL representation for module `\LDPE'. -Generating RTLIL representation for module `\RAM16X1S'. -Generating RTLIL representation for module `\RAM16X1S_1'. -Generating RTLIL representation for module `\RAM32X1S'. -Generating RTLIL representation for module `\RAM32X1S_1'. -Generating RTLIL representation for module `\RAM64X1S'. -Generating RTLIL representation for module `\RAM64X1S_1'. -Generating RTLIL representation for module `\RAM128X1S'. -Generating RTLIL representation for module `\RAM128X1S_1'. -Generating RTLIL representation for module `\RAM256X1S'. -Generating RTLIL representation for module `\RAM512X1S'. -Generating RTLIL representation for module `\RAM16X2S'. -Generating RTLIL representation for module `\RAM32X2S'. -Generating RTLIL representation for module `\RAM64X2S'. -Generating RTLIL representation for module `\RAM16X4S'. -Generating RTLIL representation for module `\RAM32X4S'. -Generating RTLIL representation for module `\RAM16X8S'. -Generating RTLIL representation for module `\RAM32X8S'. -Generating RTLIL representation for module `\RAM16X1D'. -Generating RTLIL representation for module `\RAM16X1D_1'. -Generating RTLIL representation for module `\RAM32X1D'. -Generating RTLIL representation for module `\RAM32X1D_1'. -Generating RTLIL representation for module `\RAM64X1D'. -Generating RTLIL representation for module `\RAM64X1D_1'. -Generating RTLIL representation for module `\RAM128X1D'. -Generating RTLIL representation for module `\RAM256X1D'. -Generating RTLIL representation for module `\RAM32M'. -Generating RTLIL representation for module `\RAM32M16'. -Generating RTLIL representation for module `\RAM64M'. -Generating RTLIL representation for module `\RAM64M8'. -Generating RTLIL representation for module `\ROM16X1'. -Generating RTLIL representation for module `\ROM32X1'. -Generating RTLIL representation for module `\ROM64X1'. -Generating RTLIL representation for module `\ROM128X1'. -Generating RTLIL representation for module `\ROM256X1'. -Generating RTLIL representation for module `\SRL16E'. -Generating RTLIL representation for module `\SRLC16E'. -Generating RTLIL representation for module `\SRLC32E'. -Generating RTLIL representation for module `\MULT18X18'. -Generating RTLIL representation for module `\MULT18X18S'. -Generating RTLIL representation for module `\MULT18X18SIO'. -Generating RTLIL representation for module `\DSP48A'. -Generating RTLIL representation for module `\DSP48A1'. -Generating RTLIL representation for module `\DSP48E1'. -Successfully finished Verilog frontend. - -6.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. -Generating RTLIL representation for module `\FDCPE'. -Generating RTLIL representation for module `\FDRSE'. -Generating RTLIL representation for module `\LDCPE'. -Generating RTLIL representation for module `\AND2B1L'. -Generating RTLIL representation for module `\OR2L'. -Generating RTLIL representation for module `\MUXF5'. -Generating RTLIL representation for module `\MUXF6'. -Generating RTLIL representation for module `\MUXF9'. -Generating RTLIL representation for module `\CARRY8'. -Generating RTLIL representation for module `\ORCY'. -Generating RTLIL representation for module `\MULT_AND'. -Generating RTLIL representation for module `\SRL16'. -Generating RTLIL representation for module `\SRLC16'. -Generating RTLIL representation for module `\CFGLUT5'. -Generating RTLIL representation for module `\RAMB16_S1'. -Generating RTLIL representation for module `\RAMB16_S2'. -Generating RTLIL representation for module `\RAMB16_S4'. -Generating RTLIL representation for module `\RAMB16_S9'. -Generating RTLIL representation for module `\RAMB16_S18'. -Generating RTLIL representation for module `\RAMB16_S36'. -Generating RTLIL representation for module `\RAMB16_S1_S1'. -Generating RTLIL representation for module `\RAMB16_S1_S2'. -Generating RTLIL representation for module `\RAMB16_S1_S4'. -Generating RTLIL representation for module `\RAMB16_S1_S9'. -Generating RTLIL representation for module `\RAMB16_S1_S18'. -Generating RTLIL representation for module `\RAMB16_S1_S36'. -Generating RTLIL representation for module `\RAMB16_S2_S2'. -Generating RTLIL representation for module `\RAMB16_S2_S4'. -Generating RTLIL representation for module `\RAMB16_S2_S9'. -Generating RTLIL representation for module `\RAMB16_S2_S18'. -Generating RTLIL representation for module `\RAMB16_S2_S36'. -Generating RTLIL representation for module `\RAMB16_S4_S4'. -Generating RTLIL representation for module `\RAMB16_S4_S9'. -Generating RTLIL representation for module `\RAMB16_S4_S18'. -Generating RTLIL representation for module `\RAMB16_S4_S36'. -Generating RTLIL representation for module `\RAMB16_S9_S9'. -Generating RTLIL representation for module `\RAMB16_S9_S18'. -Generating RTLIL representation for module `\RAMB16_S9_S36'. -Generating RTLIL representation for module `\RAMB16_S18_S18'. -Generating RTLIL representation for module `\RAMB16_S18_S36'. -Generating RTLIL representation for module `\RAMB16_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWER'. -Generating RTLIL representation for module `\RAMB8BWER'. -Generating RTLIL representation for module `\FIFO16'. -Generating RTLIL representation for module `\RAMB16'. -Generating RTLIL representation for module `\RAMB32_S64_ECC'. -Generating RTLIL representation for module `\FIFO18'. -Generating RTLIL representation for module `\FIFO18_36'. -Generating RTLIL representation for module `\FIFO36'. -Generating RTLIL representation for module `\FIFO36_72'. -Generating RTLIL representation for module `\RAMB18'. -Generating RTLIL representation for module `\RAMB36'. -Generating RTLIL representation for module `\RAMB18SDP'. -Generating RTLIL representation for module `\RAMB36SDP'. -Generating RTLIL representation for module `\FIFO18E1'. -Generating RTLIL representation for module `\FIFO36E1'. -Generating RTLIL representation for module `\RAMB18E1'. -Generating RTLIL representation for module `\RAMB36E1'. -Generating RTLIL representation for module `\FIFO18E2'. -Generating RTLIL representation for module `\FIFO36E2'. -Generating RTLIL representation for module `\RAMB18E2'. -Generating RTLIL representation for module `\RAMB36E2'. -Generating RTLIL representation for module `\URAM288'. -Generating RTLIL representation for module `\URAM288_BASE'. -Generating RTLIL representation for module `\DSP48'. -Generating RTLIL representation for module `\DSP48E'. -Generating RTLIL representation for module `\DSP48E2'. -Generating RTLIL representation for module `\IFDDRCPE'. -Generating RTLIL representation for module `\IFDDRRSE'. -Generating RTLIL representation for module `\OFDDRCPE'. -Generating RTLIL representation for module `\OFDDRRSE'. -Generating RTLIL representation for module `\OFDDRTCPE'. -Generating RTLIL representation for module `\OFDDRTRSE'. -Generating RTLIL representation for module `\IDDR2'. -Generating RTLIL representation for module `\ODDR2'. -Generating RTLIL representation for module `\IDDR'. -Generating RTLIL representation for module `\IDDR_2CLK'. -Generating RTLIL representation for module `\ODDR'. -Generating RTLIL representation for module `\IDELAYCTRL'. -Generating RTLIL representation for module `\IDELAY'. -Generating RTLIL representation for module `\ISERDES'. -Generating RTLIL representation for module `\OSERDES'. -Generating RTLIL representation for module `\IODELAY'. -Generating RTLIL representation for module `\ISERDES_NODELAY'. -Generating RTLIL representation for module `\IODELAYE1'. -Generating RTLIL representation for module `\ISERDESE1'. -Generating RTLIL representation for module `\OSERDESE1'. -Generating RTLIL representation for module `\IDELAYE2'. -Generating RTLIL representation for module `\ODELAYE2'. -Generating RTLIL representation for module `\ISERDESE2'. -Generating RTLIL representation for module `\OSERDESE2'. -Generating RTLIL representation for module `\PHASER_IN'. -Generating RTLIL representation for module `\PHASER_IN_PHY'. -Generating RTLIL representation for module `\PHASER_OUT'. -Generating RTLIL representation for module `\PHASER_OUT_PHY'. -Generating RTLIL representation for module `\PHASER_REF'. -Generating RTLIL representation for module `\PHY_CONTROL'. -Generating RTLIL representation for module `\IDDRE1'. -Generating RTLIL representation for module `\ODDRE1'. -Generating RTLIL representation for module `\IDELAYE3'. -Generating RTLIL representation for module `\ODELAYE3'. -Generating RTLIL representation for module `\ISERDESE3'. -Generating RTLIL representation for module `\OSERDESE3'. -Generating RTLIL representation for module `\BITSLICE_CONTROL'. -Generating RTLIL representation for module `\RIU_OR'. -Generating RTLIL representation for module `\RX_BITSLICE'. -Generating RTLIL representation for module `\RXTX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE_TRI'. -Generating RTLIL representation for module `\IODELAY2'. -Generating RTLIL representation for module `\IODRP2'. -Generating RTLIL representation for module `\IODRP2_MCB'. -Generating RTLIL representation for module `\ISERDES2'. -Generating RTLIL representation for module `\OSERDES2'. -Generating RTLIL representation for module `\IBUF_DLY_ADJ'. -Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUF_ANALOG'. -Generating RTLIL representation for module `\IBUFE3'. -Generating RTLIL representation for module `\IBUFDS'. -Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. -Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDSE3'. -Generating RTLIL representation for module `\IBUFDS_DPHY'. -Generating RTLIL representation for module `\IBUFGDS'. -Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUF_DCIEN'. -Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFE3'. -Generating RTLIL representation for module `\IOBUFDS'. -Generating RTLIL representation for module `\IOBUFDS_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDSE3'. -Generating RTLIL representation for module `\OBUFDS'. -Generating RTLIL representation for module `\OBUFDS_DPHY'. -Generating RTLIL representation for module `\OBUFTDS'. -Generating RTLIL representation for module `\KEEPER'. -Generating RTLIL representation for module `\PULLDOWN'. -Generating RTLIL representation for module `\PULLUP'. -Generating RTLIL representation for module `\DCIRESET'. -Generating RTLIL representation for module `\HPIO_VREF'. -Generating RTLIL representation for module `\BUFGCE'. -Generating RTLIL representation for module `\BUFGCE_1'. -Generating RTLIL representation for module `\BUFGMUX'. -Generating RTLIL representation for module `\BUFGMUX_1'. -Generating RTLIL representation for module `\BUFGMUX_CTRL'. -Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. -Generating RTLIL representation for module `\BUFG_GT'. -Generating RTLIL representation for module `\BUFG_GT_SYNC'. -Generating RTLIL representation for module `\BUFG_PS'. -Generating RTLIL representation for module `\BUFGCE_DIV'. -Generating RTLIL representation for module `\BUFH'. -Generating RTLIL representation for module `\BUFIO2'. -Generating RTLIL representation for module `\BUFIO2_2CLK'. -Generating RTLIL representation for module `\BUFIO2FB'. -Generating RTLIL representation for module `\BUFPLL'. -Generating RTLIL representation for module `\BUFPLL_MCB'. -Generating RTLIL representation for module `\BUFIO'. -Generating RTLIL representation for module `\BUFIODQS'. -Generating RTLIL representation for module `\BUFR'. -Generating RTLIL representation for module `\BUFMR'. -Generating RTLIL representation for module `\BUFMRCE'. -Generating RTLIL representation for module `\DCM'. -Generating RTLIL representation for module `\DCM_SP'. -Generating RTLIL representation for module `\DCM_CLKGEN'. -Generating RTLIL representation for module `\DCM_ADV'. -Generating RTLIL representation for module `\DCM_BASE'. -Generating RTLIL representation for module `\DCM_PS'. -Generating RTLIL representation for module `\PMCD'. -Generating RTLIL representation for module `\PLL_ADV'. -Generating RTLIL representation for module `\PLL_BASE'. -Generating RTLIL representation for module `\MMCM_ADV'. -Generating RTLIL representation for module `\MMCM_BASE'. -Generating RTLIL representation for module `\MMCME2_ADV'. -Generating RTLIL representation for module `\MMCME2_BASE'. -Generating RTLIL representation for module `\PLLE2_ADV'. -Generating RTLIL representation for module `\PLLE2_BASE'. -Generating RTLIL representation for module `\MMCME3_ADV'. -Generating RTLIL representation for module `\MMCME3_BASE'. -Generating RTLIL representation for module `\PLLE3_ADV'. -Generating RTLIL representation for module `\PLLE3_BASE'. -Generating RTLIL representation for module `\MMCME4_ADV'. -Generating RTLIL representation for module `\MMCME4_BASE'. -Generating RTLIL representation for module `\PLLE4_ADV'. -Generating RTLIL representation for module `\PLLE4_BASE'. -Generating RTLIL representation for module `\BUFT'. -Generating RTLIL representation for module `\IN_FIFO'. -Generating RTLIL representation for module `\OUT_FIFO'. -Generating RTLIL representation for module `\HARD_SYNC'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. -Generating RTLIL representation for module `\STARTUP_SPARTAN6'. -Generating RTLIL representation for module `\STARTUP_VIRTEX4'. -Generating RTLIL representation for module `\STARTUP_VIRTEX5'. -Generating RTLIL representation for module `\STARTUP_VIRTEX6'. -Generating RTLIL representation for module `\STARTUPE2'. -Generating RTLIL representation for module `\STARTUPE3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. -Generating RTLIL representation for module `\CAPTUREE2'. -Generating RTLIL representation for module `\ICAP_SPARTAN3A'. -Generating RTLIL representation for module `\ICAP_SPARTAN6'. -Generating RTLIL representation for module `\ICAP_VIRTEX4'. -Generating RTLIL representation for module `\ICAP_VIRTEX5'. -Generating RTLIL representation for module `\ICAP_VIRTEX6'. -Generating RTLIL representation for module `\ICAPE2'. -Generating RTLIL representation for module `\ICAPE3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. -Generating RTLIL representation for module `\BSCAN_SPARTAN6'. -Generating RTLIL representation for module `\BSCAN_VIRTEX4'. -Generating RTLIL representation for module `\BSCAN_VIRTEX5'. -Generating RTLIL representation for module `\BSCAN_VIRTEX6'. -Generating RTLIL representation for module `\BSCANE2'. -Generating RTLIL representation for module `\DNA_PORT'. -Generating RTLIL representation for module `\DNA_PORTE2'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. -Generating RTLIL representation for module `\FRAME_ECCE2'. -Generating RTLIL representation for module `\FRAME_ECCE3'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. -Generating RTLIL representation for module `\USR_ACCESSE2'. -Generating RTLIL representation for module `\POST_CRC_INTERNAL'. -Generating RTLIL representation for module `\SUSPEND_SYNC'. -Generating RTLIL representation for module `\KEY_CLEAR'. -Generating RTLIL representation for module `\MASTER_JTAG'. -Generating RTLIL representation for module `\SPI_ACCESS'. -Generating RTLIL representation for module `\EFUSE_USR'. -Generating RTLIL representation for module `\SYSMON'. -Generating RTLIL representation for module `\XADC'. -Generating RTLIL representation for module `\SYSMONE1'. -Generating RTLIL representation for module `\SYSMONE4'. -Generating RTLIL representation for module `\GTPA1_DUAL'. -Generating RTLIL representation for module `\GT11_CUSTOM'. -Generating RTLIL representation for module `\GT11_DUAL'. -Generating RTLIL representation for module `\GT11CLK'. -Generating RTLIL representation for module `\GT11CLK_MGT'. -Generating RTLIL representation for module `\GTP_DUAL'. -Generating RTLIL representation for module `\GTX_DUAL'. -Generating RTLIL representation for module `\CRC32'. -Generating RTLIL representation for module `\CRC64'. -Generating RTLIL representation for module `\GTHE1_QUAD'. -Generating RTLIL representation for module `\GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTHE1'. -Generating RTLIL representation for module `\GTHE2_CHANNEL'. -Generating RTLIL representation for module `\GTHE2_COMMON'. -Generating RTLIL representation for module `\GTPE2_CHANNEL'. -Generating RTLIL representation for module `\GTPE2_COMMON'. -Generating RTLIL representation for module `\GTXE2_CHANNEL'. -Generating RTLIL representation for module `\GTXE2_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE2'. -Generating RTLIL representation for module `\GTHE3_CHANNEL'. -Generating RTLIL representation for module `\GTHE3_COMMON'. -Generating RTLIL representation for module `\GTHE4_CHANNEL'. -Generating RTLIL representation for module `\GTHE4_COMMON'. -Generating RTLIL representation for module `\GTYE3_CHANNEL'. -Generating RTLIL representation for module `\GTYE3_COMMON'. -Generating RTLIL representation for module `\GTYE4_CHANNEL'. -Generating RTLIL representation for module `\GTYE4_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE3'. -Generating RTLIL representation for module `\IBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE3'. -Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. -Generating RTLIL representation for module `\OBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. -Generating RTLIL representation for module `\PCIE_A1'. -Generating RTLIL representation for module `\PCIE_EP'. -Generating RTLIL representation for module `\PCIE_2_0'. -Generating RTLIL representation for module `\PCIE_2_1'. -Generating RTLIL representation for module `\PCIE_3_0'. -Generating RTLIL representation for module `\PCIE_3_1'. -Generating RTLIL representation for module `\PCIE40E4'. -Generating RTLIL representation for module `\EMAC'. -Generating RTLIL representation for module `\TEMAC'. -Generating RTLIL representation for module `\TEMAC_SINGLE'. -Generating RTLIL representation for module `\CMAC'. -Generating RTLIL representation for module `\CMACE4'. -Generating RTLIL representation for module `\PPC405_ADV'. -Generating RTLIL representation for module `\PPC440'. -Generating RTLIL representation for module `\MCB'. -Generating RTLIL representation for module `\PS7'. -Generating RTLIL representation for module `\PS8'. -Generating RTLIL representation for module `\ILKN'. -Generating RTLIL representation for module `\ILKNE4'. -Successfully finished Verilog frontend. - -6.3. Executing HIERARCHY pass (managing design hierarchy). - -6.3.1. Analyzing design hierarchy.. -Top module: \distributed_ram - -6.3.2. Analyzing design hierarchy.. -Top module: \distributed_ram -Removed 0 unused modules. - -6.4. Executing PROC pass (convert processes to netlists). - -6.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -6.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -6.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 1 assignment to connection. - -6.4.4. Executing PROC_INIT pass (extract init attributes). - -6.4.5. Executing PROC_ARST pass (detect async resets in processes). - -6.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\distributed_ram.$proc$attributes_test.v:36$188'. - 1/3: $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 - 2/3: $0$memwr$\memory$attributes_test.v:38$187_DATA[7:0]$190 - 3/3: $0$memwr$\memory$attributes_test.v:38$187_ADDR[3:0]$189 - -6.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). - -6.4.8. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\distributed_ram.\data_out_r' using process `\distributed_ram.$proc$attributes_test.v:36$188'. - created $dff cell `$procdff$227' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_ADDR' using process `\distributed_ram.$proc$attributes_test.v:36$188'. - created $dff cell `$procdff$228' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_DATA' using process `\distributed_ram.$proc$attributes_test.v:36$188'. - created $dff cell `$procdff$229' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_EN' using process `\distributed_ram.$proc$attributes_test.v:36$188'. - created $dff cell `$procdff$230' with positive edge clock. - -6.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\distributed_ram.$proc$attributes_test.v:36$188'. -Removing empty process `distributed_ram.$proc$attributes_test.v:36$188'. -Cleaned up 1 empty switch. - -6.5. Executing TRIBUF pass. - -6.6. Executing DEMINOUT pass (demote inout ports to input or output). - -6.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. -Removed 0 unused cells and 7 unused wires. - - -6.9. Executing CHECK pass (checking for obvious problems). -checking module distributed_ram.. -found and reported 0 problems. - -6.10. Executing OPT pass (performing simple optimizations). - -6.10.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.10.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -6.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. - Consolidated identical input bits for $mux cell $procmux$221: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] - New connections: $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [7:1] = { $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] } - Optimizing cells in module \distributed_ram. -Performed a total of 1 changes. - -6.10.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.10.6. Executing OPT_RMDFF pass (remove dff with constant values). - -6.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.10.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.10.9. Rerunning OPT passes. (Maybe there is more to do..) - -6.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -6.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. -Performed a total of 0 changes. - -6.10.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.10.13. Executing OPT_RMDFF pass (remove dff with constant values). - -6.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.10.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.10.16. Finished OPT passes. (There is nothing left to do.) - -6.11. Executing WREDUCE pass (reducing word size of cells). -Removed cell distributed_ram.$procmux$223 ($mux). -Removed cell distributed_ram.$procmux$225 ($mux). -Removed top 7 bits (of 8) from FF cell distributed_ram.$procdff$230 ($dff). - -6.12. Executing PEEPOPT pass (run peephole optimizers). - -6.13. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. -Removed 0 unused cells and 2 unused wires. - - -6.14. Executing PMUX2SHIFTX pass. - -6.15. Executing TECHMAP pass (map to technology primitives). - -6.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. -Generating RTLIL representation for module `\_90_lut_cmp_'. -Successfully finished Verilog frontend. - -6.15.2. Continuing TECHMAP pass. -No more expansions possible. - -6.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). -Checking cell `$memwr$\memory$attributes_test.v:38$193' in module `\distributed_ram': merged $dff to cell. -Checking cell `$memrd$\memory$attributes_test.v:39$192' in module `\distributed_ram': merged data $dff to cell. - -6.17. Executing TECHMAP pass (map to technology primitives). - -6.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. -Generating RTLIL representation for module `\_80_mul'. -Generating RTLIL representation for module `\_90_soft_mul'. -Successfully finished Verilog frontend. - -6.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. -Generating RTLIL representation for module `\$__MUL25X18'. -Successfully finished Verilog frontend. - -6.17.3. Continuing TECHMAP pass. -No more expansions possible. - -6.18. Executing OPT_EXPR pass (perform const folding). - -6.19. Executing WREDUCE pass (reducing word size of cells). - -6.20. Executing XILINX_DSP pass (pack resources into DSPs). - -6.21. Executing ALUMACC pass (create $alu and $macc cells). -Extracting $alu and $macc cells in module distributed_ram: - created 0 $alu and 0 $macc cells. - -6.22. Executing SHARE pass (SAT-based resource sharing). - -6.23. Executing OPT pass (performing simple optimizations). - -6.23.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.23.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -6.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. -Performed a total of 0 changes. - -6.23.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.23.6. Executing OPT_RMDFF pass (remove dff with constant values). - -6.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. -Removed 4 unused cells and 5 unused wires. - - -6.23.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.23.9. Rerunning OPT passes. (Maybe there is more to do..) - -6.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -6.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. -Performed a total of 0 changes. - -6.23.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.23.13. Executing OPT_RMDFF pass (remove dff with constant values). - -6.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.23.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.23.16. Finished OPT passes. (There is nothing left to do.) - -6.24. Executing FSM pass (extract and optimize FSM). - -6.24.1. Executing FSM_DETECT pass (finding FSMs in design). - -6.24.2. Executing FSM_EXTRACT pass (extracting FSM from design). - -6.24.3. Executing FSM_OPT pass (simple optimizations of FSMs). - -6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.24.5. Executing FSM_OPT pass (simple optimizations of FSMs). - -6.24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). - -6.24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). - -6.24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). - -6.25. Executing OPT pass (performing simple optimizations). - -6.25.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.25.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.25.3. Executing OPT_RMDFF pass (remove dff with constant values). - -6.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.25.5. Finished fast OPT passes. - -6.26. Executing MEMORY pass. - -6.26.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. - -6.26.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). - -6.26.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.26.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). - -6.26.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.26.6. Executing MEMORY_COLLECT pass (generating $mem cells). -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram': - $memwr$\memory$attributes_test.v:38$193 ($memwr) - $memrd$\memory$attributes_test.v:39$192 ($memrd) - -6.27. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). -Processing distributed_ram.memory: - Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 - Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): - Bram geometry: abits=9 dbits=72 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_SDP: awaste=496 dwaste=64 bwaste=36736 waste=36736 efficiency=0 - Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. - Checking rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1): - Bram geometry: abits=9 dbits=36 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_SDP: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 - Rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1): - Bram geometry: abits=10 dbits=36 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=1008 dwaste=28 bwaste=36736 waste=36736 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2): - Bram geometry: abits=11 dbits=18 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=2032 dwaste=10 bwaste=36736 waste=36736 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3): - Bram geometry: abits=12 dbits=9 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=4080 dwaste=1 bwaste=36736 waste=36736 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4): - Bram geometry: abits=13 dbits=4 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=8176 dwaste=0 bwaste=32704 waste=32704 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5): - Bram geometry: abits=14 dbits=2 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=16368 dwaste=0 bwaste=32736 waste=32736 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6): - Bram geometry: abits=15 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=32752 dwaste=0 bwaste=32752 waste=32752 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1): - Bram geometry: abits=10 dbits=18 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2): - Bram geometry: abits=11 dbits=9 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3): - Bram geometry: abits=12 dbits=4 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4): - Bram geometry: abits=13 dbits=2 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5): - Bram geometry: abits=14 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. - No acceptable bram resources found. - -6.29. Executing TECHMAP pass (map to technology primitives). - -6.29.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v' to AST representation. -Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. -Successfully finished Verilog frontend. - -6.29.2. Continuing TECHMAP pass. -No more expansions possible. - -6.30. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). -Processing distributed_ram.memory: - Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 - Checking rule #1 for bram type $__XILINX_RAM32X1D (variant 1): - Bram geometry: abits=5 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAM32X1D: awaste=16 dwaste=0 bwaste=16 waste=16 efficiency=50 - Rule #1 for bram type $__XILINX_RAM32X1D (variant 1) accepted. - Mapping to bram type $__XILINX_RAM32X1D (variant 1): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=16 efficiency=50 - Storing for later selection. - Checking rule #2 for bram type $__XILINX_RAM64X1D (variant 1): - Bram geometry: abits=6 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAM64X1D: awaste=48 dwaste=0 bwaste=48 waste=48 efficiency=25 - Rule #2 for bram type $__XILINX_RAM64X1D (variant 1) accepted. - Mapping to bram type $__XILINX_RAM64X1D (variant 1): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=48 efficiency=25 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAM128X1D (variant 1): - Bram geometry: abits=7 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAM128X1D: awaste=112 dwaste=0 bwaste=112 waste=112 efficiency=12 - Rule #3 for bram type $__XILINX_RAM128X1D (variant 1) accepted. - Mapping to bram type $__XILINX_RAM128X1D (variant 1): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=112 efficiency=12 - Storing for later selection. - Selecting best of 3 rules: - Efficiency for rule 3.1: efficiency=12, cells=8, acells=1 - Efficiency for rule 2.1: efficiency=25, cells=8, acells=1 - Efficiency for rule 1.1: efficiency=50, cells=8, acells=1 - Selected rule 1.1 with efficiency 50. - Mapping to bram type $__XILINX_RAM32X1D (variant 1): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Creating $__XILINX_RAM32X1D cell at grid position <0 0 0>: memory.0.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <1 0 0>: memory.1.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <2 0 0>: memory.2.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <3 0 0>: memory.3.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <4 0 0>: memory.4.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <5 0 0>: memory.5.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <6 0 0>: memory.6.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <7 0 0>: memory.7.0.0 - -6.31. Executing TECHMAP pass (map to technology primitives). - -6.31.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v' to AST representation. -Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. -Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. -Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. -Successfully finished Verilog frontend. - -6.31.2. Continuing TECHMAP pass. -Using template $paramod\$__XILINX_RAM32X1D\CLKPOL2=1 for cells of type $__XILINX_RAM32X1D. -No more expansions possible. - - -6.32. Executing OPT pass (performing simple optimizations). - -6.32.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - - -6.32.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.32.3. Executing OPT_RMDFF pass (remove dff with constant values). - -6.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. -Removed 0 unused cells and 65 unused wires. - - -6.32.5. Finished fast OPT passes. - -6.33. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). - -6.34. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). - -6.35. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). -Transforming FF to FF+Enable cells in module distributed_ram: - -6.36. Executing OPT pass (performing simple optimizations). - -6.36.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.36.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -6.36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. -Performed a total of 0 changes. - -6.36.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.36.6. Executing OPT_SHARE pass. - -6.36.7. Executing OPT_RMDFF pass (remove dff with constant values). - -6.36.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.36.9. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.36.10. Finished OPT passes. (There is nothing left to do.) - -6.37. Executing XILINX_SRL pass (Xilinx shift register extraction). - -6.38. Executing TECHMAP pass (map to technology primitives). - -6.38.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -6.38.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v' to AST representation. -Generating RTLIL representation for module `\_80_xilinx_lcu'. -Generating RTLIL representation for module `\_80_xilinx_alu'. -Successfully finished Verilog frontend. - -6.38.3. Continuing TECHMAP pass. -Using extmapper simplemap for cells of type $dff. -No more expansions possible. - - -6.39. Executing OPT pass (performing simple optimizations). - -6.39.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.39.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.39.3. Executing OPT_RMDFF pass (remove dff with constant values). - -6.39.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.39.5. Finished fast OPT passes. - -6.40. Executing TECHMAP pass (map to technology primitives). - -6.40.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -6.40.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. -Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. -Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. -Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. -Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. -Generating RTLIL representation for module `\$__SHREG_'. -Generating RTLIL representation for module `\$__XILINX_SHREG_'. -Generating RTLIL representation for module `\$__XILINX_MUXF78'. -Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. -Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. -Successfully finished Verilog frontend. - -6.40.3. Continuing TECHMAP pass. -No more expansions possible. - -6.41. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.42. Executing ABC pass (technology mapping using ABC). - -6.42.1. Extracting gate netlist of module `\distributed_ram' to `/input.blif'.. -Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. -Don't call ABC as there is nothing to map. -Removing temp directory. - -6.43. Executing XILINX_SRL pass (Xilinx shift register extraction). - -6.44. Executing TECHMAP pass (map to technology primitives). - -6.44.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v' to AST representation. -Generating RTLIL representation for module `\$lut'. -Successfully finished Verilog frontend. - -6.44.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. -Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. -Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. -Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. -Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. -Generating RTLIL representation for module `\$__SHREG_'. -Generating RTLIL representation for module `\$__XILINX_SHREG_'. -Generating RTLIL representation for module `\$__XILINX_MUXF78'. -Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. -Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. -Successfully finished Verilog frontend. - -6.44.3. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v' to AST representation. -Generating RTLIL representation for module `\$_DFF_N_'. -Generating RTLIL representation for module `\$_DFF_P_'. -Generating RTLIL representation for module `\$_DFFE_NP_'. -Generating RTLIL representation for module `\$_DFFE_PP_'. -Generating RTLIL representation for module `\$_DFF_NN0_'. -Generating RTLIL representation for module `\$_DFF_NP0_'. -Generating RTLIL representation for module `\$_DFF_PN0_'. -Generating RTLIL representation for module `\$_DFF_PP0_'. -Generating RTLIL representation for module `\$_DFF_NN1_'. -Generating RTLIL representation for module `\$_DFF_NP1_'. -Generating RTLIL representation for module `\$_DFF_PN1_'. -Generating RTLIL representation for module `\$_DFF_PP1_'. -Generating RTLIL representation for module `\$_DLATCH_N_'. -Generating RTLIL representation for module `\$_DLATCH_P_'. -Successfully finished Verilog frontend. - -6.44.4. Continuing TECHMAP pass. -Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. -No more expansions possible. - -Removed 0 unused cells and 32 unused wires. - -6.45. Executing CLKBUFMAP pass (inserting global clock buffers). -Inserting BUFG on distributed_ram.clk[0]. - -6.46. Executing HIERARCHY pass (managing design hierarchy). - -6.46.1. Analyzing design hierarchy.. -Top module: \distributed_ram - -6.46.2. Analyzing design hierarchy.. -Top module: \distributed_ram -Removed 0 unused modules. - -6.47. Printing statistics. - -=== distributed_ram === - - Number of wires: 16 - Number of wire bits: 40 - Number of public wires: 6 - Number of public wire bits: 30 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 17 - BUFG 1 - FDRE 8 - RAM32X1D 8 - - Estimated number of LCs: 0 - -6.48. Executing CHECK pass (checking for obvious problems). -checking module distributed_ram.. -found and reported 0 problems. - -7. Executing Verilog-2005 frontend: attributes_test.v -Parsing Verilog input from `attributes_test.v' to AST representation. -Generating RTLIL representation for module `\block_ram'. -Generating RTLIL representation for module `\distributed_ram'. -Generating RTLIL representation for module `\distributed_ram_manual'. -Generating RTLIL representation for module `\distributed_ram_manual_syn'. -Successfully finished Verilog frontend. - -8. Executing PREP pass. - -8.1. Executing HIERARCHY pass (managing design hierarchy). - -8.2. Executing PROC pass (convert processes to netlists). - -8.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -8.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -8.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 4 assignments to connections. - -8.2.4. Executing PROC_INIT pass (extract init attributes). - -8.2.5. Executing PROC_ARST pass (detect async resets in processes). - -8.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - 1/3: $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 - 2/3: $0$memwr$\memory$attributes_test.v:82$440_DATA[7:0]$444 - 3/3: $0$memwr$\memory$attributes_test.v:82$440_ADDR[3:0]$442 -Creating decoders for process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - 1/3: $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 - 2/3: $0$memwr$\memory$attributes_test.v:60$433_DATA[7:0]$437 - 3/3: $0$memwr$\memory$attributes_test.v:60$433_ADDR[3:0]$436 -Creating decoders for process `\distributed_ram.$proc$attributes_test.v:36$427'. - 1/3: $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 - 2/3: $0$memwr$\memory$attributes_test.v:38$426_DATA[7:0]$429 - 3/3: $0$memwr$\memory$attributes_test.v:38$426_ADDR[3:0]$428 -Creating decoders for process `\block_ram.$proc$attributes_test.v:14$420'. - 1/3: $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 - 2/3: $0$memwr$\memory$attributes_test.v:16$419_DATA[3:0]$422 - 3/3: $0$memwr$\memory$attributes_test.v:16$419_ADDR[9:0]$421 - -8.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). - -8.2.8. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_ADDR' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - created $dff cell `$procdff$471' with positive edge clock. -Creating register for signal `\distributed_ram_manual_syn.\data_out_r' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - created $dff cell `$procdff$472' with positive edge clock. -Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_EN' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - created $dff cell `$procdff$473' with positive edge clock. -Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_DATA' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - created $dff cell `$procdff$474' with positive edge clock. -Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_EN' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - created $dff cell `$procdff$475' with positive edge clock. -Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_ADDR' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - created $dff cell `$procdff$476' with positive edge clock. -Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_DATA' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - created $dff cell `$procdff$477' with positive edge clock. -Creating register for signal `\distributed_ram_manual.\data_out_r' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - created $dff cell `$procdff$478' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_ADDR' using process `\distributed_ram.$proc$attributes_test.v:36$427'. - created $dff cell `$procdff$479' with positive edge clock. -Creating register for signal `\distributed_ram.\data_out_r' using process `\distributed_ram.$proc$attributes_test.v:36$427'. - created $dff cell `$procdff$480' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_DATA' using process `\distributed_ram.$proc$attributes_test.v:36$427'. - created $dff cell `$procdff$481' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_EN' using process `\distributed_ram.$proc$attributes_test.v:36$427'. - created $dff cell `$procdff$482' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_ADDR' using process `\block_ram.$proc$attributes_test.v:14$420'. - created $dff cell `$procdff$483' with positive edge clock. -Creating register for signal `\block_ram.\data_out_r' using process `\block_ram.$proc$attributes_test.v:14$420'. - created $dff cell `$procdff$484' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_DATA' using process `\block_ram.$proc$attributes_test.v:14$420'. - created $dff cell `$procdff$485' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_EN' using process `\block_ram.$proc$attributes_test.v:14$420'. - created $dff cell `$procdff$486' with positive edge clock. - -8.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. -Removing empty process `distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. -Found and cleaned up 1 empty switch in `\distributed_ram_manual.$proc$attributes_test.v:58$434'. -Removing empty process `distributed_ram_manual.$proc$attributes_test.v:58$434'. -Found and cleaned up 1 empty switch in `\distributed_ram.$proc$attributes_test.v:36$427'. -Removing empty process `distributed_ram.$proc$attributes_test.v:36$427'. -Found and cleaned up 1 empty switch in `\block_ram.$proc$attributes_test.v:14$420'. -Removing empty process `block_ram.$proc$attributes_test.v:14$420'. -Cleaned up 4 empty switches. - -8.3. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram_manual_syn. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram. -Optimizing module block_ram. - -8.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram_manual_syn.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 28 unused wires. - - -8.5. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -checking module distributed_ram.. -checking module distributed_ram_manual.. -checking module distributed_ram_manual_syn.. -found and reported 0 problems. - -8.6. Executing OPT pass (performing simple optimizations). - -8.6.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. -Optimizing module distributed_ram. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram_manual_syn. - -8.6.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Finding identical cells in module `\distributed_ram'. -Finding identical cells in module `\distributed_ram_manual'. -Finding identical cells in module `\distributed_ram_manual_syn'. -Removed a total of 0 cells. - -8.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram_manual.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram_manual_syn.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -8.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. - Consolidated identical input bits for $mux cell $procmux$465: - Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] - New connections: $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [3:1] = { $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] } - Optimizing cells in module \block_ram. - Optimizing cells in module \distributed_ram. - Consolidated identical input bits for $mux cell $procmux$459: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] - New connections: $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [7:1] = { $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] } - Optimizing cells in module \distributed_ram. - Optimizing cells in module \distributed_ram_manual. - Consolidated identical input bits for $mux cell $procmux$453: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] - New connections: $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [7:1] = { $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] } - Optimizing cells in module \distributed_ram_manual. - Optimizing cells in module \distributed_ram_manual_syn. - Consolidated identical input bits for $mux cell $procmux$447: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] - New connections: $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [7:1] = { $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] } - Optimizing cells in module \distributed_ram_manual_syn. -Performed a total of 4 changes. - -8.6.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Finding identical cells in module `\distributed_ram'. -Finding identical cells in module `\distributed_ram_manual'. -Finding identical cells in module `\distributed_ram_manual_syn'. -Removed a total of 0 cells. - -8.6.6. Executing OPT_RMDFF pass (remove dff with constant values). - -8.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram_manual_syn.. - -8.6.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. -Optimizing module distributed_ram. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram_manual_syn. - -8.6.9. Rerunning OPT passes. (Maybe there is more to do..) - -8.6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram_manual.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram_manual_syn.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -8.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. - Optimizing cells in module \distributed_ram. - Optimizing cells in module \distributed_ram_manual. - Optimizing cells in module \distributed_ram_manual_syn. -Performed a total of 0 changes. - -8.6.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Finding identical cells in module `\distributed_ram'. -Finding identical cells in module `\distributed_ram_manual'. -Finding identical cells in module `\distributed_ram_manual_syn'. -Removed a total of 0 cells. - -8.6.13. Executing OPT_RMDFF pass (remove dff with constant values). - -8.6.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram_manual_syn.. - -8.6.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. -Optimizing module distributed_ram. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram_manual_syn. - -8.6.16. Finished OPT passes. (There is nothing left to do.) - -8.7. Executing WREDUCE pass (reducing word size of cells). -Removed top 3 bits (of 4) from FF cell block_ram.$procdff$486 ($dff). -Removed top 7 bits (of 8) from FF cell distributed_ram.$procdff$482 ($dff). -Removed top 7 bits (of 8) from FF cell distributed_ram_manual.$procdff$475 ($dff). -Removed top 7 bits (of 8) from FF cell distributed_ram_manual_syn.$procdff$473 ($dff). - -8.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). -Checking cell `$memwr$\memory$attributes_test.v:16$425' in module `\block_ram': merged $dff to cell. -Checking cell `$memwr$\memory$attributes_test.v:38$432' in module `\distributed_ram': merged $dff to cell. -Checking cell `$memwr$\memory$attributes_test.v:60$439' in module `\distributed_ram_manual': merged $dff to cell. -Checking cell `$memwr$\memory$attributes_test.v:82$446' in module `\distributed_ram_manual_syn': merged $dff to cell. - -8.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram_manual_syn.. -Removed 12 unused cells and 12 unused wires. - - -8.10. Executing MEMORY_COLLECT pass (generating $mem cells). -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\block_ram': - $memwr$\memory$attributes_test.v:16$425 ($memwr) - $memrd$\memory$attributes_test.v:17$424 ($memrd) -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram': - $memwr$\memory$attributes_test.v:38$432 ($memwr) - $memrd$\memory$attributes_test.v:39$431 ($memrd) -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram_manual': - $memwr$\memory$attributes_test.v:60$439 ($memwr) - $memrd$\memory$attributes_test.v:61$438 ($memrd) -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram_manual_syn': - $memwr$\memory$attributes_test.v:82$446 ($memwr) - $memrd$\memory$attributes_test.v:83$445 ($memrd) - -8.11. Executing OPT pass (performing simple optimizations). - -8.11.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. -Optimizing module distributed_ram. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram_manual_syn. - -8.11.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Finding identical cells in module `\distributed_ram'. -Finding identical cells in module `\distributed_ram_manual'. -Finding identical cells in module `\distributed_ram_manual_syn'. -Removed a total of 0 cells. - -8.11.3. Executing OPT_RMDFF pass (remove dff with constant values). - -8.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram_manual_syn.. - -8.11.5. Finished fast OPT passes. - -8.12. Printing statistics. - -=== block_ram === - - Number of wires: 10 - Number of wire bits: 46 - Number of public wires: 6 - Number of public wire bits: 24 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 5 - $dff 1 - $mem 1 - $mux 3 - -=== distributed_ram === - - Number of wires: 10 - Number of wire bits: 58 - Number of public wires: 6 - Number of public wire bits: 30 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 5 - $dff 1 - $mem 1 - $mux 3 - -=== distributed_ram_manual === - - Number of wires: 10 - Number of wire bits: 58 - Number of public wires: 6 - Number of public wire bits: 30 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 5 - $dff 1 - $mem 1 - $mux 3 - -=== distributed_ram_manual_syn === - - Number of wires: 10 - Number of wire bits: 58 - Number of public wires: 6 - Number of public wire bits: 30 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 5 - $dff 1 - $mem 1 - $mux 3 - -8.13. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -checking module distributed_ram.. -checking module distributed_ram_manual.. -checking module distributed_ram_manual_syn.. -found and reported 0 problems. - -9. Executing SYNTH_XILINX pass. - -9.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. -Generating RTLIL representation for module `\VCC'. -Generating RTLIL representation for module `\GND'. -Generating RTLIL representation for module `\IBUF'. -Generating RTLIL representation for module `\IBUFG'. -Generating RTLIL representation for module `\OBUF'. -Generating RTLIL representation for module `\IOBUF'. -Generating RTLIL representation for module `\OBUFT'. -Generating RTLIL representation for module `\BUFG'. -Generating RTLIL representation for module `\BUFGCTRL'. -Generating RTLIL representation for module `\BUFHCE'. -Generating RTLIL representation for module `\INV'. -Generating RTLIL representation for module `\LUT1'. -Generating RTLIL representation for module `\LUT2'. -Generating RTLIL representation for module `\LUT3'. -Generating RTLIL representation for module `\LUT4'. -Generating RTLIL representation for module `\LUT5'. -Generating RTLIL representation for module `\LUT6'. -Generating RTLIL representation for module `\LUT6_2'. -Generating RTLIL representation for module `\MUXCY'. -Generating RTLIL representation for module `\MUXF7'. -Generating RTLIL representation for module `\MUXF8'. -Generating RTLIL representation for module `\XORCY'. -Generating RTLIL representation for module `\CARRY4'. -Generating RTLIL representation for module `\FDRE'. -Generating RTLIL representation for module `\FDSE'. -Generating RTLIL representation for module `\FDCE'. -Generating RTLIL representation for module `\FDPE'. -Generating RTLIL representation for module `\FDRE_1'. -Generating RTLIL representation for module `\FDSE_1'. -Generating RTLIL representation for module `\FDCE_1'. -Generating RTLIL representation for module `\FDPE_1'. -Generating RTLIL representation for module `\LDCE'. -Generating RTLIL representation for module `\LDPE'. -Generating RTLIL representation for module `\RAM16X1S'. -Generating RTLIL representation for module `\RAM16X1S_1'. -Generating RTLIL representation for module `\RAM32X1S'. -Generating RTLIL representation for module `\RAM32X1S_1'. -Generating RTLIL representation for module `\RAM64X1S'. -Generating RTLIL representation for module `\RAM64X1S_1'. -Generating RTLIL representation for module `\RAM128X1S'. -Generating RTLIL representation for module `\RAM128X1S_1'. -Generating RTLIL representation for module `\RAM256X1S'. -Generating RTLIL representation for module `\RAM512X1S'. -Generating RTLIL representation for module `\RAM16X2S'. -Generating RTLIL representation for module `\RAM32X2S'. -Generating RTLIL representation for module `\RAM64X2S'. -Generating RTLIL representation for module `\RAM16X4S'. -Generating RTLIL representation for module `\RAM32X4S'. -Generating RTLIL representation for module `\RAM16X8S'. -Generating RTLIL representation for module `\RAM32X8S'. -Generating RTLIL representation for module `\RAM16X1D'. -Generating RTLIL representation for module `\RAM16X1D_1'. -Generating RTLIL representation for module `\RAM32X1D'. -Generating RTLIL representation for module `\RAM32X1D_1'. -Generating RTLIL representation for module `\RAM64X1D'. -Generating RTLIL representation for module `\RAM64X1D_1'. -Generating RTLIL representation for module `\RAM128X1D'. -Generating RTLIL representation for module `\RAM256X1D'. -Generating RTLIL representation for module `\RAM32M'. -Generating RTLIL representation for module `\RAM32M16'. -Generating RTLIL representation for module `\RAM64M'. -Generating RTLIL representation for module `\RAM64M8'. -Generating RTLIL representation for module `\ROM16X1'. -Generating RTLIL representation for module `\ROM32X1'. -Generating RTLIL representation for module `\ROM64X1'. -Generating RTLIL representation for module `\ROM128X1'. -Generating RTLIL representation for module `\ROM256X1'. -Generating RTLIL representation for module `\SRL16E'. -Generating RTLIL representation for module `\SRLC16E'. -Generating RTLIL representation for module `\SRLC32E'. -Generating RTLIL representation for module `\MULT18X18'. -Generating RTLIL representation for module `\MULT18X18S'. -Generating RTLIL representation for module `\MULT18X18SIO'. -Generating RTLIL representation for module `\DSP48A'. -Generating RTLIL representation for module `\DSP48A1'. -Generating RTLIL representation for module `\DSP48E1'. -Successfully finished Verilog frontend. - -9.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. -Generating RTLIL representation for module `\FDCPE'. -Generating RTLIL representation for module `\FDRSE'. -Generating RTLIL representation for module `\LDCPE'. -Generating RTLIL representation for module `\AND2B1L'. -Generating RTLIL representation for module `\OR2L'. -Generating RTLIL representation for module `\MUXF5'. -Generating RTLIL representation for module `\MUXF6'. -Generating RTLIL representation for module `\MUXF9'. -Generating RTLIL representation for module `\CARRY8'. -Generating RTLIL representation for module `\ORCY'. -Generating RTLIL representation for module `\MULT_AND'. -Generating RTLIL representation for module `\SRL16'. -Generating RTLIL representation for module `\SRLC16'. -Generating RTLIL representation for module `\CFGLUT5'. -Generating RTLIL representation for module `\RAMB16_S1'. -Generating RTLIL representation for module `\RAMB16_S2'. -Generating RTLIL representation for module `\RAMB16_S4'. -Generating RTLIL representation for module `\RAMB16_S9'. -Generating RTLIL representation for module `\RAMB16_S18'. -Generating RTLIL representation for module `\RAMB16_S36'. -Generating RTLIL representation for module `\RAMB16_S1_S1'. -Generating RTLIL representation for module `\RAMB16_S1_S2'. -Generating RTLIL representation for module `\RAMB16_S1_S4'. -Generating RTLIL representation for module `\RAMB16_S1_S9'. -Generating RTLIL representation for module `\RAMB16_S1_S18'. -Generating RTLIL representation for module `\RAMB16_S1_S36'. -Generating RTLIL representation for module `\RAMB16_S2_S2'. -Generating RTLIL representation for module `\RAMB16_S2_S4'. -Generating RTLIL representation for module `\RAMB16_S2_S9'. -Generating RTLIL representation for module `\RAMB16_S2_S18'. -Generating RTLIL representation for module `\RAMB16_S2_S36'. -Generating RTLIL representation for module `\RAMB16_S4_S4'. -Generating RTLIL representation for module `\RAMB16_S4_S9'. -Generating RTLIL representation for module `\RAMB16_S4_S18'. -Generating RTLIL representation for module `\RAMB16_S4_S36'. -Generating RTLIL representation for module `\RAMB16_S9_S9'. -Generating RTLIL representation for module `\RAMB16_S9_S18'. -Generating RTLIL representation for module `\RAMB16_S9_S36'. -Generating RTLIL representation for module `\RAMB16_S18_S18'. -Generating RTLIL representation for module `\RAMB16_S18_S36'. -Generating RTLIL representation for module `\RAMB16_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWER'. -Generating RTLIL representation for module `\RAMB8BWER'. -Generating RTLIL representation for module `\FIFO16'. -Generating RTLIL representation for module `\RAMB16'. -Generating RTLIL representation for module `\RAMB32_S64_ECC'. -Generating RTLIL representation for module `\FIFO18'. -Generating RTLIL representation for module `\FIFO18_36'. -Generating RTLIL representation for module `\FIFO36'. -Generating RTLIL representation for module `\FIFO36_72'. -Generating RTLIL representation for module `\RAMB18'. -Generating RTLIL representation for module `\RAMB36'. -Generating RTLIL representation for module `\RAMB18SDP'. -Generating RTLIL representation for module `\RAMB36SDP'. -Generating RTLIL representation for module `\FIFO18E1'. -Generating RTLIL representation for module `\FIFO36E1'. -Generating RTLIL representation for module `\RAMB18E1'. -Generating RTLIL representation for module `\RAMB36E1'. -Generating RTLIL representation for module `\FIFO18E2'. -Generating RTLIL representation for module `\FIFO36E2'. -Generating RTLIL representation for module `\RAMB18E2'. -Generating RTLIL representation for module `\RAMB36E2'. -Generating RTLIL representation for module `\URAM288'. -Generating RTLIL representation for module `\URAM288_BASE'. -Generating RTLIL representation for module `\DSP48'. -Generating RTLIL representation for module `\DSP48E'. -Generating RTLIL representation for module `\DSP48E2'. -Generating RTLIL representation for module `\IFDDRCPE'. -Generating RTLIL representation for module `\IFDDRRSE'. -Generating RTLIL representation for module `\OFDDRCPE'. -Generating RTLIL representation for module `\OFDDRRSE'. -Generating RTLIL representation for module `\OFDDRTCPE'. -Generating RTLIL representation for module `\OFDDRTRSE'. -Generating RTLIL representation for module `\IDDR2'. -Generating RTLIL representation for module `\ODDR2'. -Generating RTLIL representation for module `\IDDR'. -Generating RTLIL representation for module `\IDDR_2CLK'. -Generating RTLIL representation for module `\ODDR'. -Generating RTLIL representation for module `\IDELAYCTRL'. -Generating RTLIL representation for module `\IDELAY'. -Generating RTLIL representation for module `\ISERDES'. -Generating RTLIL representation for module `\OSERDES'. -Generating RTLIL representation for module `\IODELAY'. -Generating RTLIL representation for module `\ISERDES_NODELAY'. -Generating RTLIL representation for module `\IODELAYE1'. -Generating RTLIL representation for module `\ISERDESE1'. -Generating RTLIL representation for module `\OSERDESE1'. -Generating RTLIL representation for module `\IDELAYE2'. -Generating RTLIL representation for module `\ODELAYE2'. -Generating RTLIL representation for module `\ISERDESE2'. -Generating RTLIL representation for module `\OSERDESE2'. -Generating RTLIL representation for module `\PHASER_IN'. -Generating RTLIL representation for module `\PHASER_IN_PHY'. -Generating RTLIL representation for module `\PHASER_OUT'. -Generating RTLIL representation for module `\PHASER_OUT_PHY'. -Generating RTLIL representation for module `\PHASER_REF'. -Generating RTLIL representation for module `\PHY_CONTROL'. -Generating RTLIL representation for module `\IDDRE1'. -Generating RTLIL representation for module `\ODDRE1'. -Generating RTLIL representation for module `\IDELAYE3'. -Generating RTLIL representation for module `\ODELAYE3'. -Generating RTLIL representation for module `\ISERDESE3'. -Generating RTLIL representation for module `\OSERDESE3'. -Generating RTLIL representation for module `\BITSLICE_CONTROL'. -Generating RTLIL representation for module `\RIU_OR'. -Generating RTLIL representation for module `\RX_BITSLICE'. -Generating RTLIL representation for module `\RXTX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE_TRI'. -Generating RTLIL representation for module `\IODELAY2'. -Generating RTLIL representation for module `\IODRP2'. -Generating RTLIL representation for module `\IODRP2_MCB'. -Generating RTLIL representation for module `\ISERDES2'. -Generating RTLIL representation for module `\OSERDES2'. -Generating RTLIL representation for module `\IBUF_DLY_ADJ'. -Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUF_ANALOG'. -Generating RTLIL representation for module `\IBUFE3'. -Generating RTLIL representation for module `\IBUFDS'. -Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. -Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDSE3'. -Generating RTLIL representation for module `\IBUFDS_DPHY'. -Generating RTLIL representation for module `\IBUFGDS'. -Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUF_DCIEN'. -Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFE3'. -Generating RTLIL representation for module `\IOBUFDS'. -Generating RTLIL representation for module `\IOBUFDS_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDSE3'. -Generating RTLIL representation for module `\OBUFDS'. -Generating RTLIL representation for module `\OBUFDS_DPHY'. -Generating RTLIL representation for module `\OBUFTDS'. -Generating RTLIL representation for module `\KEEPER'. -Generating RTLIL representation for module `\PULLDOWN'. -Generating RTLIL representation for module `\PULLUP'. -Generating RTLIL representation for module `\DCIRESET'. -Generating RTLIL representation for module `\HPIO_VREF'. -Generating RTLIL representation for module `\BUFGCE'. -Generating RTLIL representation for module `\BUFGCE_1'. -Generating RTLIL representation for module `\BUFGMUX'. -Generating RTLIL representation for module `\BUFGMUX_1'. -Generating RTLIL representation for module `\BUFGMUX_CTRL'. -Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. -Generating RTLIL representation for module `\BUFG_GT'. -Generating RTLIL representation for module `\BUFG_GT_SYNC'. -Generating RTLIL representation for module `\BUFG_PS'. -Generating RTLIL representation for module `\BUFGCE_DIV'. -Generating RTLIL representation for module `\BUFH'. -Generating RTLIL representation for module `\BUFIO2'. -Generating RTLIL representation for module `\BUFIO2_2CLK'. -Generating RTLIL representation for module `\BUFIO2FB'. -Generating RTLIL representation for module `\BUFPLL'. -Generating RTLIL representation for module `\BUFPLL_MCB'. -Generating RTLIL representation for module `\BUFIO'. -Generating RTLIL representation for module `\BUFIODQS'. -Generating RTLIL representation for module `\BUFR'. -Generating RTLIL representation for module `\BUFMR'. -Generating RTLIL representation for module `\BUFMRCE'. -Generating RTLIL representation for module `\DCM'. -Generating RTLIL representation for module `\DCM_SP'. -Generating RTLIL representation for module `\DCM_CLKGEN'. -Generating RTLIL representation for module `\DCM_ADV'. -Generating RTLIL representation for module `\DCM_BASE'. -Generating RTLIL representation for module `\DCM_PS'. -Generating RTLIL representation for module `\PMCD'. -Generating RTLIL representation for module `\PLL_ADV'. -Generating RTLIL representation for module `\PLL_BASE'. -Generating RTLIL representation for module `\MMCM_ADV'. -Generating RTLIL representation for module `\MMCM_BASE'. -Generating RTLIL representation for module `\MMCME2_ADV'. -Generating RTLIL representation for module `\MMCME2_BASE'. -Generating RTLIL representation for module `\PLLE2_ADV'. -Generating RTLIL representation for module `\PLLE2_BASE'. -Generating RTLIL representation for module `\MMCME3_ADV'. -Generating RTLIL representation for module `\MMCME3_BASE'. -Generating RTLIL representation for module `\PLLE3_ADV'. -Generating RTLIL representation for module `\PLLE3_BASE'. -Generating RTLIL representation for module `\MMCME4_ADV'. -Generating RTLIL representation for module `\MMCME4_BASE'. -Generating RTLIL representation for module `\PLLE4_ADV'. -Generating RTLIL representation for module `\PLLE4_BASE'. -Generating RTLIL representation for module `\BUFT'. -Generating RTLIL representation for module `\IN_FIFO'. -Generating RTLIL representation for module `\OUT_FIFO'. -Generating RTLIL representation for module `\HARD_SYNC'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. -Generating RTLIL representation for module `\STARTUP_SPARTAN6'. -Generating RTLIL representation for module `\STARTUP_VIRTEX4'. -Generating RTLIL representation for module `\STARTUP_VIRTEX5'. -Generating RTLIL representation for module `\STARTUP_VIRTEX6'. -Generating RTLIL representation for module `\STARTUPE2'. -Generating RTLIL representation for module `\STARTUPE3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. -Generating RTLIL representation for module `\CAPTUREE2'. -Generating RTLIL representation for module `\ICAP_SPARTAN3A'. -Generating RTLIL representation for module `\ICAP_SPARTAN6'. -Generating RTLIL representation for module `\ICAP_VIRTEX4'. -Generating RTLIL representation for module `\ICAP_VIRTEX5'. -Generating RTLIL representation for module `\ICAP_VIRTEX6'. -Generating RTLIL representation for module `\ICAPE2'. -Generating RTLIL representation for module `\ICAPE3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. -Generating RTLIL representation for module `\BSCAN_SPARTAN6'. -Generating RTLIL representation for module `\BSCAN_VIRTEX4'. -Generating RTLIL representation for module `\BSCAN_VIRTEX5'. -Generating RTLIL representation for module `\BSCAN_VIRTEX6'. -Generating RTLIL representation for module `\BSCANE2'. -Generating RTLIL representation for module `\DNA_PORT'. -Generating RTLIL representation for module `\DNA_PORTE2'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. -Generating RTLIL representation for module `\FRAME_ECCE2'. -Generating RTLIL representation for module `\FRAME_ECCE3'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. -Generating RTLIL representation for module `\USR_ACCESSE2'. -Generating RTLIL representation for module `\POST_CRC_INTERNAL'. -Generating RTLIL representation for module `\SUSPEND_SYNC'. -Generating RTLIL representation for module `\KEY_CLEAR'. -Generating RTLIL representation for module `\MASTER_JTAG'. -Generating RTLIL representation for module `\SPI_ACCESS'. -Generating RTLIL representation for module `\EFUSE_USR'. -Generating RTLIL representation for module `\SYSMON'. -Generating RTLIL representation for module `\XADC'. -Generating RTLIL representation for module `\SYSMONE1'. -Generating RTLIL representation for module `\SYSMONE4'. -Generating RTLIL representation for module `\GTPA1_DUAL'. -Generating RTLIL representation for module `\GT11_CUSTOM'. -Generating RTLIL representation for module `\GT11_DUAL'. -Generating RTLIL representation for module `\GT11CLK'. -Generating RTLIL representation for module `\GT11CLK_MGT'. -Generating RTLIL representation for module `\GTP_DUAL'. -Generating RTLIL representation for module `\GTX_DUAL'. -Generating RTLIL representation for module `\CRC32'. -Generating RTLIL representation for module `\CRC64'. -Generating RTLIL representation for module `\GTHE1_QUAD'. -Generating RTLIL representation for module `\GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTHE1'. -Generating RTLIL representation for module `\GTHE2_CHANNEL'. -Generating RTLIL representation for module `\GTHE2_COMMON'. -Generating RTLIL representation for module `\GTPE2_CHANNEL'. -Generating RTLIL representation for module `\GTPE2_COMMON'. -Generating RTLIL representation for module `\GTXE2_CHANNEL'. -Generating RTLIL representation for module `\GTXE2_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE2'. -Generating RTLIL representation for module `\GTHE3_CHANNEL'. -Generating RTLIL representation for module `\GTHE3_COMMON'. -Generating RTLIL representation for module `\GTHE4_CHANNEL'. -Generating RTLIL representation for module `\GTHE4_COMMON'. -Generating RTLIL representation for module `\GTYE3_CHANNEL'. -Generating RTLIL representation for module `\GTYE3_COMMON'. -Generating RTLIL representation for module `\GTYE4_CHANNEL'. -Generating RTLIL representation for module `\GTYE4_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE3'. -Generating RTLIL representation for module `\IBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE3'. -Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. -Generating RTLIL representation for module `\OBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. -Generating RTLIL representation for module `\PCIE_A1'. -Generating RTLIL representation for module `\PCIE_EP'. -Generating RTLIL representation for module `\PCIE_2_0'. -Generating RTLIL representation for module `\PCIE_2_1'. -Generating RTLIL representation for module `\PCIE_3_0'. -Generating RTLIL representation for module `\PCIE_3_1'. -Generating RTLIL representation for module `\PCIE40E4'. -Generating RTLIL representation for module `\EMAC'. -Generating RTLIL representation for module `\TEMAC'. -Generating RTLIL representation for module `\TEMAC_SINGLE'. -Generating RTLIL representation for module `\CMAC'. -Generating RTLIL representation for module `\CMACE4'. -Generating RTLIL representation for module `\PPC405_ADV'. -Generating RTLIL representation for module `\PPC440'. -Generating RTLIL representation for module `\MCB'. -Generating RTLIL representation for module `\PS7'. -Generating RTLIL representation for module `\PS8'. -Generating RTLIL representation for module `\ILKN'. -Generating RTLIL representation for module `\ILKNE4'. -Successfully finished Verilog frontend. - -9.3. Executing HIERARCHY pass (managing design hierarchy). - -9.3.1. Analyzing design hierarchy.. -Top module: \block_ram - -9.3.2. Analyzing design hierarchy.. -Top module: \block_ram -Removing unused module `\distributed_ram'. -Removing unused module `\distributed_ram_manual'. -Removing unused module `\distributed_ram_manual_syn'. -Removed 3 unused modules. - -9.4. Executing PROC pass (convert processes to netlists). - -9.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -9.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -9.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. - -9.4.4. Executing PROC_INIT pass (extract init attributes). - -9.4.5. Executing PROC_ARST pass (detect async resets in processes). - -9.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). - -9.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). - -9.4.8. Executing PROC_DFF pass (convert process syncs to FFs). - -9.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -9.5. Executing TRIBUF pass. - -9.6. Executing DEMINOUT pass (demote inout ports to input or output). - -9.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -9.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -9.9. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -found and reported 0 problems. - -9.10. Executing OPT pass (performing simple optimizations). - -9.10.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -9.10.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -9.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -9.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -9.10.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -9.10.6. Executing OPT_RMDFF pass (remove dff with constant values). - -9.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -9.10.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -9.10.9. Finished OPT passes. (There is nothing left to do.) - -9.11. Executing WREDUCE pass (reducing word size of cells). -Removed cell block_ram.$procmux$469 ($mux). -Removed cell block_ram.$procmux$467 ($mux). - -9.12. Executing PEEPOPT pass (run peephole optimizers). - -9.13. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 2 unused wires. - - -9.14. Executing PMUX2SHIFTX pass. - -9.15. Executing TECHMAP pass (map to technology primitives). - -9.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. -Generating RTLIL representation for module `\_90_lut_cmp_'. -Successfully finished Verilog frontend. - -9.15.2. Continuing TECHMAP pass. -No more expansions possible. - -9.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). - -9.17. Executing TECHMAP pass (map to technology primitives). - -9.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. -Generating RTLIL representation for module `\_80_mul'. -Generating RTLIL representation for module `\_90_soft_mul'. -Successfully finished Verilog frontend. - -9.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. -Generating RTLIL representation for module `\$__MUL25X18'. -Successfully finished Verilog frontend. - -9.17.3. Continuing TECHMAP pass. -No more expansions possible. - -9.18. Executing OPT_EXPR pass (perform const folding). - -9.19. Executing WREDUCE pass (reducing word size of cells). - -9.20. Executing XILINX_DSP pass (pack resources into DSPs). - -9.21. Executing ALUMACC pass (create $alu and $macc cells). -Extracting $alu and $macc cells in module block_ram: - created 0 $alu and 0 $macc cells. - -9.22. Executing SHARE pass (SAT-based resource sharing). From abcd82dacadc8b5af6b2b7f6d7cbdb635d276440 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 16 Dec 2019 13:09:31 +0100 Subject: [PATCH 26/46] add assert option to scratchpad command --- passes/cmds/scratchpad.cc | 49 +++++++++++++++++++++++++++++++++---- tests/various/scratchpad.sh | 14 ----------- tests/various/scratchpad.ys | 5 ++++ 3 files changed, 49 insertions(+), 19 deletions(-) delete mode 100755 tests/various/scratchpad.sh create mode 100644 tests/various/scratchpad.ys diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index 6bf14a6bd..805badc7e 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -34,15 +34,29 @@ struct ScratchpadPass : public Pass { log(" scratchpad [options]\n"); log("\n"); log("This pass allows to read and modify values from the scratchpad of the current\n"); - log("design. Options:\n\n"); + log("design. Options:\n"); + log("\n"); log(" -get \n"); - log(" print the value saved in the scratchpad under the given identifier.\n\n"); + log(" print the value saved in the scratchpad under the given identifier.\n"); + log("\n"); log(" -set \n"); - log(" save the given value in the scratchpad under the given identifier.\n\n"); + log(" save the given value in the scratchpad under the given identifier.\n"); + log("\n"); log(" -unset \n"); - log(" remove the entry for the given identifier from the scratchpad.\n\n"); + log(" remove the entry for the given identifier from the scratchpad.\n"); + log("\n"); log(" -copy \n"); - log(" copy the value of the first identifier to the second identifier.\n\n"); + log(" copy the value of the first identifier to the second identifier.\n"); + log("\n"); + log(" -assert \n"); + log(" assert that the entry for the given identifier is set to the given value.\n"); + log("\n"); + log(" -assert-set \n"); + log(" assert that the entry for the given identifier exists.\n"); + log("\n"); + log(" -assert-unset \n"); + log(" assert that the entry for the given identifier does not exist.\n"); + log("\n"); log("The identifier may not contain whitespace. By convention, it is usually prefixed\n"); log("by the name of the pass that uses it, e.g. 'opt.did_something'. If the value\n"); log("contains whitespace, it must be enclosed in double quotes.\n"); @@ -83,6 +97,31 @@ struct ScratchpadPass : public Pass { design->scratchpad_set_string(identifier_to, value); continue; } + if (args[argidx] == "-assert" && argidx+2 < args.size()) { + string identifier = args[++argidx]; + string expected = args[++argidx]; + if (expected.front() == '\"' && expected.back() == '\"') expected = expected.substr(1, expected.size() - 2); + if (design->scratchpad.count(identifier) == 0) + log_error("Assertion failed: scratchpad entry '%s' is not defined\n", identifier.c_str()); + string value = design->scratchpad_get_string(identifier); + if (value != expected) { + log_error("Assertion failed: scratchpad entry '%s' is set to '%s' instead of the asserted '%s'\n", + identifier.c_str(), value.c_str(), expected.c_str()); + } + continue; + } + if (args[argidx] == "-assert-set" && argidx+1 < args.size()) { + string identifier = args[++argidx]; + if (design->scratchpad.count(identifier) == 0) + log_error("Assertion failed: scratchpad entry '%s' is not defined\n", identifier.c_str()); + continue; + } + if (args[argidx] == "-assert-unset" && argidx+1 < args.size()) { + string identifier = args[++argidx]; + if (design->scratchpad.count(identifier) > 0) + log_error("Assertion failed: scratchpad entry '%s' is defined\n", identifier.c_str()); + continue; + } log("Unrecognized argument: %s\n", args[argidx].c_str()); break; } diff --git a/tests/various/scratchpad.sh b/tests/various/scratchpad.sh deleted file mode 100755 index 4e92473f8..000000000 --- a/tests/various/scratchpad.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -trap 'echo "ERROR in scratchpad.sh" >&2; exit 1' ERR - -../../yosys -qp "scratchpad -set foo \"bar baz\"; \ -scratchpad -copy foo oof; scratchpad -unset foo; \ -tee -o scratchpad1.log scratchpad -get oof; \ -tee -o scratchpad2.log scratchpad -get foo" - -test "$(cat scratchpad1.log)" = "bar baz" -test "$(cat scratchpad2.log)" = "\"foo\" not set" - -rm scratchpad1.log -rm scratchpad2.log diff --git a/tests/various/scratchpad.ys b/tests/various/scratchpad.ys new file mode 100644 index 000000000..dc94081ea --- /dev/null +++ b/tests/various/scratchpad.ys @@ -0,0 +1,5 @@ +scratchpad -set foo "bar baz" +scratchpad -copy foo oof +scratchpad -unset foo +scratchpad -assert oof "bar baz" +scratchpad -assert-unset foo From 87e21b0122bd682db8aeffae3e1ac503c9cea2d2 Mon Sep 17 00:00:00 2001 From: Diego H Date: Mon, 16 Dec 2019 10:23:45 -0600 Subject: [PATCH 27/46] Fixing compiler warning/issues. Moving test script to the correct place --- passes/memory/memory_bram.cc | 16 ++++++++-------- .../attributes_test.ys | 12 ++++++------ 2 files changed, 14 insertions(+), 14 deletions(-) rename tests/arch/{common/memory_attributes => xilinx}/attributes_test.ys (81%) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 10b48e321..703e87f05 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -821,8 +821,8 @@ grow_read_ports:; log(" Updated properties: dups=%d waste=%d efficiency=%d\n", match_properties["dups"], match_properties["waste"], match_properties["efficiency"]); - for (auto& iter: match.attr_match) { - for (auto& iter: iter.second) { + for (auto iter: match.attr_match) { + for (auto iter: iter.second) { auto it = cell->attributes.find(iter.first); if (iter.second.empty()) { @@ -1124,8 +1124,8 @@ void handle_cell(Cell *cell, const rules_t &rules) goto next_match_rule; } - for (auto& iter: match.attr_match) { - for (auto& iter: iter.second) { + for (auto iter: match.attr_match) { + for (auto iter: iter.second) { auto it = cell->attributes.find(iter.first); if (it != cell->attributes.end()) { @@ -1149,10 +1149,10 @@ void handle_cell(Cell *cell, const rules_t &rules) if (!it->second.empty()) { if (it->second.decode_string().length() == 1) it->second = it->second.as_string().back(); - if (!it->second.decode_string().compare(iter.second.decode_string())) - goto next_match_rule; - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); + if (!it->second.decode_string().compare(iter.second.decode_string())) + goto next_match_rule; + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); } } } diff --git a/tests/arch/common/memory_attributes/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys similarity index 81% rename from tests/arch/common/memory_attributes/attributes_test.ys rename to tests/arch/xilinx/attributes_test.ys index 4e06a35e7..4c881b280 100644 --- a/tests/arch/common/memory_attributes/attributes_test.ys +++ b/tests/arch/xilinx/attributes_test.ys @@ -1,5 +1,5 @@ # Check that blockram memory without parameters is not modified -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top block_ram synth_xilinx -top block_ram cd block_ram # Constrain all select calls below inside the top module @@ -7,7 +7,7 @@ select -assert-count 1 t:RAMB18E1 # Check that distributed memory without parameters is not modified design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top distributed_ram synth_xilinx -top distributed_ram cd distributed_ram # Constrain all select calls below inside the top module @@ -15,7 +15,7 @@ select -assert-count 8 t:RAM32X1D # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set ram_style "distributed" block_ram synth_xilinx -top block_ram @@ -24,7 +24,7 @@ select -assert-count 32 t:RAM128X1D # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set logic_block 1 block_ram synth_xilinx -top block_ram @@ -34,14 +34,14 @@ select -assert-count 32 t:RAM128X1D # Set ram_style block to a distributed memory; will be implemented as blockram design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v synth_xilinx -top distributed_ram_manual cd distributed_ram_manual # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 # Set synthesis, ram_block block to a distributed memory; will be implemented as blockram design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v synth_xilinx -top distributed_ram_manual_syn cd distributed_ram_manual_syn # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 From c4d37813cb112d7f3717049d7cf4e6e6b0456fbb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 10:41:13 -0800 Subject: [PATCH 28/46] Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q --- techlibs/xilinx/lutrams.txt | 8 ++++---- techlibs/xilinx/lutrams_map.v | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index ae629bce8..29f6b05cc 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -78,7 +78,7 @@ bram $__XILINX_RAM64X3SDP clkpol 0 2 endbram -bram $__XILINX_RAM32M +bram $__XILINX_RAM32X2Q init 1 abits 5 dbits 2 @@ -91,7 +91,7 @@ bram $__XILINX_RAM32M clkpol 0 2 endbram -bram $__XILINX_RAM64M +bram $__XILINX_RAM64X1Q init 1 abits 6 dbits 1 @@ -151,7 +151,7 @@ match $__XILINX_RAM64X3SDP or_next_if_better endmatch -match $__XILINX_RAM32M +match $__XILINX_RAM32X2Q min bits 5 min rports 3 min wports 1 @@ -159,7 +159,7 @@ match $__XILINX_RAM32M or_next_if_better endmatch -match $__XILINX_RAM64M +match $__XILINX_RAM64X1Q min bits 5 min rports 3 min wports 1 diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v index d01508de5..884f709ab 100644 --- a/techlibs/xilinx/lutrams_map.v +++ b/techlibs/xilinx/lutrams_map.v @@ -200,7 +200,7 @@ module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); ); endmodule -module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); +module \$__XILINX_RAM32X2Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; input CLK1; @@ -236,7 +236,7 @@ module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, ); endmodule -module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); +module \$__XILINX_RAM64X1Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; input CLK1; From 7545ab3814a01047698f45739a04437045248da3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 11:56:26 -0800 Subject: [PATCH 29/46] Populate DID/DOD even if unused --- techlibs/xilinx/lutrams_map.v | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v index d01508de5..47424aa73 100644 --- a/techlibs/xilinx/lutrams_map.v +++ b/techlibs/xilinx/lutrams_map.v @@ -140,6 +140,8 @@ module \$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [5:0] B1DATA; input B1EN; + wire [1:0] DOD_unused; + RAM32M #( .INIT_A({INIT[187:186], INIT[181:180], INIT[175:174], INIT[169:168], INIT[163:162], INIT[157:156], INIT[151:150], INIT[145:144], INIT[139:138], INIT[133:132], INIT[127:126], INIT[121:120], INIT[115:114], INIT[109:108], INIT[103:102], INIT[ 97: 96], INIT[ 91: 90], INIT[ 85: 84], INIT[ 79: 78], INIT[ 73: 72], INIT[ 67: 66], INIT[ 61: 60], INIT[ 55: 54], INIT[ 49: 48], INIT[ 43: 42], INIT[ 37: 36], INIT[ 31: 30], INIT[ 25: 24], INIT[ 19: 18], INIT[ 13: 12], INIT[ 7: 6], INIT[ 1: 0]}), .INIT_B({INIT[189:188], INIT[183:182], INIT[177:176], INIT[171:170], INIT[165:164], INIT[159:158], INIT[153:152], INIT[147:146], INIT[141:140], INIT[135:134], INIT[129:128], INIT[123:122], INIT[117:116], INIT[111:110], INIT[105:104], INIT[ 99: 98], INIT[ 93: 92], INIT[ 87: 86], INIT[ 81: 80], INIT[ 75: 74], INIT[ 69: 68], INIT[ 63: 62], INIT[ 57: 56], INIT[ 51: 50], INIT[ 45: 44], INIT[ 39: 38], INIT[ 33: 32], INIT[ 27: 26], INIT[ 21: 20], INIT[ 15: 14], INIT[ 9: 8], INIT[ 3: 2]}), @@ -153,12 +155,13 @@ module \$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DOA(A1DATA[1:0]), .DOB(A1DATA[3:2]), .DOC(A1DATA[5:4]), + .DOD(DOD_unused), .ADDRD(B1ADDR), .DIA(B1DATA[1:0]), .DIB(B1DATA[3:2]), .DIC(B1DATA[5:4]), - .DID(), + .DID(2'b00), .WCLK(CLK1), .WE(B1EN) ); @@ -176,6 +179,8 @@ module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [2:0] B1DATA; input B1EN; + wire DOD_unused; + RAM64M #( .INIT_A({INIT[189], INIT[186], INIT[183], INIT[180], INIT[177], INIT[174], INIT[171], INIT[168], INIT[165], INIT[162], INIT[159], INIT[156], INIT[153], INIT[150], INIT[147], INIT[144], INIT[141], INIT[138], INIT[135], INIT[132], INIT[129], INIT[126], INIT[123], INIT[120], INIT[117], INIT[114], INIT[111], INIT[108], INIT[105], INIT[102], INIT[ 99], INIT[ 96], INIT[ 93], INIT[ 90], INIT[ 87], INIT[ 84], INIT[ 81], INIT[ 78], INIT[ 75], INIT[ 72], INIT[ 69], INIT[ 66], INIT[ 63], INIT[ 60], INIT[ 57], INIT[ 54], INIT[ 51], INIT[ 48], INIT[ 45], INIT[ 42], INIT[ 39], INIT[ 36], INIT[ 33], INIT[ 30], INIT[ 27], INIT[ 24], INIT[ 21], INIT[ 18], INIT[ 15], INIT[ 12], INIT[ 9], INIT[ 6], INIT[ 3], INIT[ 0]}), .INIT_B({INIT[190], INIT[187], INIT[184], INIT[181], INIT[178], INIT[175], INIT[172], INIT[169], INIT[166], INIT[163], INIT[160], INIT[157], INIT[154], INIT[151], INIT[148], INIT[145], INIT[142], INIT[139], INIT[136], INIT[133], INIT[130], INIT[127], INIT[124], INIT[121], INIT[118], INIT[115], INIT[112], INIT[109], INIT[106], INIT[103], INIT[100], INIT[ 97], INIT[ 94], INIT[ 91], INIT[ 88], INIT[ 85], INIT[ 82], INIT[ 79], INIT[ 76], INIT[ 73], INIT[ 70], INIT[ 67], INIT[ 64], INIT[ 61], INIT[ 58], INIT[ 55], INIT[ 52], INIT[ 49], INIT[ 46], INIT[ 43], INIT[ 40], INIT[ 37], INIT[ 34], INIT[ 31], INIT[ 28], INIT[ 25], INIT[ 22], INIT[ 19], INIT[ 16], INIT[ 13], INIT[ 10], INIT[ 7], INIT[ 4], INIT[ 1]}), @@ -189,12 +194,13 @@ module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DOA(A1DATA[0]), .DOB(A1DATA[1]), .DOC(A1DATA[2]), + .DOD(DOD_unused), .ADDRD(B1ADDR), .DIA(B1DATA[0]), .DIB(B1DATA[1]), .DIC(B1DATA[2]), - .DID(), + .DID(1'b0), .WCLK(CLK1), .WE(B1EN) ); From 503d1db551b5ab91a6ed262d011f5b9b2fa78d8e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 12:58:13 -0800 Subject: [PATCH 30/46] Implement 'attributes' grammar --- passes/memory/memory_bram.cc | 164 ++++++++++++++++++----------------- 1 file changed, 86 insertions(+), 78 deletions(-) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 703e87f05..a1353e56d 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -134,9 +134,7 @@ struct rules_t dict min_limits, max_limits; bool or_next_if_better, make_transp, make_outreg; char shuffle_enable; - dict>> attr_match; - pair attr_val; - dict attr_unmatch; + vector>> attributes; }; dict> brams; @@ -331,29 +329,20 @@ struct rules_t } if (GetSize(tokens) >= 2 && tokens[0] == "attribute") { - if (GetSize(tokens) <=2) { - size_t notval = tokens[1].find("!"); - size_t val = tokens[1].find("="); + data.attributes.emplace_back(); + for (int idx = 1; idx <= GetSize(tokens)-1; idx++) { + size_t c1 = tokens[1][0] == '!' ? 1 : 0; + size_t c2 = tokens[1].find("="); + if (c2 != std::string::npos) + c2--; - if (notval != std::string::npos) { - if (val != std::string::npos) - data.attr_unmatch[RTLIL::escape_id(tokens[1].substr(1, val-1))] = tokens[1].substr(val+1); - else - data.attr_unmatch[RTLIL::escape_id(tokens[1].substr(notval+1))] = RTLIL::Const('1'); - } - continue; - } + bool exists = (c1 == 0); + IdString key = RTLIL::escape_id(tokens[1].substr(c1, c2)); + Const val = c2 != std::string::npos ? tokens[1].substr(c2) : RTLIL::Const(1); - else if (GetSize(tokens) > 2) { - for (int idx=1; idx<= GetSize(tokens)-1; idx++) { - size_t val = tokens[idx].find("="); - if (val != std::string::npos) { - data.attr_val = make_pair(RTLIL::escape_id(tokens[idx].substr(0, val)), tokens[idx].substr(val+1)); - data.attr_match[RTLIL::escape_id(tokens[0])].push_back(data.attr_val); - } - } - continue; + data.attributes.back().emplace_back(exists, key, val); } + continue; } syntax_error(); @@ -821,27 +810,6 @@ grow_read_ports:; log(" Updated properties: dups=%d waste=%d efficiency=%d\n", match_properties["dups"], match_properties["waste"], match_properties["efficiency"]); - for (auto iter: match.attr_match) { - for (auto iter: iter.second) { - auto it = cell->attributes.find(iter.first); - - if (iter.second.empty()) { - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); - return false; - } - - if (it != cell->attributes.end()) { - if (it->second == iter.second) - continue; - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); - return false; - } - return true; - } - } - for (auto it : match.min_limits) { if (!match_properties.count(it.first)) log_error("Unknown property '%s' in match rule for bram type %s.\n", @@ -863,6 +831,43 @@ grow_read_ports:; return false; } + for (const auto &sums : match.attributes) { + bool found = false; + for (const auto &term : sums) { + bool exists = std::get<0>(term); + IdString key = std::get<1>(term); + const Const &value = std::get<2>(term); + auto it = cell->attributes.find(key); + if (it == cell->attributes.end()) { + if (exists) + continue; + found = true; + break; + } + if (it->second != value) + continue; + found = true; + break; + } + if (!found) { + std::stringstream ss; + bool exists = std::get<0>(sums.front()); + if (!exists) + ss << "!"; + IdString key = std::get<1>(sums.front()); + ss << key.str(); + const Const &value = std::get<2>(sums.front()); + if (exists) + ss << "="; + if (value != Const(1)) + ss << "\"" << value.decode_string() << "\""; + + log(" Rule for bram type %s rejected: requirement 'attribute %s ...' not met.\n", + log_id(match.name), ss.str().c_str()); + return false; + } + } + if (mode == 1) return true; } @@ -1124,39 +1129,6 @@ void handle_cell(Cell *cell, const rules_t &rules) goto next_match_rule; } - for (auto iter: match.attr_match) { - for (auto iter: iter.second) { - auto it = cell->attributes.find(iter.first); - - if (it != cell->attributes.end()) { - if (!it->second.empty()) { - if (it->second.decode_string().length() == 1) - it->second = it->second.as_string().back(); - if (!it->second.decode_string().compare(iter.second.decode_string())) - goto attribute_matched; - else - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); - } - } - } - } - - for (auto& iter: match.attr_unmatch) { - auto it = cell->attributes.find(iter.first); - - if (it != cell->attributes.end()) { - if (!it->second.empty()) { - if (it->second.decode_string().length() == 1) - it->second = it->second.as_string().back(); - if (!it->second.decode_string().compare(iter.second.decode_string())) - goto next_match_rule; - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); - } - } - } - for (auto it : match.min_limits) { if (it.first == "waste" || it.first == "dups" || it.first == "acells" || it.first == "dcells" || it.first == "cells") continue; @@ -1183,7 +1155,43 @@ void handle_cell(Cell *cell, const rules_t &rules) goto next_match_rule; } - attribute_matched: + for (const auto &sums : match.attributes) { + bool found = false; + for (const auto &term : sums) { + bool exists = std::get<0>(term); + IdString key = std::get<1>(term); + const Const &value = std::get<2>(term); + auto it = cell->attributes.find(key); + if (it == cell->attributes.end()) { + if (exists) + continue; + found = true; + break; + } + if (it->second != value) + continue; + found = true; + break; + } + if (!found) { + std::stringstream ss; + bool exists = std::get<0>(sums.front()); + if (!exists) + ss << "!"; + IdString key = std::get<1>(sums.front()); + ss << key.str(); + const Const &value = std::get<2>(sums.front()); + if (exists) + ss << "="; + if (value != Const(1)) + ss << "\"" << value.decode_string() << "\""; + + log(" Rule for bram type %s (variant %d) rejected: requirement 'attribute %s ...' not met.\n", + log_id(bram.name), bram.variant, ss.str().c_str()); + goto next_match_rule; + } + } + log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, log_id(bram.name), bram.variant); if (or_next_if_better || !best_rule_cache.empty()) From d910bec8e00b5e9eba2fc62dec1a6b734e429cc4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:00:58 -0800 Subject: [PATCH 31/46] Update xc7/xcu bram rules --- techlibs/xilinx/xc7_xcu_brams.txt | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 1374a0a36..60425fed9 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -77,8 +77,7 @@ endbram # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf match $__XILINX_RAMB36_SDP - attribute ram_style=block ram_block=1 - attribute !ram_style + attribute !ram_style ram_style=block ram_block attribute !logic_block min bits 1024 min efficiency 5 @@ -88,8 +87,7 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - attribute ram_style=block ram_block=1 - attribute !ram_style + attribute !ram_style ram_style=block ram_block attribute !logic_block min bits 1024 min efficiency 5 @@ -99,8 +97,7 @@ match $__XILINX_RAMB18_SDP endmatch match $__XILINX_RAMB36_TDP - attribute ram_style=block ram_block=1 - attribute !ram_style + attribute !ram_style ram_style=block ram_block attribute !logic_block min bits 1024 min efficiency 5 @@ -110,8 +107,7 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - attribute ram_style=block ram_block=1 - attribute !ram_style + attribute !ram_style ram_style=block ram_block attribute !logic_block min bits 1024 min efficiency 5 From e990c013c57da8149dbbd2fe2633e953ec8f471b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:01:51 -0800 Subject: [PATCH 32/46] Merge blockram tests --- .../common/{blockram_params.v => blockram.v} | 0 tests/arch/xilinx/blockram.ys | 81 +++++++++++++++++++ tests/arch/xilinx/blockram_params.ys | 47 ----------- 3 files changed, 81 insertions(+), 47 deletions(-) rename tests/arch/common/{blockram_params.v => blockram.v} (100%) create mode 100644 tests/arch/xilinx/blockram.ys delete mode 100644 tests/arch/xilinx/blockram_params.ys diff --git a/tests/arch/common/blockram_params.v b/tests/arch/common/blockram.v similarity index 100% rename from tests/arch/common/blockram_params.v rename to tests/arch/common/blockram.v diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys new file mode 100644 index 000000000..362d33229 --- /dev/null +++ b/tests/arch/xilinx/blockram.ys @@ -0,0 +1,81 @@ +### TODO: Not running equivalence checking because BRAM models does not exists +### currently. Checking instance counts instead. +## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +## Anything memory bits < 1024 -> LUTRAM +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 0 t:RAMB18E1 +#select -assert-count 4 t:RAM128X1D +# +## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB36E1 +# +# +#### With parameters + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_block 1 m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set logic_block 1 m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 diff --git a/tests/arch/xilinx/blockram_params.ys b/tests/arch/xilinx/blockram_params.ys deleted file mode 100644 index 27a94834e..000000000 --- a/tests/arch/xilinx/blockram_params.ys +++ /dev/null @@ -1,47 +0,0 @@ -## TODO: Not running equivalence checking because BRAM models does not exists -## currently. Checking instance counts instead. -# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -# Anything memory bits < 1024 -> LUTRAM -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 -select -assert-count 4 t:RAM128X1D - -# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB36E1 - From 6b384861e4b1e02b24bf11d266cf11f461115cd8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:31:05 -0800 Subject: [PATCH 33/46] Oops --- passes/memory/memory_bram.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index a1353e56d..7ce5e80e1 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -333,12 +333,9 @@ struct rules_t for (int idx = 1; idx <= GetSize(tokens)-1; idx++) { size_t c1 = tokens[1][0] == '!' ? 1 : 0; size_t c2 = tokens[1].find("="); - if (c2 != std::string::npos) - c2--; - bool exists = (c1 == 0); IdString key = RTLIL::escape_id(tokens[1].substr(c1, c2)); - Const val = c2 != std::string::npos ? tokens[1].substr(c2) : RTLIL::Const(1); + Const val = c2 != std::string::npos ? tokens[1].substr(c2+1) : RTLIL::Const(1); data.attributes.back().emplace_back(exists, key, val); } From 5a00d5578cea91ce84f3d95e6138c85d1a949b89 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:31:15 -0800 Subject: [PATCH 34/46] Add unconditional match blocks for force RAM --- techlibs/xilinx/xc7_xcu_brams.txt | 44 ++++++++++++++++++++++++++----- tests/arch/xilinx/blockram.ys | 9 +++++++ 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 60425fed9..c63218ae1 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -77,7 +77,25 @@ endbram # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf match $__XILINX_RAMB36_SDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style + attribute !logic_block + min bits 1024 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB36_SDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_SDP + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -87,7 +105,15 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - attribute !ram_style ram_style=block ram_block + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB36_TDP + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -97,7 +123,15 @@ match $__XILINX_RAMB18_SDP endmatch match $__XILINX_RAMB36_TDP - attribute !ram_style ram_style=block ram_block + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_TDP + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -107,10 +141,8 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - attribute !ram_style ram_style=block ram_block + attribute ram_style=block ram_block attribute !logic_block - min bits 1024 - min efficiency 5 shuffle_enable B make_transp endmatch diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index 362d33229..b6e105854 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -79,3 +79,12 @@ setattr -set logic_block 1 m:memory synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +dump m:* +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 From db0003410ff35ab39e3ea408684f600e75c16e78 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:31:47 -0800 Subject: [PATCH 35/46] Accidentally commented out tests --- tests/arch/xilinx/blockram.ys | 94 +++++++++++++++++------------------ 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index b6e105854..4b7716739 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -1,52 +1,52 @@ ### TODO: Not running equivalence checking because BRAM models does not exists ### currently. Checking instance counts instead. -## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -## Anything memory bits < 1024 -> LUTRAM -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 0 t:RAMB18E1 -#select -assert-count 4 t:RAM128X1D -# -## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB36E1 -# -# -#### With parameters +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + + +### With parameters design -reset read_verilog ../common/blockram.v From 4158ce4eda4853e89187824daa32fcb57f6dfa27 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:56:45 -0800 Subject: [PATCH 36/46] More sloppiness, thanks @dh73 for spotting --- passes/memory/memory_bram.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 7ce5e80e1..29dc4ce07 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -331,11 +331,11 @@ struct rules_t if (GetSize(tokens) >= 2 && tokens[0] == "attribute") { data.attributes.emplace_back(); for (int idx = 1; idx <= GetSize(tokens)-1; idx++) { - size_t c1 = tokens[1][0] == '!' ? 1 : 0; - size_t c2 = tokens[1].find("="); + size_t c1 = tokens[idx][0] == '!' ? 1 : 0; + size_t c2 = tokens[idx].find("="); bool exists = (c1 == 0); - IdString key = RTLIL::escape_id(tokens[1].substr(c1, c2)); - Const val = c2 != std::string::npos ? tokens[1].substr(c2+1) : RTLIL::Const(1); + IdString key = RTLIL::escape_id(tokens[idx].substr(c1, c2)); + Const val = c2 != std::string::npos ? tokens[idx].substr(c2+1) : RTLIL::Const(1); data.attributes.back().emplace_back(exists, key, val); } From 378d9e6e0c16e13cf161aec283ab366e2462745c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:57:55 -0800 Subject: [PATCH 37/46] Add another test --- tests/arch/xilinx/blockram.ys | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index 4b7716739..bb908cbbf 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -84,7 +84,14 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory -dump m:* +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_block 1 m:memory synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 From 187e1c46e61dc910bf591625f7034b052ba928a7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 14:48:53 -0800 Subject: [PATCH 38/46] Update doc --- passes/memory/memory_bram.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 29dc4ce07..7f551134a 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -1314,10 +1314,12 @@ struct MemoryBramPass : public Pass { log(" dcells ....... number of cells in 'data-direction'\n"); log(" cells ........ total number of cells (acells*dcells*dups)\n"); log("\n"); - log("A match containing the condition 'attribute' followed by a name and optional\n"); - log("value requires that the memory contains the given attribute name and value\n"); - log("(if specified) or that the attribute is not present (prepending a '!')\n"); - log("or the value is empty (if value is not specified\n)."); + log("A match containing the command 'attribute' followed by a list of space\n"); + log("separated 'name[=string_value]' values requires that the memory contains any\n"); + log("one of the given attribute name and string values (where specified), or name\n"); + log("and integer 1 value (if no string_value given, since Verilog will interpret\n"); + log("'(* attr *)' as '(* attr=1 *)').\n"); + log("A name prefixed with '!' indicates that the attribute must not exist.\n"); log("\n"); log("The interface for the created bram instances is derived from the bram\n"); log("description. Use 'techmap' to convert the created bram instances into\n"); From 33e6d0558500d14e6711f7fc4ded1ebdb296bcaa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 17:06:30 -0800 Subject: [PATCH 39/46] Enforce non-existence --- passes/memory/memory_bram.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 7f551134a..e0970d192 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -841,6 +841,8 @@ grow_read_ports:; found = true; break; } + else if (!exists) + continue; if (it->second != value) continue; found = true; @@ -1165,6 +1167,8 @@ void handle_cell(Cell *cell, const rules_t &rules) found = true; break; } + else if (!exists) + continue; if (it->second != value) continue; found = true; From dccd7eb39f897f7fb04b038ee8ac11e676a8ea77 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 17 Dec 2019 00:25:08 -0800 Subject: [PATCH 40/46] Cleanup --- passes/memory/memory_bram.cc | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index e0970d192..24478f2ee 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -330,7 +330,7 @@ struct rules_t if (GetSize(tokens) >= 2 && tokens[0] == "attribute") { data.attributes.emplace_back(); - for (int idx = 1; idx <= GetSize(tokens)-1; idx++) { + for (int idx = 1; idx < GetSize(tokens); idx++) { size_t c1 = tokens[idx][0] == '!' ? 1 : 0; size_t c2 = tokens[idx].find("="); bool exists = (c1 == 0); @@ -854,12 +854,10 @@ grow_read_ports:; if (!exists) ss << "!"; IdString key = std::get<1>(sums.front()); - ss << key.str(); + ss << log_id(key); const Const &value = std::get<2>(sums.front()); - if (exists) - ss << "="; - if (value != Const(1)) - ss << "\"" << value.decode_string() << "\""; + if (exists && value != Const(1)) + ss << "=\"" << value.decode_string() << "\""; log(" Rule for bram type %s rejected: requirement 'attribute %s ...' not met.\n", log_id(match.name), ss.str().c_str()); @@ -1180,12 +1178,10 @@ void handle_cell(Cell *cell, const rules_t &rules) if (!exists) ss << "!"; IdString key = std::get<1>(sums.front()); - ss << key.str(); + ss << log_id(key); const Const &value = std::get<2>(sums.front()); - if (exists) - ss << "="; - if (value != Const(1)) - ss << "\"" << value.decode_string() << "\""; + if (exists && value != Const(1)) + ss << "=\"" << value.decode_string() << "\""; log(" Rule for bram type %s (variant %d) rejected: requirement 'attribute %s ...' not met.\n", log_id(bram.name), bram.variant, ss.str().c_str()); From 3671ecc7d0b3792c61ceee858435b3b75ad4739c Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Wed, 18 Dec 2019 12:30:30 +0100 Subject: [PATCH 41/46] use extra_args --- passes/cmds/scratchpad.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index 805badc7e..7ec55b78e 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -122,9 +122,9 @@ struct ScratchpadPass : public Pass { log_error("Assertion failed: scratchpad entry '%s' is defined\n", identifier.c_str()); continue; } - log("Unrecognized argument: %s\n", args[argidx].c_str()); break; } + extra_args(args, argidx, design, false); } } ScratchpadPass; PRIVATE_NAMESPACE_END From 22dd9f107c8986463041709aabcd0c886c87d33f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 18 Dec 2019 13:06:34 +0100 Subject: [PATCH 42/46] Send people to symbioticeda.com instead of verific.com Signed-off-by: Clifford Wolf --- frontends/verific/README | 8 ++++++-- frontends/verific/verific.cc | 23 ++++++++++++++++++++--- 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/frontends/verific/README b/frontends/verific/README index 89584f2e8..c37d76343 100644 --- a/frontends/verific/README +++ b/frontends/verific/README @@ -1,7 +1,11 @@ - This directory contains Verific bindings for Yosys. -See http://www.verific.com/ for details. + +Use Symbiotic EDA Suite if you need Yosys+Verifc. +https://www.symbioticeda.com/seda-suite + +Contact office@symbioticeda.com for free evaluation +binaries of Symbiotic EDA Suite. Verific Features that should be enabled in your Verific library diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 843e7b9b4..9274cf5ca 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2065,7 +2065,12 @@ struct VerificPass : public Pass { log(" -d \n"); log(" Dump the Verific netlist as a verilog file.\n"); log("\n"); - log("Visit http://verific.com/ for more information on Verific.\n"); + log("\n"); + log("Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"); + log("https://www.symbioticeda.com/seda-suite\n"); + log("\n"); + log("Contact office@symbioticeda.com for free evaluation\n"); + log("binaries of Symbiotic EDA Suite.\n"); log("\n"); } #ifdef YOSYS_ENABLE_VERIFIC @@ -2074,7 +2079,13 @@ struct VerificPass : public Pass { static bool set_verific_global_flags = true; if (check_noverific_env()) - log_cmd_error("This version of Yosys is built without Verific support.\n"); + log_cmd_error("This version of Yosys is built without Verific support.\n" + "\n" + "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n" + "https://www.symbioticeda.com/seda-suite\n" + "\n" + "Contact office@symbioticeda.com for free evaluation\n" + "binaries of Symbiotic EDA Suite.\n"); log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n"); @@ -2493,7 +2504,13 @@ struct VerificPass : public Pass { } #else /* YOSYS_ENABLE_VERIFIC */ void execute(std::vector, RTLIL::Design *) YS_OVERRIDE { - log_cmd_error("This version of Yosys is built without Verific support.\n"); + log_cmd_error("This version of Yosys is built without Verific support.\n" + "\n" + "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n" + "https://www.symbioticeda.com/seda-suite\n" + "\n" + "Contact office@symbioticeda.com for free evaluation\n" + "binaries of Symbiotic EDA Suite.\n"); } #endif } VerificPass; From aff6ad1ce09264fb7fbf43a7456a746a586bea90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Thu, 21 Nov 2019 06:30:06 +0100 Subject: [PATCH 43/46] xilinx: Improve flip-flop handling. This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. --- CHANGELOG | 2 + techlibs/xilinx/cells_map.v | 27 ++++++ techlibs/xilinx/synth_xilinx.cc | 15 ++- techlibs/xilinx/xc6s_ff_map.v | 166 +++++++++++++++++++++++++------- techlibs/xilinx/xc7_ff_map.v | 102 ++++++++++++++++---- tests/arch/xilinx/adffs.ys | 9 +- tests/arch/xilinx/fsm.ys | 11 ++- tests/arch/xilinx/macc.ys | 3 +- 8 files changed, 264 insertions(+), 71 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index a49c27b05..cb2b7bf0c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -50,6 +50,8 @@ Yosys 0.9 .. Yosys 0.9-dev - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) - "synth_ice40 -dsp" to infer DSP blocks - Added latch support to synth_xilinx + - Added support for flip-flops with synchronous reset to synth_xilinx + - Added support for flip-flops with reset and enable to synth_xilinx - Added "check -mapped" - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index de2068bc5..cc180f2b9 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -28,6 +28,33 @@ module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPL (* techmap_celltype = "$_DFF_PN1_" *) module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$__DFFE_NN0" *) +module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFE_PN0" *) +module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFE_NN1" *) +module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFE_PN1" *) +module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule + +(* techmap_celltype = "$__DFFS_NN0_" *) +module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$__DFFS_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$__DFFS_PN0_" *) +module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$__DFFS_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$__DFFS_NN1_" *) +module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$__DFFS_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$__DFFS_PN1_" *) +module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$__DFFS_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule + +(* techmap_celltype = "$__DFFSE_NN0" *) +module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFSE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFSE_PN0" *) +module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFSE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFSE_NN1" *) +module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFSE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFSE_PN1" *) +module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFSE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule + module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; parameter [DEPTH-1:0] INIT = 0; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2c5686a35..a061c8dc0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -444,6 +444,16 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_ffram")) { + // Required for dffsr2dff to work. + run("simplemap t:$dff t:$adff t:$mux"); + // Needs to be done before opt -mux_bool happens. + run("dffsr2dff"); + if (help_mode) + run("dff2dffs [-match-init]", "(-match-init for xc6s only)"); + else if (family == "xc6s") + run("dff2dffs -match-init"); + else + run("dff2dffs"); if (widemux > 0) run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover // performs less efficiently @@ -453,14 +463,11 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("fine")) { - run("dffsr2dff"); - run("dff2dffe"); + run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); if (help_mode) { - run("simplemap t:$mux", " ('-widemux' only)"); run("muxcover , ('-widemux' only)"); } else if (widemux > 0) { - run("simplemap t:$mux"); constexpr int cost_mux2 = 100; std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2); switch (widemux) { diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v index bf35b09e5..c40f446e0 100644 --- a/techlibs/xilinx/xc6s_ff_map.v +++ b/techlibs/xilinx/xc6s_ff_map.v @@ -27,6 +27,8 @@ `ifndef _NO_FFS +// No reset. + module \$_DFF_N_ (input D, C, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) @@ -46,6 +48,8 @@ module \$_DFF_P_ (input D, C, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// No reset, enable. + module \$_DFFE_NP_ (input D, C, E, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) @@ -65,15 +69,8 @@ module \$_DFFE_PP_ (input D, C, E, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); - else - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule +// Async reset. + module \$_DFF_NP0_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) @@ -83,15 +80,6 @@ module \$_DFF_NP0_ (input D, C, R, output Q); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); - else - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule module \$_DFF_PP0_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) @@ -102,15 +90,6 @@ module \$_DFF_PP0_ (input D, C, R, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); - else - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule module \$_DFF_NP1_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) @@ -120,15 +99,6 @@ module \$_DFF_NP1_ (input D, C, R, output Q); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); - else - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule module \$_DFF_PP1_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) @@ -139,6 +109,128 @@ module \$_DFF_PP1_ (input D, C, R, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// Async reset, enable. + +module \$__DFFE_NP0 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); + else + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFE_PP0 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); + else + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFE_NP1 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); + else + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFE_PP1 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); + else + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset. + +module \$__DFFS_NP0_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with reset initialized to 1"); + else + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFS_PP0_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with reset initialized to 1"); + else + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFS_NP1_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with set initialized to 0"); + else + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with set initialized to 0"); + else + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset, enable. + +module \$__DFFSE_NP0 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with reset initialized to 1"); + else + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP0 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with reset initialized to 1"); + else + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFSE_NP1 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with set initialized to 0"); + else + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP1 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with set initialized to 0"); + else + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches (no reset). + module \$_DLATCH_N_ (input E, D, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) @@ -158,5 +250,7 @@ module \$_DLATCH_P_ (input E, D, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// Latches with reset (TODO). + `endif diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v index 32ca9f560..2bd874457 100644 --- a/techlibs/xilinx/xc7_ff_map.v +++ b/techlibs/xilinx/xc7_ff_map.v @@ -37,6 +37,8 @@ `ifndef _NO_FFS +// No reset. + module \$_DFF_N_ (input D, C, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); @@ -48,6 +50,8 @@ module \$_DFF_P_ (input D, C, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// No reset, enable. + module \$_DFFE_NP_ (input D, C, E, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); @@ -59,48 +63,104 @@ module \$_DFFE_PP_ (input D, C, E, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule +// Async reset. + module \$_DFF_NP0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule module \$_DFF_PP0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule module \$_DFF_NP1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule module \$_DFF_PP1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// Async reset, enable. + +module \$__DFFE_NP0 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFE_PP0 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFE_NP1 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFE_PP1 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset. + +module \$__DFFS_NP0_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFS_PP0_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFS_NP1_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset, enable. + +module \$__DFFSE_NP0 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP0 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFSE_NP1 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP1 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches (no reset). + module \$_DLATCH_N_ (input E, D, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); @@ -112,5 +172,7 @@ module \$_DLATCH_P_ (input E, D, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// Latches with reset (TODO). + `endif diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index e73bfe0b9..c0ff6a2e2 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -32,10 +32,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivale design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 1 t:FDRE -select -assert-count 1 t:LUT2 +select -assert-count 1 t:FDSE -select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDSE %% t:* %D design -load read @@ -46,6 +45,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 -select -assert-count 1 t:LUT2 +select -assert-count 1 t:INV -select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 2a72c34e8..4545cf6d7 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -11,8 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 5 t:FDRE -select -assert-count 1 t:LUT3 -select -assert-count 2 t:LUT4 -select -assert-count 4 t:LUT6 -select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D +select -assert-count 4 t:FDRE +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT2 +select -assert-count 2 t:LUT3 +select -assert-count 4 t:LUT5 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 6e884b35a..11e959976 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -23,9 +23,10 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd macc2 # Constrain all select calls below inside the top module + select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 -select -assert-count 41 t:LUT3 +select -assert-count 40 t:LUT3 select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D From a2352504031ee69efd0aac214fc947737303eb5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 18 Dec 2019 13:42:26 +0100 Subject: [PATCH 44/46] xilinx: Add xilinx_dffopt pass (#1557) --- CHANGELOG | 1 + passes/equiv/equiv_opt.cc | 18 +- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/cells_sim.v | 35 ++ techlibs/xilinx/cells_xtra.py | 2 +- techlibs/xilinx/cells_xtra.v | 21 -- techlibs/xilinx/synth_xilinx.cc | 1 + techlibs/xilinx/xilinx_dffopt.cc | 351 ++++++++++++++++++ tests/arch/xilinx/fsm.ys | 6 +- tests/arch/xilinx/xilinx_dffopt.ys | 216 +++++++++++ tests/arch/xilinx/xilinx_dffopt_blacklist.txt | 13 + 11 files changed, 638 insertions(+), 27 deletions(-) create mode 100644 techlibs/xilinx/xilinx_dffopt.cc create mode 100644 tests/arch/xilinx/xilinx_dffopt.ys create mode 100644 tests/arch/xilinx/xilinx_dffopt_blacklist.txt diff --git a/CHANGELOG b/CHANGELOG index cb2b7bf0c..9b87af8f0 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -55,6 +55,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "check -mapped" - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) + - Added "xilinx_dffopt" pass Yosys 0.8 .. Yosys 0.9 ---------------------- diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index c7e6d71a6..7c6c2e685 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -44,6 +44,10 @@ struct EquivOptPass:public ScriptPass log(" expand the modules in this file before proving equivalence. this is\n"); log(" useful for handling architecture-specific primitives.\n"); log("\n"); + log(" -blacklist \n"); + log(" Do not match cells or signals that match the names in the file\n"); + log(" (passed to equiv_make).\n"); + log("\n"); log(" -assert\n"); log(" produce an error if the circuits are not equivalent.\n"); log("\n"); @@ -61,13 +65,14 @@ struct EquivOptPass:public ScriptPass log("\n"); } - std::string command, techmap_opts; + std::string command, techmap_opts, make_opts; bool assert, undef, multiclock, async2sync; void clear_flags() YS_OVERRIDE { command = ""; techmap_opts = ""; + make_opts = ""; assert = false; undef = false; multiclock = false; @@ -93,6 +98,10 @@ struct EquivOptPass:public ScriptPass techmap_opts += " -map " + args[++argidx]; continue; } + if (args[argidx] == "-blacklist" && argidx + 1 < args.size()) { + make_opts += " -blacklist " + args[++argidx]; + continue; + } if (args[argidx] == "-assert") { assert = true; continue; @@ -170,7 +179,12 @@ struct EquivOptPass:public ScriptPass run("clk2fflogic", "(only with -multiclock)"); if (async2sync || help_mode) run("async2sync", " (only with -async2sync)"); - run("equiv_make gold gate equiv"); + string opts; + if (help_mode) + opts = " -blacklist ..."; + else + opts = make_opts; + run("equiv_make" + opts + " gold gate equiv"); if (help_mode) run("equiv_induct [-undef] equiv"); else if (undef) diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 3ebc72fe8..3f2fbcc85 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -1,5 +1,6 @@ OBJS += techlibs/xilinx/synth_xilinx.o +OBJS += techlibs/xilinx/xilinx_dffopt.o GENFILES += techlibs/xilinx/brams_init_36.vh GENFILES += techlibs/xilinx/brams_init_32.vh diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index f9ce496ff..cf7923777 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -329,6 +329,41 @@ module FDSE ( endcase endgenerate endmodule +module FDRSE ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + (* invertible_pin = "IS_CE_INVERTED" *) + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_R_INVERTED" *) + input R, + (* invertible_pin = "IS_S_INVERTED" *) + input S +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + initial Q <= INIT; + wire c = C ^ IS_C_INVERTED; + wire ce = CE ^ IS_CE_INVERTED; + wire d = D ^ IS_D_INVERTED; + wire r = R ^ IS_R_INVERTED; + wire s = S ^ IS_S_INVERTED; + always @(posedge c) + if (r) + Q <= 0; + else if (s) + Q <= 1; + else if (ce) + Q <= d; +endmodule + module FDCE ( (* abc9_arrival=303 *) output reg Q, diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index e4c580b9d..6d5adf1aa 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -66,7 +66,7 @@ CELLS = [ # CLB -- registers/latches. # Virtex 1/2/4/5, Spartan 3. Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}), - Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), + # Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}), # Virtex 6, Spartan 6, Series 7, Ultrascale. # Cell('FDCE'), diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 8ac596459..66b7c583f 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -17,27 +17,6 @@ module FDCPE (...); input PRE; endmodule -module FDRSE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - (* invertible_pin = "IS_R_INVERTED" *) - input R; - (* invertible_pin = "IS_S_INVERTED" *) - input S; -endmodule - module LDCPE (...); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a061c8dc0..971089b28 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -570,6 +570,7 @@ struct SynthXilinxPass : public ScriptPass else techmap_args += " -map " + ff_map_file; run("techmap " + techmap_args); + run("xilinx_dffopt"); run("clean"); } diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc new file mode 100644 index 000000000..1256a08cb --- /dev/null +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -0,0 +1,351 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +typedef std::pair> LutData; + +// Compute a LUT implementing (select ^ select_inv) ? alt_data : data. Returns true if successful. +bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) { + // First, gather input signals. + result.second = data.second; + int idx_alt = -1; + if (alt_data.wire) { + // Check if we already have it. + for (int i = 0; i < GetSize(result.second); i++) + if (result.second[i] == alt_data) + idx_alt = i; + // If not, add it. + if (idx_alt == -1) { + idx_alt = GetSize(result.second); + result.second.push_back(alt_data); + } + } + std::vector idx_sel; + for (auto bit : select.second) { + int idx = -1; + for (int i = 0; i < GetSize(result.second); i++) + if (result.second[i] == bit) + idx = i; + if (idx == -1) { + idx = GetSize(result.second); + result.second.push_back(bit); + } + idx_sel.push_back(idx); + } + + // If LUT would be too large, bail. + if (GetSize(result.second) > max_lut_size) + return false; + + // Okay, we're doing it — compute the LUT mask. + result.first = Const(0, 1 << GetSize(result.second)); + for (int i = 0; i < GetSize(result.first); i++) { + int sel_lut_idx = 0; + for (int j = 0; j < GetSize(select.second); j++) + if (i & 1 << idx_sel[j]) + sel_lut_idx |= 1 << j; + bool select_val = (select.first.bits[sel_lut_idx] == State::S1); + bool new_bit; + if (select_val ^ select_inv) { + // Use alt_data. + if (alt_data.wire) + new_bit = (i & 1 << idx_alt) != 0; + else + new_bit = alt_data.data == State::S1; + } else { + // Use original LUT. + int lut_idx = i & ((1 << GetSize(data.second)) - 1); + new_bit = data.first.bits[lut_idx] == State::S1; + } + result.first.bits[i] = new_bit ? State::S1 : State::S0; + } + return true; +} + +struct XilinxDffOptPass : public Pass { + XilinxDffOptPass() : Pass("xilinx_dffopt", "Xilinx: optimize FF control signal usage") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" xilinx_dffopt [options] [selection]\n"); + log("\n"); + log("Converts hardware clock enable and set/reset signals on FFs to emulation\n"); + log("using LUTs, if doing so would improve area. Operates on post-techmap Xilinx\n"); + log("cells (LUT*, FD*).\n"); + log("\n"); + log(" -lut4\n"); + log(" Assume a LUT4-based device (instead of a LUT6-based device).\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing XILINX_DFFOPT pass (optimize FF control signal usage).\n"); + + size_t argidx; + int max_lut_size = 6; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-lut4") { + max_lut_size = 4; + continue; + } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + log("Optimizing FFs in %s.\n", log_id(module)); + + SigMap sigmap(module); + dict> bit_to_lut; + dict bit_uses; + + // Gather LUTs. + for (auto cell : module->selected_cells()) + { + for (auto port : cell->connections()) + for (auto bit : port.second) + bit_uses[sigmap(bit)]++; + if (cell->get_bool_attribute(ID::keep)) + continue; + if (cell->type == ID(INV)) { + SigBit sigout = sigmap(cell->getPort(ID(O))); + SigBit sigin = sigmap(cell->getPort(ID(I))); + bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell); + } else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) { + SigBit sigout = sigmap(cell->getPort(ID(O))); + const Const &init = cell->getParam(ID(INIT)); + std::vector sigin; + sigin.push_back(sigmap(cell->getPort(ID(I0)))); + if (cell->type == ID(LUT1)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I1)))); + if (cell->type == ID(LUT2)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I2)))); + if (cell->type == ID(LUT3)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I3)))); + if (cell->type == ID(LUT4)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I4)))); + if (cell->type == ID(LUT5)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I5)))); +lut_sigin_done: + bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell); + } + } + for (auto wire : module->wires()) + if (wire->port_output || wire->port_input) + for (int i = 0; i < GetSize(wire); i++) + bit_uses[sigmap(SigBit(wire, i))]++; + + // Iterate through FFs. + for (auto cell : module->selected_cells()) + { + bool has_s = false, has_r = false; + if (cell->type.in(ID(FDCE), ID(FDPE), ID(FDCPE), ID(FDCE_1), ID(FDPE_1), ID(FDCPE_1))) { + // Async reset. + } else if (cell->type.in(ID(FDRE), ID(FDRE_1))) { + has_r = true; + } else if (cell->type.in(ID(FDSE), ID(FDSE_1))) { + has_s = true; + } else if (cell->type.in(ID(FDRSE), ID(FDRSE_1))) { + has_r = true; + has_s = true; + } else { + // Not a FF. + continue; + } + if (cell->get_bool_attribute(ID::keep)) + continue; + + // Don't bother if D has more than one use. + SigBit sig_D = sigmap(cell->getPort(ID(D))); + if (bit_uses[sig_D] > 2) + continue; + + // Find the D LUT. + auto it_D = bit_to_lut.find(sig_D); + if (it_D == bit_to_lut.end()) + continue; + LutData lut_d = it_D->second.first; + Cell *cell_d = it_D->second.second; + if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) { + // Flip all bits in the LUT. + for (int i = 0; i < GetSize(lut_d.first); i++) + lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1; + } + + LutData lut_d_post_ce; + LutData lut_d_post_s; + LutData lut_d_post_r; + bool worthy_post_ce = false; + bool worthy_post_s = false; + bool worthy_post_r = false; + + // First, unmap CE. + SigBit sig_Q = sigmap(cell->getPort(ID(Q))); + SigBit sig_CE = sigmap(cell->getPort(ID(CE))); + LutData lut_ce = LutData(Const(2, 2), {sig_CE}); + auto it_CE = bit_to_lut.find(sig_CE); + if (it_CE != bit_to_lut.end()) + lut_ce = it_CE->second.first; + if (sig_CE.wire) { + // Merge CE LUT and D LUT into one. If it cannot be done, nothing to do about this FF. + if (!merge_lut(lut_d_post_ce, lut_d, lut_ce, true, sig_Q, max_lut_size)) + continue; + + // If this gets rid of a CE LUT, it's worth it. If not, it still may be worth it, if we can remove set/reset as well. + if (it_CE != bit_to_lut.end()) + worthy_post_ce = true; + } else if (sig_CE.data != State::S1) { + // Strange. Should not happen in a reasonable flow, so bail. + continue; + } else { + lut_d_post_ce = lut_d; + } + + // Second, unmap S, if any. + lut_d_post_s = lut_d_post_ce; + if (has_s) { + SigBit sig_S = sigmap(cell->getPort(ID(S))); + LutData lut_s = LutData(Const(2, 2), {sig_S}); + bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool(); + auto it_S = bit_to_lut.find(sig_S); + if (it_S != bit_to_lut.end()) + lut_s = it_S->second.first; + if (sig_S.wire) { + // Merge S LUT and D LUT into one. If it cannot be done, try to at least merge CE. + if (!merge_lut(lut_d_post_s, lut_d_post_ce, lut_s, inv_s, SigBit(State::S1), max_lut_size)) + goto unmap; + // If this gets rid of an S LUT, it's worth it. + if (it_S != bit_to_lut.end()) + worthy_post_s = true; + } else if (sig_S.data != (inv_s ? State::S1 : State::S0)) { + // Strange. Should not happen in a reasonable flow, so bail. + continue; + } + } + + // Third, unmap R, if any. + lut_d_post_r = lut_d_post_s; + if (has_r) { + SigBit sig_R = sigmap(cell->getPort(ID(R))); + LutData lut_r = LutData(Const(2, 2), {sig_R}); + bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool(); + auto it_R = bit_to_lut.find(sig_R); + if (it_R != bit_to_lut.end()) + lut_r = it_R->second.first; + if (sig_R.wire) { + // Merge R LUT and D LUT into one. If it cannot be done, try to at least merge CE/S. + if (!merge_lut(lut_d_post_r, lut_d_post_s, lut_r, inv_r, SigBit(State::S0), max_lut_size)) + goto unmap; + // If this gets rid of an S LUT, it's worth it. + if (it_R != bit_to_lut.end()) + worthy_post_r = true; + } else if (sig_R.data != (inv_r ? State::S1 : State::S0)) { + // Strange. Should not happen in a reasonable flow, so bail. + continue; + } + } + +unmap: + LutData final_lut; + if (worthy_post_r) { + final_lut = lut_d_post_r; + log(" Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + } else if (worthy_post_s) { + final_lut = lut_d_post_s; + log(" Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + } else if (worthy_post_ce) { + final_lut = lut_d_post_ce; + log(" Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + } else { + // Nothing to do here. + continue; + } + + // Okay, we're doing it. Unmap ports. + if (worthy_post_r) { + cell->unsetParam(ID(IS_R_INVERTED)); + cell->setPort(ID(R), Const(0, 1)); + } + if (has_s && (worthy_post_r || worthy_post_s)) { + cell->unsetParam(ID(IS_S_INVERTED)); + cell->setPort(ID(S), Const(0, 1)); + } + cell->setPort(ID(CE), Const(1, 1)); + cell->unsetParam(ID(IS_D_INVERTED)); + + // Create the new LUT. + Cell *lut_cell = 0; + switch (GetSize(final_lut.second)) { + case 1: + lut_cell = module->addCell(NEW_ID, ID(LUT1)); + break; + case 2: + lut_cell = module->addCell(NEW_ID, ID(LUT2)); + break; + case 3: + lut_cell = module->addCell(NEW_ID, ID(LUT3)); + break; + case 4: + lut_cell = module->addCell(NEW_ID, ID(LUT4)); + break; + case 5: + lut_cell = module->addCell(NEW_ID, ID(LUT5)); + break; + case 6: + lut_cell = module->addCell(NEW_ID, ID(LUT6)); + break; + default: + log_assert(!"unknown lut size"); + } + lut_cell->attributes = cell_d->attributes; + Wire *lut_out = module->addWire(NEW_ID); + lut_cell->setParam(ID(INIT), final_lut.first); + cell->setPort(ID(D), lut_out); + lut_cell->setPort(ID(O), lut_out); + lut_cell->setPort(ID(I0), final_lut.second[0]); + if (GetSize(final_lut.second) >= 2) + lut_cell->setPort(ID(I1), final_lut.second[1]); + if (GetSize(final_lut.second) >= 3) + lut_cell->setPort(ID(I2), final_lut.second[2]); + if (GetSize(final_lut.second) >= 4) + lut_cell->setPort(ID(I3), final_lut.second[3]); + if (GetSize(final_lut.second) >= 5) + lut_cell->setPort(ID(I4), final_lut.second[4]); + if (GetSize(final_lut.second) >= 6) + lut_cell->setPort(ID(I5), final_lut.second[5]); + } + } + } +} XilinxDffOptPass; + +PRIVATE_NAMESPACE_END + diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 4545cf6d7..f03400fe7 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -14,6 +14,6 @@ select -assert-count 1 t:BUFG select -assert-count 4 t:FDRE select -assert-count 1 t:FDSE select -assert-count 1 t:LUT2 -select -assert-count 2 t:LUT3 -select -assert-count 4 t:LUT5 -select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D +select -assert-count 3 t:LUT5 +select -assert-count 1 t:LUT6 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys new file mode 100644 index 000000000..dc036acfd --- /dev/null +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -0,0 +1,216 @@ +read_verilog << EOT + +// FDRE, mergeable CE and R. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT6 +select -assert-count 3 t:LUT2 +select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDSE, mergeable CE and S, inversions. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDSE #(.IS_D_INVERTED(1'b1), .IS_S_INVERTED(1'b1)) ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT6 +select -assert-count 3 t:LUT2 +select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDCE, mergeable CE. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDCE ff (.D(tmp[0]), .CE(tmp[1]), .CLR(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDCE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDSE, mergeable CE and S, but CE only not worth it. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); + +FDSE ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT5 +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDRSE, mergeable CE, S, R. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h8)) lut2 (.I0(i[2]), .I1(i[0]), .O(tmp[2])); +LUT2 #(.INIT(4'h6)) lut3 (.I0(i[3]), .I1(i[4]), .O(tmp[3])); + +FDRSE ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .R(tmp[3]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDRSE +select -assert-count 1 t:LUT6 +select -assert-count 4 t:LUT2 +select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDRSE +select -assert-count 1 t:LUT4 +select -assert-count 4 t:LUT2 +select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D + +design -reset diff --git a/tests/arch/xilinx/xilinx_dffopt_blacklist.txt b/tests/arch/xilinx/xilinx_dffopt_blacklist.txt new file mode 100644 index 000000000..6a31a0cd3 --- /dev/null +++ b/tests/arch/xilinx/xilinx_dffopt_blacklist.txt @@ -0,0 +1,13 @@ +lut0 +lut1 +lut2 +lut3 +ff +ff.D +ff.R +ff.S +ff.CE +ff.d +ff.r +ff.s +ff.ce From f382164d6ed4e6fd6820322db5becf081a74f272 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 18 Dec 2019 15:53:20 +0100 Subject: [PATCH 45/46] tests/xilinx: fix flaky mux test --- tests/arch/xilinx/mux.ys | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 821d0fab7..388272449 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -40,6 +40,8 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT6 +select -assert-min 5 t:LUT6 +select -assert-max 7 t:LUT6 +select -assert-max 2 t:MUXF7 -select -assert-none t:LUT6 %% t:* %D +select -assert-none t:LUT6 t:MUXF7 %% t:* %D From f52c6efd9da161e625538f9e8c23875efebda60f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Dec 2019 12:09:11 -0800 Subject: [PATCH 46/46] Add "scratchpad" to CHANGELOG --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG b/CHANGELOG index 9b87af8f0..01ae17c2b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,6 +56,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) - Added "xilinx_dffopt" pass + - Added "scratchpad" pass Yosys 0.8 .. Yosys 0.9 ----------------------