mirror of https://github.com/YosysHQ/yosys.git
Fix issue #306, "Bug in opt -full"
Add check for whether the high bit in the constant expression is greater than the width of the variable, and optimizes that to a constant 1 or 0
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@ -1208,6 +1208,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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//width of the variable port
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//width of the variable port
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int width;
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int width;
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int const_width;
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bool var_signed;
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bool var_signed;
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@ -1216,6 +1217,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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sigVar = cell->getPort("\\A");
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sigVar = cell->getPort("\\A");
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sigConst = cell->getPort("\\B");
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sigConst = cell->getPort("\\B");
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width = cell->parameters["\\A_WIDTH"].as_int();
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width = cell->parameters["\\A_WIDTH"].as_int();
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const_width = cell->parameters["\\B_WIDTH"].as_int();
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var_signed = cell->parameters["\\A_SIGNED"].as_bool();
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var_signed = cell->parameters["\\A_SIGNED"].as_bool();
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} else
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} else
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if (cell->type == "$gt" || cell->type == "$le") {
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if (cell->type == "$gt" || cell->type == "$le") {
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@ -1223,6 +1225,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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sigVar = cell->getPort("\\B");
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sigVar = cell->getPort("\\B");
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sigConst = cell->getPort("\\A");
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sigConst = cell->getPort("\\A");
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width = cell->parameters["\\B_WIDTH"].as_int();
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width = cell->parameters["\\B_WIDTH"].as_int();
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const_width = cell->parameters["\\A_WIDTH"].as_int();
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var_signed = cell->parameters["\\B_SIGNED"].as_bool();
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var_signed = cell->parameters["\\B_SIGNED"].as_bool();
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}
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}
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@ -1265,7 +1268,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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int const_bit_set = get_onehot_bit_index(sigConst);
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int const_bit_set = get_onehot_bit_index(sigConst);
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if (const_bit_set >= 0) {
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if (const_bit_set >= 0 && const_bit_set < width) {
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int bit_set = const_bit_set;
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int bit_set = const_bit_set;
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RTLIL::SigSpec a_prime(RTLIL::State::S0, width - bit_set);
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RTLIL::SigSpec a_prime(RTLIL::State::S0, width - bit_set);
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for (int i = bit_set; i < width; i++) {
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for (int i = bit_set; i < width; i++) {
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@ -1284,6 +1287,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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did_something = true;
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did_something = true;
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goto next_cell;
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goto next_cell;
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}
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}
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else if(const_bit_set >= width && const_bit_set >= 0){
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RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
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if(is_lt){
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a_prime[0] = RTLIL::State::S1;
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log("Replacing %s cell `%s' (implementing unsigned X[%d:0] < %s[%d:0]) with constant 0.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
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}
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else{
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log("Replacing %s cell `%s' (implementing unsigned X[%d:0]>= %s[%d:0]) with constant 1.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
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}
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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}
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}
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}
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}
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