Use selection helpers

Catch more uses of selection constructor without assigning a design.

backends/rtlil/rtlil_backend.cc

@@ -304,8 +304,8 @@ void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::
 
 void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
 {
-	bool print_header = flag_m || design->selected_whole_module(module->name);
+	bool print_header = flag_m || module->is_selected_whole();
-	bool print_body = !flag_n || !design->selected_whole_module(module->name);
+	bool print_body = !flag_n || !module->is_selected_whole();
 
 	if (print_header)
 	{

docs/source/code_examples/extensions/my_cmd.cc

@@ -51,10 +51,10 @@ struct Test2Pass : public Pass {
     Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
     void execute(std::vector<std::string>, RTLIL::Design *design) override
     {
-        if (design->selection_stack.back().empty())
+        if (design->selection().empty())
             log_cmd_error("This command can't operator on an empty selection!\n");
 
-        RTLIL::Module *module = design->modules_.at("\\test");
+        RTLIL::Module *module = design->module("\\test");
 
         RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")), y(module->wire("\\y"));
         log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"

docs/source/yosys_internals/extending_yosys/extensions.rst

@@ -241,7 +241,7 @@ Use ``log_cmd_error()`` to report a recoverable error:
 
 .. code:: C++
 
-    if (design->selection_stack.back().empty())
+    if (design->selection().empty())
         log_cmd_error("This command can't operator on an empty selection!\n");
 
 Use ``log_assert()`` and ``log_abort()`` instead of ``assert()`` and ``abort()``.

kernel/driver.cc

@@ -106,7 +106,7 @@ void run(const char *command)
 		log_last_error = "";
 	} catch (...) {
 		while (GetSize(yosys_get_design()->selection_stack) > selSize)
-			yosys_get_design()->selection_stack.pop_back();
+			yosys_get_design()->pop_selection();
 		throw;
 	}
 }

kernel/register.cc

@@ -318,18 +318,18 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
 	pass_register[args[0]]->execute(args, design);
 	pass_register[args[0]]->post_execute(state);
 	while (design->selection_stack.size() > orig_sel_stack_pos)
-		design->selection_stack.pop_back();
+		design->pop_selection();
 }
 
 void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
 {
 	std::string backup_selected_active_module = design->selected_active_module;
 	design->selected_active_module.clear();
-	design->selection_stack.push_back(selection);
+	design->push_selection(selection);
 
 	Pass::call(design, command);
 
-	design->selection_stack.pop_back();
+	design->pop_selection();
 	design->selected_active_module = backup_selected_active_module;
 }
 
@@ -337,11 +337,11 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
 {
 	std::string backup_selected_active_module = design->selected_active_module;
 	design->selected_active_module.clear();
-	design->selection_stack.push_back(selection);
+	design->push_selection(selection);
 
 	Pass::call(design, args);
 
-	design->selection_stack.pop_back();
+	design->pop_selection();
 	design->selected_active_module = backup_selected_active_module;
 }
 
@@ -349,12 +349,12 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
 {
 	std::string backup_selected_active_module = design->selected_active_module;
 	design->selected_active_module = module->name.str();
-	design->selection_stack.push_back(RTLIL::Selection(false));
+	design->push_empty_selection();
-	design->selection_stack.back().select(module);
+	design->select(module);
 
 	Pass::call(design, command);
 
-	design->selection_stack.pop_back();
+	design->pop_selection();
 	design->selected_active_module = backup_selected_active_module;
 }
 
@@ -362,12 +362,12 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vec
 {
 	std::string backup_selected_active_module = design->selected_active_module;
 	design->selected_active_module = module->name.str();
-	design->selection_stack.push_back(RTLIL::Selection(false));
+	design->push_empty_selection();
-	design->selection_stack.back().select(module);
+	design->select(module);
 
 	Pass::call(design, args);
 
-	design->selection_stack.pop_back();
+	design->pop_selection();
 	design->selected_active_module = backup_selected_active_module;
 }
 
@@ -745,7 +745,7 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f
 	}
 
 	while (design->selection_stack.size() > orig_sel_stack_pos)
-		design->selection_stack.pop_back();
+		design->pop_selection();
 }
 
 struct SimHelper {

kernel/rtlil.cc

@@ -887,7 +887,7 @@ RTLIL::Design::Design()
 	hashidx_ = hashidx_count;
 
 	refcount_modules_ = 0;
-	selection_stack.push_back(RTLIL::Selection(true, false, this));
+	push_full_selection();
 
 #ifdef WITH_PYTHON
 	RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
@@ -1115,7 +1115,7 @@ bool RTLIL::Design::selected_module(const RTLIL::IdString& mod_name) const
 		return false;
 	if (selection_stack.size() == 0)
 		return true;
-	return selection_stack.back().selected_module(mod_name);
+	return selection().selected_module(mod_name);
 }
 
 bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const
@@ -1124,7 +1124,7 @@ bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const
 		return false;
 	if (selection_stack.size() == 0)
 		return true;
-	return selection_stack.back().selected_whole_module(mod_name);
+	return selection().selected_whole_module(mod_name);
 }
 
 bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL::IdString& memb_name) const
@@ -1133,7 +1133,7 @@ bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL
 		return false;
 	if (selection_stack.size() == 0)
 		return true;
-	return selection_stack.back().selected_member(mod_name, memb_name);
+	return selection().selected_member(mod_name, memb_name);
 }
 
 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const

kernel/rtlil.h

@@ -1254,7 +1254,7 @@ struct RTLIL::Design
 	}
 
 	bool full_selection() const {
-		return selection_stack.back().full_selection;
+		return selection().full_selection;
 	}
 
 	template<typename T1> bool selected(T1 *module) const {
@@ -1267,14 +1267,14 @@ struct RTLIL::Design
 
 	template<typename T1> void select(T1 *module) {
 		if (selection_stack.size() > 0) {
-			RTLIL::Selection &sel = selection_stack.back();
+			RTLIL::Selection &sel = selection();
 			sel.select(module);
 		}
 	}
 
 	template<typename T1, typename T2> void select(T1 *module, T2 *member) {
 		if (selection_stack.size() > 0) {
-			RTLIL::Selection &sel = selection_stack.back();
+			RTLIL::Selection &sel = selection();
 			sel.select(module, member);
 		}
 	}

kernel/yosys.cc

@@ -674,11 +674,11 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter)
 	str += "yosys";
 	if (!design->selected_active_module.empty())
 		str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str());
-	if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) {
+	if (!design->selection_stack.empty() && !design->full_selection()) {
 		if (design->selected_active_module.empty())
 			str += "*";
-		else if (design->selection_stack.back().selected_modules.size() != 1 || design->selection_stack.back().selected_members.size() != 0 ||
+		else if (design->selection().selected_modules.size() != 1 || design->selection().selected_members.size() != 0 ||
-				design->selection_stack.back().selected_modules.count(design->selected_active_module) == 0)
+				design->selection().selected_modules.count(design->selected_active_module) == 0)
 			str += "*";
 	}
 	snprintf(buffer, 100, "%s> ", str.c_str());
@@ -799,7 +799,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a
 		if (in_repl) {
 			auto design = yosys_get_design();
 			while (design->selection_stack.size() > 1)
-				design->selection_stack.pop_back();
+				design->pop_selection();
 			log_reset_stack();
 		}
 		Tcl_SetResult(interp, (char *)"Yosys command produced an error", TCL_STATIC);
@@ -1458,7 +1458,7 @@ void shell(RTLIL::Design *design)
 			Pass::call(design, command);
 		} catch (log_cmd_error_exception) {
 			while (design->selection_stack.size() > 1)
-				design->selection_stack.pop_back();
+				design->pop_selection();
 			log_reset_stack();
 		}
 		design->check();

passes/cmds/add.cc

@@ -102,7 +102,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 		RTLIL::Module *mod = design->module(cell->type);
 		if (mod == nullptr)
 			continue;
-		if (!design->selected_whole_module(mod->name))
+		if (!mod->is_selected_whole())
 			continue;
 		if (mod->get_blackbox_attribute())
 			continue;

passes/cmds/design.cc

@@ -216,8 +216,8 @@ struct DesignPass : public Pass {
 			RTLIL::Selection sel;
 			if (argidx != args.size()) {
 				handle_extra_select_args(this, args, argidx, args.size(), copy_from_design);
-				sel = copy_from_design->selection_stack.back();
+				sel = copy_from_design->selection();
-				copy_from_design->selection_stack.pop_back();
+				copy_from_design->pop_selection();
 				argidx = args.size();
 			}
 
@@ -368,7 +368,7 @@ struct DesignPass : public Pass {
 			design->selection_vars.clear();
 			design->selected_active_module.clear();
 
-			design->selection_stack.push_back(RTLIL::Selection());
+			design->push_full_selection();
 		}
 
 		if (reset_mode || reset_vlog_mode || !load_name.empty() || push_mode || pop_mode)

passes/cmds/scc.cc

@@ -340,7 +340,7 @@ struct SccPass : public Pass {
 		int origSelectPos = design->selection_stack.size() - 1;
 		extra_args(args, argidx, design);
 
-		RTLIL::Selection newSelection(false);
+		RTLIL::Selection newSelection(false, false, design);
 		int scc_counter = 0;
 
 		for (auto mod : design->selected_modules())

passes/cmds/select.cc

@@ -687,7 +687,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 	if (arg[0] == '%') {
 		if (arg == "%") {
 			if (design->selection_stack.size() > 0)
-				work_stack.push_back(design->selection_stack.back());
+				work_stack.push_back(design->selection());
 		} else
 		if (arg == "%%") {
 			while (work_stack.size() > 1) {
@@ -1031,9 +1031,9 @@ void handle_extra_select_args(Pass *pass, const vector<string> &args, size_t arg
 		work_stack.pop_back();
 	}
 	if (work_stack.empty())
-		design->selection_stack.push_back(RTLIL::Selection(false, false, design));
+		design->push_empty_selection();
 	else
-		design->selection_stack.push_back(work_stack.back());
+		design->push_selection(work_stack.back());
 }
 
 // extern decl. in register.h
@@ -1420,7 +1420,7 @@ struct SelectPass : public Pass {
 			if (f.fail())
 				log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno));
 
-			RTLIL::Selection sel(false);
+			RTLIL::Selection sel(false, false, design);
 			string line;
 
 			while (std::getline(f, line)) {
@@ -1461,7 +1461,7 @@ struct SelectPass : public Pass {
 			log_cmd_error("Option -unset can not be combined with -list, -write, -count, -set, %s.\n", common_flagset);
 
 		if (work_stack.size() == 0 && got_module) {
-			RTLIL::Selection sel;
+			RTLIL::Selection sel(true, false, design);
 			select_filter_active_mod(design, sel);
 			work_stack.push_back(sel);
 		}
@@ -1474,13 +1474,15 @@ struct SelectPass : public Pass {
 		log_assert(design->selection_stack.size() > 0);
 
 		if (clear_mode) {
-			design->selection_stack.back() = RTLIL::Selection(true, false, design);
+			design->pop_selection();
+			design->push_full_selection();
 			design->selected_active_module = std::string();
 			return;
 		}
 
 		if (none_mode) {
-			design->selection_stack.back() = RTLIL::Selection(false, false, design);
+			design->pop_selection();
+			design->push_empty_selection();
 			return;
 		}
 
@@ -1496,8 +1498,8 @@ struct SelectPass : public Pass {
 					log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno));
 			}
 			if (work_stack.size() > 0)
-				design->selection_stack.push_back(work_stack.back());
+				design->push_selection(work_stack.back());
-			RTLIL::Selection *sel = &design->selection_stack.back();
+			RTLIL::Selection *sel = &design->selection();
 			sel->optimize(design);
 			for (auto mod : design->selected_modules())
 			{
@@ -1515,7 +1517,7 @@ struct SelectPass : public Pass {
 			if (f != nullptr)
 				fclose(f);
 			if (work_stack.size() > 0)
-				design->selection_stack.pop_back();
+				design->pop_selection();
 		#undef LOG_OBJECT
 			return;
 		}
@@ -1524,8 +1526,8 @@ struct SelectPass : public Pass {
 		{
 			if (work_stack.size() == 0)
 				log_cmd_error("Nothing to add to selection.\n");
-			select_op_union(design, design->selection_stack.back(), work_stack.back());
+			select_op_union(design, design->selection(), work_stack.back());
-			design->selection_stack.back().optimize(design);
+			design->selection().optimize(design);
 			return;
 		}
 
@@ -1533,8 +1535,8 @@ struct SelectPass : public Pass {
 		{
 			if (work_stack.size() == 0)
 				log_cmd_error("Nothing to delete from selection.\n");
-			select_op_diff(design, design->selection_stack.back(), work_stack.back());
+			select_op_diff(design, design->selection(), work_stack.back());
-			design->selection_stack.back().optimize(design);
+			design->selection().optimize(design);
 			return;
 		}
 
@@ -1574,7 +1576,7 @@ struct SelectPass : public Pass {
 			if (work_stack.size() == 0)
 				log_cmd_error("No selection to check.\n");
 			RTLIL::Selection *sel = &work_stack.back();
-			design->selection_stack.push_back(*sel);
+			design->push_selection(*sel);
 			sel->optimize(design);
 			for (auto mod : design->selected_modules()) {
 				module_count++;
@@ -1604,7 +1606,7 @@ struct SelectPass : public Pass {
 				log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s",
 						total_count, assert_min, sel_str.c_str(), desc.c_str());
 			}
-			design->selection_stack.pop_back();
+			design->pop_selection();
 			return;
 		}
 
@@ -1625,7 +1627,7 @@ struct SelectPass : public Pass {
 		}
 
 		if (work_stack.size() == 0) {
-			RTLIL::Selection &sel = design->selection_stack.back();
+			RTLIL::Selection &sel = design->selection();
 			if (sel.full_selection)
 				log("*\n");
 			for (auto &it : sel.selected_modules)
@@ -1636,8 +1638,8 @@ struct SelectPass : public Pass {
 			return;
 		}
 
-		design->selection_stack.back() = work_stack.back();
+		design->selection() = work_stack.back();
-		design->selection_stack.back().optimize(design);
+		design->selection().optimize(design);
 	}
 } SelectPass;
 
@@ -1677,7 +1679,8 @@ struct CdPass : public Pass {
 			log_cmd_error("Invalid number of arguments.\n");
 
 		if (args.size() == 1 || args[1] == "/") {
-			design->selection_stack.back() = RTLIL::Selection(true, false, design);
+			design->pop_selection();
+			design->push_full_selection();
 			design->selected_active_module = std::string();
 			return;
 		}
@@ -1686,7 +1689,8 @@ struct CdPass : public Pass {
 		{
 			string modname = design->selected_active_module;
 
-			design->selection_stack.back() = RTLIL::Selection(true, false, design);
+			design->pop_selection();
+			design->push_full_selection();
 			design->selected_active_module = std::string();
 
 			while (1)
@@ -1703,9 +1707,10 @@ struct CdPass : public Pass {
 					continue;
 
 				design->selected_active_module = modname;
-				design->selection_stack.back() = RTLIL::Selection(true, false, design);
+				design->pop_selection();
-				select_filter_active_mod(design, design->selection_stack.back());
+				design->push_full_selection();
-				design->selection_stack.back().optimize(design);
+				select_filter_active_mod(design, design->selection());
+				design->selection().optimize(design);
 				return;
 			}
 
@@ -1722,9 +1727,10 @@ struct CdPass : public Pass {
 
 		if (design->module(modname) != nullptr) {
 			design->selected_active_module = modname;
-			design->selection_stack.back() = RTLIL::Selection(true, false, design);
+			design->pop_selection();
-			select_filter_active_mod(design, design->selection_stack.back());
+			design->push_full_selection();
-			design->selection_stack.back().optimize(design);
+			select_filter_active_mod(design, design->selection());
+			design->selection().optimize(design);
 			return;
 		}
 

passes/cmds/show.cc

@@ -802,8 +802,8 @@ struct ShowPass : public Pass {
 				std::pair<std::string, RTLIL::Selection> data;
 				data.first = args[++argidx], argidx++;
 				handle_extra_select_args(this, args, argidx, argidx+1, design);
-				data.second = design->selection_stack.back();
+				data.second = design->selection();
-				design->selection_stack.pop_back();
+				design->pop_selection();
 				color_selections.push_back(data);
 				continue;
 			}
@@ -811,8 +811,8 @@ struct ShowPass : public Pass {
 				std::pair<std::string, RTLIL::Selection> data;
 				data.first = args[++argidx], argidx++;
 				handle_extra_select_args(this, args, argidx, argidx+1, design);
-				data.second = design->selection_stack.back();
+				data.second = design->selection();
-				design->selection_stack.pop_back();
+				design->pop_selection();
 				label_selections.push_back(data);
 				continue;
 			}

passes/cmds/stat.cc

@@ -468,7 +468,7 @@ struct StatPass : public Pass {
 				first_module = false;
 			} else {
 				log("\n");
-				log("=== %s%s ===\n", log_id(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
+				log("=== %s%s ===\n", log_id(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
 				log("\n");
 				data.log_data(mod->name, false);
 			}

passes/cmds/viz.cc

@@ -950,8 +950,8 @@ struct VizPass : public Pass {
 				auto type = arg == "-g" || arg == "-G" ? VizConfig::TYPE_G :
 					arg == "-u" || arg == "-U" ? VizConfig::TYPE_U :
 					arg == "-x" || arg == "-X" ? VizConfig::TYPE_X : VizConfig::TYPE_S;
-				config.groups.push_back({type, design->selection_stack.back()});
+				config.groups.push_back({type, design->selection()});
-				design->selection_stack.pop_back();
+				design->pop_selection();
 				continue;
 			}
 			if (arg == "-0" || arg == "-1" || arg == "-2" || arg == "-3" || arg == "-4" ||

passes/hierarchy/submod.cc

@@ -246,7 +246,7 @@ struct SubmodWorker
 	SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, bool hidden_mode = false, std::string opt_name = std::string()) :
 			design(design), module(module), sigmap(module), copy_mode(copy_mode), hidden_mode(hidden_mode), opt_name(opt_name)
 	{
-		if (!design->selected_whole_module(module->name) && opt_name.empty())
+		if (!module->is_selected_whole() && opt_name.empty())
 			return;
 
 		if (module->processes.size() > 0) {

passes/sat/cutpoint.cc

@@ -57,7 +57,7 @@ struct CutpointPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		{
-			if (design->selected_whole_module(module->name)) {
+			if (module->is_selected_whole()) {
 				log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
 				module->new_connections(std::vector<RTLIL::SigSig>());
 				for (auto cell : vector<Cell*>(module->cells()))

passes/techmap/abc9.cc

@@ -400,7 +400,7 @@ struct Abc9Pass : public ScriptPass
 					}
 
 					log_push();
-					active_design->selection().select(mod);
+					active_design->select(mod);
 
 					if (!active_design->selected_whole_module(mod))
 						log_error("Can't handle partially selected module %s!\n", log_id(mod));
@@ -452,7 +452,7 @@ struct Abc9Pass : public ScriptPass
 					log_pop();
 				}
 
-				active_design->selection_stack.pop_back();
+				active_design->pop_selection();
 			}
 		}
 

passes/techmap/abc9_ops.cc

@@ -454,7 +454,7 @@ void prep_bypass(RTLIL::Design *design)
 
 void prep_dff(RTLIL::Design *design)
 {
-	auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false)));
+	auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false, false, design)));
 	auto &modules_sel = r.first->second;
 
 	for (auto module : design->selected_modules())

passes/techmap/abc_new.cc

@@ -128,7 +128,7 @@ struct AbcNewPass : public ScriptPass {
 					exe_options = abc_exe_options;
 					log_header(active_design, "Mapping module '%s'.\n", log_id(mod));
 					log_push();
-					active_design->selection().select(mod);
+					active_design->select(mod);
 				}
 
 				run(stringf("  abc9_ops -write_box %s/input.box", tmpdir.c_str()));
@@ -144,7 +144,7 @@ struct AbcNewPass : public ScriptPass {
 			}
 
 			if (!help_mode) {
-				active_design->selection_stack.pop_back();
+				active_design->pop_selection();
 			}
 		}
 	}

passes/techmap/aigmap.cc

@@ -172,7 +172,7 @@ struct AigmapPass : public Pass {
 
 			if (select_mode) {
 				log_assert(!design->selection_stack.empty());
-				RTLIL::Selection& sel = design->selection_stack.back();
+				RTLIL::Selection& sel = design->selection();
 				sel.selected_members[module->name] = std::move(new_sel);
 			}
 

passes/techmap/nlutmap.cc

@@ -42,7 +42,7 @@ struct NlutmapWorker
 
 	RTLIL::Selection get_selection()
 	{
-		RTLIL::Selection sel(false);
+		RTLIL::Selection sel(false, false, module->design);
 		for (auto cell : module->cells())
 			if (!mapped_cells.count(cell))
 				sel.select(module, cell);