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Renamed extend_un0() to extend_u0() and use it in genrtlil

This commit is contained in:
Clifford Wolf 2013-11-07 18:17:10 +01:00
parent 0e1661f84e
commit 947bd9b96b
4 changed files with 12 additions and 8 deletions
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12
frontends/ast/genrtlil.cc
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@ -966,7 +966,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_TO_UNSIGNED: { case AST_TO_UNSIGNED: {
RTLIL::SigSpec sig = children[0]->genRTLIL(); RTLIL::SigSpec sig = children[0]->genRTLIL();
if (sig.width < width_hint) if (sig.width < width_hint)
sig.extend(width_hint, sign_hint); sig.extend_u0(width_hint, sign_hint);
is_signed = sign_hint; is_signed = sign_hint;
return sig; return sig;
} }
@ -983,7 +983,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
} }
if (sig.width < width_hint) if (sig.width < width_hint)
sig.extend(width_hint, false); sig.extend_u0(width_hint, false);
return sig; return sig;
} }
@ -998,7 +998,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (int i = 0; i < count; i++) for (int i = 0; i < count; i++)
sig.append(right); sig.append(right);
if (sig.width < width_hint) if (sig.width < width_hint)
sig.extend(width_hint, false); sig.extend_u0(width_hint, false);
is_signed = false; is_signed = false;
return sig; return sig;
} }
@ -1153,7 +1153,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
widthExtend(this, val1, width, is_signed); widthExtend(this, val1, width, is_signed);
widthExtend(this, val2, width, is_signed); widthExtend(this, val2, width, is_signed);
return mux2rtlil(this, cond, val1, val2); RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
if (sig.width < width_hint)
sig.extend_u0(width_hint, sign_hint);
return sig;
} }
// generate $memrd cells for memory read ports // generate $memrd cells for memory read ports

2
kernel/rtlil.cc
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@ -940,7 +940,7 @@ void RTLIL::SigSpec::extend(int width, bool is_signed)
optimize(); optimize();
} }
void RTLIL::SigSpec::extend_un0(int width, bool is_signed) void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
{ {
if (this->width > width) if (this->width > width)
remove(width, this->width - width); remove(width, this->width - width);

2
kernel/rtlil.h
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@ -342,7 +342,7 @@ struct RTLIL::SigSpec {
void append(const RTLIL::SigSpec &signal); void append(const RTLIL::SigSpec &signal);
bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool override = false); bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool override = false);
void extend(int width, bool is_signed = false); void extend(int width, bool is_signed = false);
void extend_un0(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false);
void check() const; void check() const;
bool operator <(const RTLIL::SigSpec &other) const; bool operator <(const RTLIL::SigSpec &other) const;
bool operator ==(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const;

4
passes/opt/opt_const.cc
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@ -151,8 +151,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) { if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int()); int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
a.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()); a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
b.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()); b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
} }
RTLIL::SigSpec new_a, new_b; RTLIL::SigSpec new_a, new_b;