diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index fd5db188e..c2e320658 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -87,7 +87,6 @@ struct rules_t
 		tokens.clear();
 		string line;
 		while (std::getline(infile, line)) {
-			log("> %s\n", line.c_str());
 			for (string tok = next_token(line); !tok.empty(); tok = next_token(line)) {
 				if (tok[0] == '#')
 					break;
diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/brams.txt
index 69214fd59..0d039d78d 100644
--- a/techlibs/xilinx/brams.txt
+++ b/techlibs/xilinx/brams.txt
@@ -11,7 +11,7 @@ bram $__XILINX_RAMB36_SDP72
   clkpol 2 3
 endbram
 
-bram $__XILINX_RAMB36_SDP36
+bram $__XILINX_RAMB18_SDP36
   abits 10
   dbits 36
   groups 2
@@ -23,7 +23,7 @@ bram $__XILINX_RAMB36_SDP36
   clkpol 2 3
 endbram
 
-bram $__XILINX_RAMB36_SDP18
+bram $__XILINX_RAMB18_TDP18
   abits 11
   dbits 18
   groups 2
@@ -35,7 +35,7 @@ bram $__XILINX_RAMB36_SDP18
   clkpol 2 3
 endbram
 
-bram $__XILINX_RAMB36_SDP9
+bram $__XILINX_RAMB18_TDP9
   abits 12
   dbits 9
   groups 2
@@ -47,7 +47,7 @@ bram $__XILINX_RAMB36_SDP9
   clkpol 2 3
 endbram
 
-bram $__XILINX_RAMB36_SDP4
+bram $__XILINX_RAMB18_TDP4
   abits 13
   dbits 4
   groups 2
@@ -59,7 +59,7 @@ bram $__XILINX_RAMB36_SDP4
   clkpol 2 3
 endbram
 
-bram $__XILINX_RAMB36_SDP2
+bram $__XILINX_RAMB18_TDP2
   abits 14
   dbits 2
   groups 2
@@ -71,7 +71,7 @@ bram $__XILINX_RAMB36_SDP2
   clkpol 2 3
 endbram
 
-bram $__XILINX_RAMB36_SDP1
+bram $__XILINX_RAMB18_TDP1
   abits 15
   dbits 1
   groups 2
@@ -84,39 +84,36 @@ bram $__XILINX_RAMB36_SDP1
 endbram
 
 match $__XILINX_RAMB36_SDP72
+  min bits 4096
+  min efficiency 5
   shuffle_enable 8
-  # min efficiency 20
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAMB18_SDP36
+  min bits 4096
+  min efficiency 5
+  shuffle_enable 4
   # or_next_if_better
 endmatch
 
-# match $__XILINX_RAMB36_SDP36
-#   shuffle_enable 4
-#   min efficiency 20
-#   or_next_if_better
-# endmatch
-#
-# match $__XILINX_RAMB36_SDP18
+# match $__XILINX_RAMB18_TDP18
 #   shuffle_enable 2
-#   min efficiency 20
+#   or_next_if_better
+# endmatch
+# 
+# match $__XILINX_RAMB18_TDP9
 #   or_next_if_better
 # endmatch
 #
-# match $__XILINX_RAMB36_SDP9
-#   min efficiency 20
+# match $__XILINX_RAMB18_TDP4
 #   or_next_if_better
 # endmatch
 #
-# match $__XILINX_RAMB36_SDP4
-#   min efficiency 20
+# match $__XILINX_RAMB18_TDP2
 #   or_next_if_better
 # endmatch
 #
-# match $__XILINX_RAMB36_SDP2
-#   min efficiency 20
-#   or_next_if_better
-# endmatch
-#
-# match $__XILINX_RAMB36_SDP1
-#   min efficiency 20
+# match $__XILINX_RAMB18_TDP1
 # endmatch
 
diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index f98625bfa..a5d2b59cc 100644
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -79,3 +79,155 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.WEBWE(B1EN)
 	);
 endmodule
+
+// ------------------------------------------------------------------------
+
+module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter TRANSP2 = 1;
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+
+	input CLK2;
+	input CLK3;
+
+	input [8:0] A1ADDR;
+	output [35:0] A1DATA;
+
+	input [8:0] B1ADDR;
+	input [35:0] B1DATA;
+	input [3:0] B1EN;
+
+	wire [15:0] A1ADDR_16 = {A1ADDR, 5'b0};
+	wire [15:0] B1ADDR_16 = {B1ADDR, 5'b0};
+
+	wire [3:0] DIP, DOP;
+	wire [31:0] DI, DO;
+
+	wire [35:0] A1DATA_BUF;
+	reg [35:0] B1DATA_Q;
+	reg [3:0] transparent_cycle;
+
+	wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
+
+	generate if (CLKPOL2)
+		always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
+	else
+		always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
+	endgenerate
+
+	assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
+	assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
+	assign A1DATA[26:18] = transparent_cycle[2] ? B1DATA_Q[26:18] : A1DATA_BUF[26:18];
+	assign A1DATA[35:27] = transparent_cycle[3] ? B1DATA_Q[35:27] : A1DATA_BUF[35:27];
+
+	assign A1DATA_BUF = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
+
+	RAMB18E1 #(
+		.RAM_MODE("SDP"),
+		.READ_WIDTH_A(36),
+		.WRITE_WIDTH_B(36),
+		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
+		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+	) _TECHMAP_REPLACE_ (
+		.DOBDO(DO[31:16]),
+		.DOADO(DO[15:0]),
+		.DOPBDOP(DOP[3:2]),
+		.DOPADOP(DOP[1:0]),
+		.DIBDI(DI[31:16]),
+		.DIADI(DI[15:0]),
+		.DIPBDIP(DIP[3:2]),
+		.DIPADIP(DIP[1:0]),
+
+		.ADDRARDADDR(A1ADDR_16),
+		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.ENARDEN(|1),
+		.REGCEAREGCE(|1),
+		.RSTRAMARSTRAM(|0),
+		.RSTREGARSTREG(|0),
+		.WEA(4'b0),
+
+		.ADDRBWRADDR(B1ADDR_16),
+		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.ENBWREN(|1),
+		.REGCEB(|0),
+		.RSTRAMB(|0),
+		.RSTREGB(|0),
+		.WEBWE(B1EN)
+	);
+endmodule
+
+// ------------------------------------------------------------------------
+
+module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter TRANSP2 = 1;
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+
+	input CLK2;
+	input CLK3;
+
+	input [8:0] A1ADDR;
+	output [17:0] A1DATA;
+
+	input [8:0] B1ADDR;
+	input [17:0] B1DATA;
+	input [1:0] B1EN;
+
+	wire [13:0] A1ADDR_14 = {A1ADDR, 4'b0};
+	wire [13:0] B1ADDR_14 = {B1ADDR, 4'b0};
+
+	wire [1:0] DIP, DOP;
+	wire [15:0] DI, DO;
+
+	wire [17:0] A1DATA_BUF;
+	reg [17:0] B1DATA_Q;
+	reg [1:0] transparent_cycle;
+
+	wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
+
+	generate if (CLKPOL2)
+		always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
+	else
+		always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
+	endgenerate
+
+	assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
+	assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
+
+	assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+	assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
+
+	RAMB18E1 #(
+		.RAM_MODE("TDP"),
+		.READ_WIDTH_A(18),
+		.READ_WIDTH_B(18),
+		.WRITE_WIDTH_A(18),
+		.WRITE_WIDTH_B(18),
+		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
+		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+	) _TECHMAP_REPLACE_ (
+		.DIADI(16'b0),
+		.DIPADIP(2'b0),
+		.DOADO(DO[15:0]),
+		.DOPADOP(DOP[1:0]),
+		.ADDRARDADDR(A1ADDR_14),
+		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.ENARDEN(|1),
+		.REGCEAREGCE(|1),
+		.RSTRAMARSTRAM(|0),
+		.RSTREGARSTREG(|0),
+		.WEA(2'b0),
+
+		.DIBDI(DI[15:0]),
+		.DIPBDIP(DIP[1:0]),
+		.ADDRBWRADDR(B1ADDR_14),
+		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.ENBWREN(|1),
+		.REGCEB(|0),
+		.RSTRAMB(|0),
+		.RSTREGB(|0),
+		.WEBWE({2'b00, B1EN})
+	);
+endmodule
+
diff --git a/techlibs/xilinx/tests/bram1.sh b/techlibs/xilinx/tests/bram1.sh
index f233be9fa..15c4034aa 100644
--- a/techlibs/xilinx/tests/bram1.sh
+++ b/techlibs/xilinx/tests/bram1.sh
@@ -1,5 +1,7 @@
 #!/bin/bash
 
+set -e
+
 use_xsim=false
 unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
 
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v
index c14cf6e30..dbefdb6e8 100644
--- a/techlibs/xilinx/tests/bram1_tb.v
+++ b/techlibs/xilinx/tests/bram1_tb.v
@@ -70,7 +70,7 @@ module bram1_tb #(
 					expected_rd[j] = RD_DATA[j];
 			end
 
-			$display("#OUT# | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
+			$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
 			if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end
 		end
 	end