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docs: Updating todos

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Krystine Sherwin 2023-09-19 11:21:15 +12:00
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docs/source/getting_started/scripting_intro.rst
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Scripting in Yosys Scripting in Yosys
------------------ ------------------
.. todo:: copypaste .. todo:: check logical consistency
Yosys reads and processes commands from synthesis scripts, command line Yosys reads and processes commands from synthesis scripts, command line
arguments and an interactive command prompt. Yosys commands consist of a command arguments and an interactive command prompt. Yosys commands consist of a command

2
docs/source/getting_started/typical_phases.rst
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Typical phases of a synthesis flow Typical phases of a synthesis flow
---------------------------------- ----------------------------------
.. todo:: copypaste .. todo:: expand text
- Reading and elaborating the design - Reading and elaborating the design
- Higher-level synthesis and optimization - Higher-level synthesis and optimization

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docs/source/introduction.rst
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@ -116,6 +116,8 @@ Benefits of open source HDL synthesis
The extended Yosys universe The extended Yosys universe
--------------------------- ---------------------------
.. todo:: links and add SCY
In no particular order: In no particular order:
- SBY for formal verification - SBY for formal verification
@ -125,7 +127,7 @@ In no particular order:
History of Yosys History of Yosys
---------------- ----------------
.. todo:: copypaste .. todo:: make less academic
A Hardware Description Language (HDL) is a computer language used to describe A Hardware Description Language (HDL) is a computer language used to describe
circuits. A HDL synthesis tool is a computer program that takes a formal circuits. A HDL synthesis tool is a computer program that takes a formal

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docs/source/test_suites.rst
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@ -4,7 +4,7 @@ Test suites
.. note:: Potentially significantly out of date information .. note:: Potentially significantly out of date information
last updated circa 2015 last updated circa 2015
.. todo:: copypaste .. todo:: update content from 2015
Continuously checking the correctness of Yosys and making sure that new features Continuously checking the correctness of Yosys and making sure that new features
do not break old ones is a high priority in Yosys. Two external test suites do not break old ones is a high priority in Yosys. Two external test suites

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docs/source/using_yosys/more_scripting/opt_passes.rst
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Optimization passes Optimization passes
=================== ===================
.. todo:: copypaste .. todo:: check text context, also check the optimization passes still do what they say
Yosys employs a number of optimizations to generate better and cleaner results. Yosys employs a number of optimizations to generate better and cleaner results.
This chapter outlines these optimizations. This chapter outlines these optimizations.

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docs/source/using_yosys/more_scripting/selections.rst
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Selections Selections
---------- ----------
.. todo:: copypaste .. todo:: expand on text
Most Yosys commands make use of the "selection framework" of Yosys. It can be Most Yosys commands make use of the "selection framework" of Yosys. It can be
used to apply commands only to part of the design. For example: used to apply commands only to part of the design. For example:

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docs/source/using_yosys/yosys_flows.rst
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@ -4,7 +4,7 @@ Flows, command types, and order
Command order Command order
------------- -------------
.. todo:: copypaste .. todo:: check text is coherent
Intro to coarse-grain synthesis Intro to coarse-grain synthesis
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -39,7 +39,7 @@ The extract pass
subcircuit with an instance of the module from the map file. subcircuit with an instance of the module from the map file.
- In a way the :cmd:ref:`extract` pass is the inverse of the techmap pass. - In a way the :cmd:ref:`extract` pass is the inverse of the techmap pass.
.. todo:: copypaste .. todo:: add/expand supporting text
.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.* .. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.*
:class: width-helper :class: width-helper
@ -121,7 +121,7 @@ Preconditioning: ``macc_xilinx_swap_map.v``
Make sure ``A`` is the smaller port on all multipliers Make sure ``A`` is the smaller port on all multipliers
.. todo:: copypaste .. todo:: add/expand supporting text
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v .. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
:language: verilog :language: verilog
@ -277,7 +277,7 @@ Unwrap in ``test2``:
Symbolic model checking Symbolic model checking
----------------------- -----------------------
.. todo:: copypaste .. todo:: check text context
.. note:: .. note::
@ -299,6 +299,8 @@ Checking.
Checking techmap Checking techmap
~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~
.. todo:: add/expand supporting text
Remember the following example from :doc:`/getting_started/typical_phases`? Remember the following example from :doc:`/getting_started/typical_phases`?
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v .. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
@ -351,6 +353,8 @@ slave keeps ``tready`` asserted all the time. (Something a test bench might do.)
Symbolic Model Checking can be used to expose the bug and find a sequence of Symbolic Model Checking can be used to expose the bug and find a sequence of
values for ``tready`` that yield the incorrect behavior. values for ``tready`` that yield the incorrect behavior.
.. todo:: add/expand supporting text
.. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_master.v .. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_master.v
:language: verilog :language: verilog
:caption: ``docs/resources/PRESENTATION_ExOth/axis_master.v`` :caption: ``docs/resources/PRESENTATION_ExOth/axis_master.v``

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docs/source/yosys_internals/extensions.rst
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Writing extensions Writing extensions
================== ==================
.. todo:: copypaste .. todo:: check text is coherent
This chapter contains some bits and pieces of information about programming This chapter contains some bits and pieces of information about programming
yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack. yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
@ -82,11 +82,11 @@ command has been executed can be helpful. The
:doc:`/using_yosys/more_scripting/selections` document has more information on :doc:`/using_yosys/more_scripting/selections` document has more information on
using these commands. using these commands.
.. todo:: copypaste
Creating modules from scratch Creating modules from scratch
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. todo:: add/expand supporting text
Let's create the following module using the RTLIL API: Let's create the following module using the RTLIL API:
.. code:: Verilog .. code:: Verilog

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docs/source/yosys_internals/flow/control_and_data.rst
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Control and data flow Control and data flow
===================== =====================
.. todo:: copypaste .. todo:: less academic
The data- and control-flow of a typical synthesis tool is very similar to the The data- and control-flow of a typical synthesis tool is very similar to the
data- and control-flow of a typical compiler: different subsystems are called in data- and control-flow of a typical compiler: different subsystems are called in

2
docs/source/yosys_internals/flow/overview.rst
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Flow overview Flow overview
============= =============
.. todo:: copypaste .. todo:: less academic
:numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within :numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within
Yosys. Rectangles in the figure represent program modules and ellipses internal Yosys. Rectangles in the figure represent program modules and ellipses internal

4
docs/source/yosys_internals/formats/cell_library.rst
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@ -1,13 +1,13 @@
.. role:: verilog(code) .. role:: verilog(code)
:language: Verilog :language: Verilog
.. todo:: copypaste
.. _chapter:celllib: .. _chapter:celllib:
Internal cell library Internal cell library
===================== =====================
.. todo:: less academic, also check formatting consistency
Most of the passes in Yosys operate on netlists, i.e. they only care about the Most of the passes in Yosys operate on netlists, i.e. they only care about the
RTLIL::Wire and RTLIL::Cell objects in an RTLIL::Module. This chapter discusses RTLIL::Wire and RTLIL::Cell objects in an RTLIL::Module. This chapter discusses
the cell types used by Yosys to represent a behavioural design internally. the cell types used by Yosys to represent a behavioural design internally.

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docs/source/yosys_internals/index.rst
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Yosys internals Yosys internals
=============== ===============
.. todo:: copypaste .. todo:: less academic
Yosys is an extensible open source hardware synthesis tool. It is aimed at Yosys is an extensible open source hardware synthesis tool. It is aimed at
designers who are looking for an easily accessible, universal, and designers who are looking for an easily accessible, universal, and

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docs/source/yosys_internals/techmap.rst
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.. _chapter:techmap: .. _chapter:techmap:
.. todo:: copypaste .. todo:: less academic, check text is coherent
Technology mapping Technology mapping
================== ==================
@ -109,8 +109,6 @@ sensitive information from the Liberty file.
Techmap by example Techmap by example
------------------ ------------------
.. todo:: copypaste
As a quick recap, the :cmd:ref:`techmap` command replaces cells in the design As a quick recap, the :cmd:ref:`techmap` command replaces cells in the design
with implementations given as Verilog code (called "map files"). It can replace with implementations given as Verilog code (called "map files"). It can replace
Yosys' internal cell types (such as ``$or``) as well as user-defined cell types. Yosys' internal cell types (such as ``$or``) as well as user-defined cell types.
@ -125,6 +123,8 @@ Yosys' internal cell types (such as ``$or``) as well as user-defined cell types.
Mapping OR3X1 Mapping OR3X1
~~~~~~~~~~~~~ ~~~~~~~~~~~~~
.. todo:: add/expand supporting text
.. note:: .. note::
This is a simple example for demonstration only. Techmap shouldn't be used This is a simple example for demonstration only. Techmap shouldn't be used