docs: Updating todos

docs/source/getting_started/scripting_intro.rst

@@ -1,7 +1,7 @@
 Scripting in Yosys
 ------------------
 
-.. todo:: copypaste
+.. todo:: check logical consistency
 
 Yosys reads and processes commands from synthesis scripts, command line
 arguments and an interactive command prompt. Yosys commands consist of a command

docs/source/getting_started/typical_phases.rst

@@ -1,7 +1,7 @@
 Typical phases of a synthesis flow
 ----------------------------------
 
-.. todo:: copypaste
+.. todo:: expand text
 
 - Reading and elaborating the design
 - Higher-level synthesis and optimization

docs/source/introduction.rst

@@ -116,6 +116,8 @@ Benefits of open source HDL synthesis
 The extended Yosys universe
 ---------------------------
 
+.. todo:: links and add SCY
+
 In no particular order:
 
 - SBY for formal verification
@@ -125,7 +127,7 @@ In no particular order:
 History of Yosys
 ----------------
 
-.. todo:: copypaste
+.. todo:: make less academic
 
 A Hardware Description Language (HDL) is a computer language used to describe
 circuits. A HDL synthesis tool is a computer program that takes a formal

docs/source/test_suites.rst

@@ -4,7 +4,7 @@ Test suites
 .. note:: Potentially significantly out of date information
     last updated circa 2015
 
-.. todo:: copypaste
+.. todo:: update content from 2015
 
 Continuously checking the correctness of Yosys and making sure that new features
 do not break old ones is a high priority in Yosys.  Two external test suites

docs/source/using_yosys/more_scripting/opt_passes.rst

@@ -3,7 +3,7 @@
 Optimization passes
 ===================
 
-.. todo:: copypaste
+.. todo:: check text context, also check the optimization passes still do what they say
 
 Yosys employs a number of optimizations to generate better and cleaner results.
 This chapter outlines these optimizations.

docs/source/using_yosys/more_scripting/selections.rst

@@ -1,7 +1,7 @@
 Selections
 ----------
 
-.. todo:: copypaste
+.. todo:: expand on text
 
 Most Yosys commands make use of the "selection framework" of Yosys. It can be
 used to apply commands only to part of the design. For example:

docs/source/using_yosys/yosys_flows.rst

@@ -4,7 +4,7 @@ Flows, command types, and order
 Command order
 -------------
 
-.. todo:: copypaste
+.. todo:: check text is coherent
 
 Intro to coarse-grain synthesis
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -39,7 +39,7 @@ The extract pass
   subcircuit with an instance of the module from the map file.
 - In a way the :cmd:ref:`extract` pass is the inverse of the techmap pass.
 
-.. todo:: copypaste
+.. todo:: add/expand supporting text
 
 .. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.*
     :class: width-helper
@@ -121,7 +121,7 @@ Preconditioning: ``macc_xilinx_swap_map.v``
 
 Make sure ``A`` is the smaller port on all multipliers
 
-.. todo:: copypaste
+.. todo:: add/expand supporting text
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
    :language: verilog
@@ -277,7 +277,7 @@ Unwrap in ``test2``:
 Symbolic model checking
 -----------------------
 
-.. todo:: copypaste
+.. todo:: check text context
 
 .. note:: 
     
@@ -299,6 +299,8 @@ Checking.
 Checking techmap
 ~~~~~~~~~~~~~~~~
 
+.. todo:: add/expand supporting text
+
 Remember the following example from :doc:`/getting_started/typical_phases`?
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
@@ -351,6 +353,8 @@ slave keeps ``tready`` asserted all the time. (Something a test bench might do.)
 Symbolic Model Checking can be used to expose the bug and find a sequence of
 values for ``tready`` that yield the incorrect behavior.
 
+.. todo:: add/expand supporting text
+
 .. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_master.v
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExOth/axis_master.v``

docs/source/yosys_internals/extensions.rst

@@ -3,7 +3,7 @@
 Writing extensions
 ==================
 
-.. todo:: copypaste
+.. todo:: check text is coherent
 
 This chapter contains some bits and pieces of information about programming
 yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
@@ -82,11 +82,11 @@ command has been executed can be helpful.  The
 :doc:`/using_yosys/more_scripting/selections` document has more information on
 using these commands.
 
-.. todo:: copypaste
-
 Creating modules from scratch
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+.. todo:: add/expand supporting text
+
 Let's create the following module using the RTLIL API:
 
 .. code:: Verilog

docs/source/yosys_internals/flow/control_and_data.rst

@@ -1,7 +1,7 @@
 Control and data flow
 =====================
 
-.. todo:: copypaste
+.. todo:: less academic
 
 The data- and control-flow of a typical synthesis tool is very similar to the
 data- and control-flow of a typical compiler: different subsystems are called in

docs/source/yosys_internals/flow/overview.rst

@@ -1,7 +1,7 @@
 Flow overview
 =============
 
-.. todo:: copypaste
+.. todo:: less academic
 
 :numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within
 Yosys. Rectangles in the figure represent program modules and ellipses internal

docs/source/yosys_internals/formats/cell_library.rst

@@ -1,13 +1,13 @@
 .. role:: verilog(code)
 	:language: Verilog
 
-.. todo:: copypaste
-
 .. _chapter:celllib:
 
 Internal cell library
 =====================
 
+.. todo:: less academic, also check formatting consistency
+
 Most of the passes in Yosys operate on netlists, i.e. they only care about the
 RTLIL::Wire and RTLIL::Cell objects in an RTLIL::Module. This chapter discusses
 the cell types used by Yosys to represent a behavioural design internally.

docs/source/yosys_internals/index.rst

@@ -3,7 +3,7 @@
 Yosys internals
 ===============
 
-.. todo:: copypaste
+.. todo:: less academic
 
 Yosys is an extensible open source hardware synthesis tool. It is aimed at
 designers who are looking for an easily accessible, universal, and

docs/source/yosys_internals/techmap.rst

@@ -1,6 +1,6 @@
 .. _chapter:techmap:
 
-.. todo:: copypaste
+.. todo:: less academic, check text is coherent
 
 Technology mapping 
 ==================
@@ -109,8 +109,6 @@ sensitive information from the Liberty file.
 Techmap by example
 ------------------
 
-.. todo:: copypaste
-
 As a quick recap, the :cmd:ref:`techmap` command replaces cells in the design
 with implementations given as Verilog code (called "map files"). It can replace
 Yosys' internal cell types (such as ``$or``) as well as user-defined cell types.
@@ -125,6 +123,8 @@ Yosys' internal cell types (such as ``$or``) as well as user-defined cell types.
 Mapping OR3X1
 ~~~~~~~~~~~~~
 
+.. todo:: add/expand supporting text
+
 .. note::
 
     This is a simple example for demonstration only.  Techmap shouldn't be used