riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Refactor for one "abc_carry" attribute on module

This commit is contained in:
Eddie Hung 2019-06-27 16:07:14 -07:00
parent 550760cc72
commit 9398921af1
5 changed files with 84 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
backends/aiger/xaiger.cc
View File

@ -284,8 +284,6 @@ struct XAigerWriter
for (auto user_cell : it.second) for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell); toposort.edge(driver_cell, user_cell);
pool<RTLIL::Module*> abc_carry_modules;
#if 0 #if 0
toposort.analyze_loops = true; toposort.analyze_loops = true;
#endif #endif
@ -303,54 +301,54 @@ struct XAigerWriter
#endif #endif
log_assert(no_loops); log_assert(no_loops);
pool<IdString> seen_boxes;
for (auto cell_name : toposort.sorted) { for (auto cell_name : toposort.sorted) {
RTLIL::Cell *cell = module->cell(cell_name); RTLIL::Cell *cell = module->cell(cell_name);
log_assert(cell);
RTLIL::Module* box_module = module->design->module(cell->type); RTLIL::Module* box_module = module->design->module(cell->type);
if (!box_module || !box_module->attributes.count("\\abc_box_id")) if (!box_module || !box_module->attributes.count("\\abc_box_id"))
continue; continue;
if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { if (seen_boxes.insert(cell->type).second) {
RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; auto it = box_module->attributes.find("\\abc_carry");
auto &ports = box_module->ports; if (it != box_module->attributes.end()) {
for (auto it = ports.begin(); it != ports.end(); ) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
RTLIL::Wire* w = box_module->wire(*it); auto carry_in_out = it->second.decode_string();
log_assert(w); auto pos = carry_in_out.find(',');
if (w->port_input && w->attributes.count("\\abc_carry_in")) { if (pos == std::string::npos)
if (carry_in) log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
log_error("More than one port with attribute 'abc_carry_in' found in module '%s'\n", log_id(box_module)); auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
carry_in = w; carry_in = box_module->wire(carry_in_name);
it = ports.erase(it); if (!carry_in || !carry_in->port_input)
continue; log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
}
if (w->port_output && w->attributes.count("\\abc_carry_out")) {
if (carry_out)
log_error("More than one port with attribute 'abc_carry_out' found in module '%s'\n", log_id(box_module));
carry_out = w;
it = ports.erase(it);
continue;
}
++it;
}
if (!carry_in) auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
log_error("Port with attribute 'abc_carry_in' not found in module '%s'\n", log_id(box_module)); carry_out = box_module->wire(carry_out_name);
if (!carry_out) if (!carry_out || !carry_out->port_output)
log_error("Port with attribute 'abc_carry_out' not found in module '%s'\n", log_id(box_module)); log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
for (const auto port_name : ports) { auto &ports = box_module->ports;
RTLIL::Wire* w = box_module->wire(port_name); for (auto jt = ports.begin(); jt != ports.end(); ) {
log_assert(w); RTLIL::Wire* w = box_module->wire(*jt);
if (w->port_id > carry_in->port_id) log_assert(w);
--w->port_id; if (w == carry_in || w == carry_out) {
if (w->port_id > carry_out->port_id) jt = ports.erase(jt);
--w->port_id; continue;
log_assert(w->port_input || w->port_output); }
log_assert(ports[w->port_id-1] == w->name); if (w->port_id > carry_in->port_id)
--w->port_id;
if (w->port_id > carry_out->port_id)
--w->port_id;
log_assert(w->port_input || w->port_output);
log_assert(ports[w->port_id-1] == w->name);
++jt;
}
ports.push_back(carry_in->name);
carry_in->port_id = ports.size();
ports.push_back(carry_out->name);
carry_out->port_id = ports.size();
} }
ports.push_back(carry_in->name);
carry_in->port_id = ports.size();
ports.push_back(carry_out->name);
carry_out->port_id = ports.size();
} }
// Fully pad all unused input connections of this box cell with S0 // Fully pad all unused input connections of this box cell with S0

70
frontends/aiger/aigerparse.cc
View File

@ -732,44 +732,50 @@ void AigerReader::parse_aiger_binary()
void AigerReader::post_process() void AigerReader::post_process()
{ {
pool<RTLIL::Module*> abc_carry_modules; pool<IdString> seen_boxes;
unsigned ci_count = 0, co_count = 0; unsigned ci_count = 0, co_count = 0;
for (auto cell : boxes) { for (auto cell : boxes) {
RTLIL::Module* box_module = design->module(cell->type); RTLIL::Module* box_module = design->module(cell->type);
log_assert(box_module); log_assert(box_module);
if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { if (seen_boxes.insert(cell->type).second) {
RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; auto it = box_module->attributes.find("\\abc_carry");
RTLIL::Wire* last_in = nullptr, *last_out = nullptr; if (it != box_module->attributes.end()) {
for (const auto &port_name : box_module->ports) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
RTLIL::Wire* w = box_module->wire(port_name); auto carry_in_out = it->second.decode_string();
log_assert(w); auto pos = carry_in_out.find(',');
if (w->port_input) { if (pos == std::string::npos)
if (w->attributes.count("\\abc_carry_in")) { log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
log_assert(!carry_in); auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
carry_in = w; carry_in = box_module->wire(carry_in_name);
} if (!carry_in || !carry_in->port_input)
log_assert(!last_in || last_in->port_id < w->port_id); log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
last_in = w;
}
if (w->port_output) {
if (w->attributes.count("\\abc_carry_out")) {
log_assert(!carry_out);
carry_out = w;
}
log_assert(!last_out || last_out->port_id < w->port_id);
last_out = w;
}
}
if (carry_in != last_in) { auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
std::swap(box_module->ports[carry_in->port_id], box_module->ports[last_in->port_id]); carry_out = box_module->wire(carry_out_name);
std::swap(carry_in->port_id, last_in->port_id); if (!carry_out || !carry_out->port_output)
} log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
if (carry_out != last_out) {
log_assert(last_out); auto &ports = box_module->ports;
std::swap(box_module->ports[carry_out->port_id], box_module->ports[last_out->port_id]); for (auto jt = ports.begin(); jt != ports.end(); ) {
std::swap(carry_out->port_id, last_out->port_id); RTLIL::Wire* w = box_module->wire(*jt);
log_assert(w);
if (w == carry_in || w == carry_out) {
jt = ports.erase(jt);
continue;
}
if (w->port_id > carry_in->port_id)
--w->port_id;
if (w->port_id > carry_out->port_id)
--w->port_id;
log_assert(w->port_input || w->port_output);
log_assert(ports[w->port_id-1] == w->name);
++jt;
}
ports.push_back(carry_in->name);
carry_in->port_id = ports.size();
ports.push_back(carry_out->name);
carry_out->port_id = ports.size();
} }
} }

8
techlibs/ecp5/cells_sim.v
View File

@ -15,11 +15,9 @@ module L6MUX21 (input D0, D1, SD, output Z);
endmodule endmodule
// --------------------------------------- // ---------------------------------------
(* abc_box_id=1, abc_carry, lib_whitebox *) (* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
module CCU2C((* abc_carry_in *) input CIN, module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
input A0, B0, C0, D0, A1, B1, C1, D1, output S0, S1, COUT);
output S0, S1,
(* abc_carry_out *) output COUT);
parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000; parameter [15:0] INIT1 = 16'h0000;

4
techlibs/ice40/cells_sim.v
View File

@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0]; assign O = I0 ? s1[1] : s1[0];
endmodule endmodule
(* abc_box_id = 1, abc_carry, lib_whitebox *) (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI); module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI); assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule endmodule

4
techlibs/xilinx/cells_sim.v
View File

@ -173,8 +173,8 @@ module XORCY(output O, input CI, LI);
assign O = CI ^ LI; assign O = CI ^ LI;
endmodule endmodule
(* abc_box_id = 3, abc_carry, lib_whitebox *) (* abc_box_id = 3, abc_carry="CI,CO", lib_whitebox *)
module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S); module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
assign O = S ^ {CO[2:0], CI | CYINIT}; assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0]; assign CO[0] = S[0] ? CI | CYINIT : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1]; assign CO[1] = S[1] ? CO[0] : DI[1];