mirror of https://github.com/YosysHQ/yosys.git
add lut tests
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*.log
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/run-test.mk
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read_verilog ../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 9 t:NX_LUT
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select -assert-none t:NX_LUT %% t:* %D
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#!/usr/bin/env bash
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set -eu
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source ../../gen-tests-makefile.sh
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run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
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