riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cxxrtl: run edge detectors only once in eval(). 

As a result, Minerva SRAM SoC runs ~15% faster.
This commit is contained in:
whitequark 2020-04-22 12:45:19 +00:00
parent 1d5b6ac253
commit 93288b8eae
1 changed files with 22 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
backends/cxxrtl/cxxrtl.cc
View File

@ -1020,7 +1020,7 @@ struct CxxrtlWorker {
RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0]; RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit); clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
<< mangle(clk_bit) << "()) {\n"; << mangle(clk_bit) << ") {\n";
inc_indent(); inc_indent();
if (cell->type == ID($dffe)) { if (cell->type == ID($dffe)) {
f << indent << "if ("; f << indent << "if (";
@ -1097,7 +1097,7 @@ struct CxxrtlWorker {
RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0]; RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit); clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
<< mangle(clk_bit) << "()) {\n"; << mangle(clk_bit) << ") {\n";
inc_indent(); inc_indent();
} }
RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()]; RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
@ -1365,16 +1365,16 @@ struct CxxrtlWorker {
switch (sync->type) { switch (sync->type) {
case RTLIL::STp: case RTLIL::STp:
log_assert(sync_bit.wire != nullptr); log_assert(sync_bit.wire != nullptr);
events.insert("posedge_" + mangle(sync_bit) + "()"); events.insert("posedge_" + mangle(sync_bit));
break; break;
case RTLIL::STn: case RTLIL::STn:
log_assert(sync_bit.wire != nullptr); log_assert(sync_bit.wire != nullptr);
events.insert("negedge_" + mangle(sync_bit) + "()"); events.insert("negedge_" + mangle(sync_bit));
break; break;
case RTLIL::STe: case RTLIL::STe:
log_assert(sync_bit.wire != nullptr); log_assert(sync_bit.wire != nullptr);
events.insert("posedge_" + mangle(sync_bit) + "()"); events.insert("posedge_" + mangle(sync_bit));
events.insert("negedge_" + mangle(sync_bit) + "()"); events.insert("negedge_" + mangle(sync_bit));
break; break;
case RTLIL::STa: case RTLIL::STa:
@ -1522,6 +1522,22 @@ struct CxxrtlWorker {
inc_indent(); inc_indent();
f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n"; f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
if (!module->get_bool_attribute(ID(cxxrtl.blackbox))) { if (!module->get_bool_attribute(ID(cxxrtl.blackbox))) {
for (auto wire : module->wires()) {
if (edge_wires[wire]) {
for (auto edge_type : edge_types) {
if (edge_type.first.wire == wire) {
if (edge_type.second != RTLIL::STn) {
f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
f << "this->posedge_" << mangle(edge_type.first) << "();\n";
}
if (edge_type.second != RTLIL::STp) {
f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
f << "this->negedge_" << mangle(edge_type.first) << "();\n";
}
}
}
}
}
for (auto wire : module->wires()) for (auto wire : module->wires())
dump_wire(wire, /*is_local_context=*/true); dump_wire(wire, /*is_local_context=*/true);
for (auto node : schedule[module]) { for (auto node : schedule[module]) {