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Fix files with CRLF line endings

This commit is contained in:
Claire Xenia Wolf 2021-06-09 12:16:33 +02:00
parent 72787f52fc
commit 92e705cb51
5 changed files with 422 additions and 422 deletions
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636
techlibs/common/mul2dsp.v
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@ -1,318 +1,318 @@
/* /*
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com> * 2019 Eddie Hung <eddie@fpgeh.com>
* 2019 David Shah <dave@ds0.me> * 2019 gatecat <gatecat@ds0.me>
* *
* Permission to use, copy, modify, and/or distribute this software for any * Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above * purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies. * copyright notice and this permission notice appear in all copies.
* *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
* *
* --- * ---
* *
* Tech-mapping rules for decomposing arbitrarily-sized $mul cells * Tech-mapping rules for decomposing arbitrarily-sized $mul cells
* into an equivalent collection of smaller `DSP_NAME cells (with the * into an equivalent collection of smaller `DSP_NAME cells (with the
* same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
* to $shl and $add cells. * to $shl and $add cells.
* *
*/ */
`ifndef DSP_A_MAXWIDTH `ifndef DSP_A_MAXWIDTH
$fatal(1, "Macro DSP_A_MAXWIDTH must be defined"); $fatal(1, "Macro DSP_A_MAXWIDTH must be defined");
`endif `endif
`ifndef DSP_B_MAXWIDTH `ifndef DSP_B_MAXWIDTH
$fatal(1, "Macro DSP_B_MAXWIDTH must be defined"); $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
`endif `endif
`ifndef DSP_B_MAXWIDTH `ifndef DSP_B_MAXWIDTH
$fatal(1, "Macro DSP_B_MAXWIDTH must be defined"); $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
`endif `endif
`ifndef DSP_A_MAXWIDTH_PARTIAL `ifndef DSP_A_MAXWIDTH_PARTIAL
`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH `define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH
`endif `endif
`ifndef DSP_B_MAXWIDTH_PARTIAL `ifndef DSP_B_MAXWIDTH_PARTIAL
`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH `define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH
`endif `endif
`ifndef DSP_NAME `ifndef DSP_NAME
$fatal(1, "Macro DSP_NAME must be defined"); $fatal(1, "Macro DSP_NAME must be defined");
`endif `endif
`define MAX(a,b) (a > b ? a : b) `define MAX(a,b) (a > b ? a : b)
`define MIN(a,b) (a < b ? a : b) `define MIN(a,b) (a < b ? a : b)
(* techmap_celltype = "$mul $__mul" *) (* techmap_celltype = "$mul $__mul" *)
module _80_mul (A, B, Y); module _80_mul (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;
parameter A_WIDTH = 1; parameter A_WIDTH = 1;
parameter B_WIDTH = 1; parameter B_WIDTH = 1;
parameter Y_WIDTH = 1; parameter Y_WIDTH = 1;
(* force_downto *) (* force_downto *)
input [A_WIDTH-1:0] A; input [A_WIDTH-1:0] A;
(* force_downto *) (* force_downto *)
input [B_WIDTH-1:0] B; input [B_WIDTH-1:0] B;
(* force_downto *) (* force_downto *)
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = ""; parameter _TECHMAP_CELLTYPE_ = "";
generate generate
if (0) begin end if (0) begin end
`ifdef DSP_A_MINWIDTH `ifdef DSP_A_MINWIDTH
else if (A_WIDTH < `DSP_A_MINWIDTH) else if (A_WIDTH < `DSP_A_MINWIDTH)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
`endif `endif
`ifdef DSP_B_MINWIDTH `ifdef DSP_B_MINWIDTH
else if (B_WIDTH < `DSP_B_MINWIDTH) else if (B_WIDTH < `DSP_B_MINWIDTH)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
`endif `endif
`ifdef DSP_Y_MINWIDTH `ifdef DSP_Y_MINWIDTH
else if (Y_WIDTH < `DSP_Y_MINWIDTH) else if (Y_WIDTH < `DSP_Y_MINWIDTH)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
`endif `endif
`ifdef DSP_SIGNEDONLY `ifdef DSP_SIGNEDONLY
else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED) else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED)
\$mul #( \$mul #(
.A_SIGNED(1), .A_SIGNED(1),
.B_SIGNED(1), .B_SIGNED(1),
.A_WIDTH(A_WIDTH + 1), .A_WIDTH(A_WIDTH + 1),
.B_WIDTH(B_WIDTH + 1), .B_WIDTH(B_WIDTH + 1),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A({1'b0, A}), .A({1'b0, A}),
.B({1'b0, B}), .B({1'b0, B}),
.Y(Y) .Y(Y)
); );
`endif `endif
else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH) else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
\$mul #( \$mul #(
.A_SIGNED(B_SIGNED), .A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED), .B_SIGNED(A_SIGNED),
.A_WIDTH(B_WIDTH), .A_WIDTH(B_WIDTH),
.B_WIDTH(A_WIDTH), .B_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A(B), .A(B),
.B(A), .B(A),
.Y(Y) .Y(Y)
); );
else begin else begin
wire [1023:0] _TECHMAP_DO_ = "proc; clean"; wire [1023:0] _TECHMAP_DO_ = "proc; clean";
`ifdef DSP_SIGNEDONLY `ifdef DSP_SIGNEDONLY
localparam sign_headroom = 1; localparam sign_headroom = 1;
`else `else
localparam sign_headroom = 0; localparam sign_headroom = 0;
`endif `endif
genvar i; genvar i;
if (A_WIDTH > `DSP_A_MAXWIDTH) begin if (A_WIDTH > `DSP_A_MAXWIDTH) begin
localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom); localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom); localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH; localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
if (A_SIGNED && B_SIGNED) begin : blk if (A_SIGNED && B_SIGNED) begin : blk
(* force_downto *) (* force_downto *)
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *) (* force_downto *)
wire signed [last_Y_WIDTH-1:0] last_partial; wire signed [last_Y_WIDTH-1:0] last_partial;
(* force_downto *) (* force_downto *)
wire signed [Y_WIDTH-1:0] partial_sum [n:0]; wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end end
else begin : blk else begin : blk
(* force_downto *) (* force_downto *)
wire [partial_Y_WIDTH-1:0] partial [n-1:0]; wire [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *) (* force_downto *)
wire [last_Y_WIDTH-1:0] last_partial; wire [last_Y_WIDTH-1:0] last_partial;
(* force_downto *) (* force_downto *)
wire [Y_WIDTH-1:0] partial_sum [n:0]; wire [Y_WIDTH-1:0] partial_sum [n:0];
end end
for (i = 0; i < n; i=i+1) begin:sliceA for (i = 0; i < n; i=i+1) begin:sliceA
\$__mul #( \$__mul #(
.A_SIGNED(sign_headroom), .A_SIGNED(sign_headroom),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(partial_Y_WIDTH) .Y_WIDTH(partial_Y_WIDTH)
) mul ( ) mul (
.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}), .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
.B(B), .B(B),
.Y(blk.partial[i]) .Y(blk.partial[i])
); );
// TODO: Currently a 'cascade' approach to summing the partial // TODO: Currently a 'cascade' approach to summing the partial
// products is taken here, but a more efficient 'binary // products is taken here, but a more efficient 'binary
// reduction' approach also exists... // reduction' approach also exists...
if (i == 0) if (i == 0)
assign blk.partial_sum[i] = blk.partial[i]; assign blk.partial_sum[i] = blk.partial[i];
else else
assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1]; assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
end end
\$__mul #( \$__mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(last_A_WIDTH), .A_WIDTH(last_A_WIDTH),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(last_Y_WIDTH) .Y_WIDTH(last_Y_WIDTH)
) sliceA.last ( ) sliceA.last (
.A(A[A_WIDTH-1 -: last_A_WIDTH]), .A(A[A_WIDTH-1 -: last_A_WIDTH]),
.B(B), .B(B),
.Y(blk.last_partial) .Y(blk.last_partial)
); );
assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1]; assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
assign Y = blk.partial_sum[n]; assign Y = blk.partial_sum[n];
end end
else if (B_WIDTH > `DSP_B_MAXWIDTH) begin else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom); localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom); localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH; localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
if (A_SIGNED && B_SIGNED) begin : blk if (A_SIGNED && B_SIGNED) begin : blk
(* force_downto *) (* force_downto *)
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *) (* force_downto *)
wire signed [last_Y_WIDTH-1:0] last_partial; wire signed [last_Y_WIDTH-1:0] last_partial;
(* force_downto *) (* force_downto *)
wire signed [Y_WIDTH-1:0] partial_sum [n:0]; wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end end
else begin : blk else begin : blk
(* force_downto *) (* force_downto *)
wire [partial_Y_WIDTH-1:0] partial [n-1:0]; wire [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *) (* force_downto *)
wire [last_Y_WIDTH-1:0] last_partial; wire [last_Y_WIDTH-1:0] last_partial;
(* force_downto *) (* force_downto *)
wire [Y_WIDTH-1:0] partial_sum [n:0]; wire [Y_WIDTH-1:0] partial_sum [n:0];
end end
for (i = 0; i < n; i=i+1) begin:sliceB for (i = 0; i < n; i=i+1) begin:sliceB
\$__mul #( \$__mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(sign_headroom), .B_SIGNED(sign_headroom),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL), .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),
.Y_WIDTH(partial_Y_WIDTH) .Y_WIDTH(partial_Y_WIDTH)
) mul ( ) mul (
.A(A), .A(A),
.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}), .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
.Y(blk.partial[i]) .Y(blk.partial[i])
); );
// TODO: Currently a 'cascade' approach to summing the partial // TODO: Currently a 'cascade' approach to summing the partial
// products is taken here, but a more efficient 'binary // products is taken here, but a more efficient 'binary
// reduction' approach also exists... // reduction' approach also exists...
if (i == 0) if (i == 0)
assign blk.partial_sum[i] = blk.partial[i]; assign blk.partial_sum[i] = blk.partial[i];
else else
assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1]; assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
end end
\$__mul #( \$__mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(last_B_WIDTH), .B_WIDTH(last_B_WIDTH),
.Y_WIDTH(last_Y_WIDTH) .Y_WIDTH(last_Y_WIDTH)
) mul_sliceB_last ( ) mul_sliceB_last (
.A(A), .A(A),
.B(B[B_WIDTH-1 -: last_B_WIDTH]), .B(B[B_WIDTH-1 -: last_B_WIDTH]),
.Y(blk.last_partial) .Y(blk.last_partial)
); );
assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1]; assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
assign Y = blk.partial_sum[n]; assign Y = blk.partial_sum[n];
end end
else begin else begin
if (A_SIGNED) begin : blkA if (A_SIGNED) begin : blkA
wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
end end
else begin : blkA else begin : blkA
wire [`DSP_A_MAXWIDTH-1:0] Aext = A; wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
end end
if (B_SIGNED) begin : blkB if (B_SIGNED) begin : blkB
wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B); wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
end end
else begin : blkB else begin : blkB
wire [`DSP_B_MAXWIDTH-1:0] Bext = B; wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
end end
`DSP_NAME #( `DSP_NAME #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH), .A_WIDTH(`DSP_A_MAXWIDTH),
.B_WIDTH(`DSP_B_MAXWIDTH), .B_WIDTH(`DSP_B_MAXWIDTH),
.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)), .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A(blkA.Aext), .A(blkA.Aext),
.B(blkB.Bext), .B(blkB.Bext),
.Y(Y) .Y(Y)
); );
end end
end end
endgenerate endgenerate
endmodule endmodule
(* techmap_celltype = "$mul $__mul" *) (* techmap_celltype = "$mul $__mul" *)
module _90_soft_mul (A, B, Y); module _90_soft_mul (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;
parameter A_WIDTH = 1; parameter A_WIDTH = 1;
parameter B_WIDTH = 1; parameter B_WIDTH = 1;
parameter Y_WIDTH = 1; parameter Y_WIDTH = 1;
(* force_downto *) (* force_downto *)
input [A_WIDTH-1:0] A; input [A_WIDTH-1:0] A;
(* force_downto *) (* force_downto *)
input [B_WIDTH-1:0] B; input [B_WIDTH-1:0] B;
(* force_downto *) (* force_downto *)
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
// Indirection necessary since mapping // Indirection necessary since mapping
// back to $mul will cause recursion // back to $mul will cause recursion
generate generate
if (A_SIGNED && !B_SIGNED) if (A_SIGNED && !B_SIGNED)
\$__soft_mul #( \$__soft_mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(1), .B_SIGNED(1),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH+1), .B_WIDTH(B_WIDTH+1),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A(A), .A(A),
.B({1'b0,B}), .B({1'b0,B}),
.Y(Y) .Y(Y)
); );
else if (!A_SIGNED && B_SIGNED) else if (!A_SIGNED && B_SIGNED)
\$__soft_mul #( \$__soft_mul #(
.A_SIGNED(1), .A_SIGNED(1),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH+1), .A_WIDTH(A_WIDTH+1),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A({1'b0,A}), .A({1'b0,A}),
.B(B), .B(B),
.Y(Y) .Y(Y)
); );
else else
\$__soft_mul #( \$__soft_mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A(A), .A(A),
.B(B), .B(B),
.Y(Y) .Y(Y)
); );
endgenerate endgenerate
endmodule endmodule

62
techlibs/intel_alm/common/bram_m20k_map.v
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@ -1,31 +1,31 @@
module __MISTRAL_M20K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); module __MISTRAL_M20K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10; parameter CFG_ABITS = 10;
parameter CFG_DBITS = 20; parameter CFG_DBITS = 20;
parameter CFG_ENABLE_A = 1; parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1; parameter CFG_ENABLE_B = 1;
input CLK1; input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR; input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA; input [CFG_DBITS-1:0] A1DATA;
output [CFG_DBITS-1:0] B1DATA; output [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_A-1:0] A1EN, B1EN; input [CFG_ENABLE_A-1:0] A1EN, B1EN;
altsyncram #( altsyncram #(
.operation_mode("dual_port"), .operation_mode("dual_port"),
.ram_block_type("m20k"), .ram_block_type("m20k"),
.widthad_a(CFG_ABITS), .widthad_a(CFG_ABITS),
.width_a(CFG_DBITS), .width_a(CFG_DBITS),
.widthad_b(CFG_ABITS), .widthad_b(CFG_ABITS),
.width_b(CFG_DBITS), .width_b(CFG_DBITS),
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.address_a(A1ADDR), .address_a(A1ADDR),
.data_a(A1DATA), .data_a(A1DATA),
.wren_a(A1EN), .wren_a(A1EN),
.address_b(B1ADDR), .address_b(B1ADDR),
.q_b(B1DATA), .q_b(B1DATA),
.clock0(CLK1), .clock0(CLK1),
.clock1(CLK1) .clock1(CLK1)
); );
endmodule endmodule

22
tests/arch/common/counter.v
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@ -1,11 +1,11 @@
module top ( out, clk, reset ); module top ( out, clk, reset );
output [7:0] out; output [7:0] out;
input clk, reset; input clk, reset;
reg [7:0] out; reg [7:0] out;
always @(posedge clk, posedge reset) always @(posedge clk, posedge reset)
if (reset) if (reset)
out <= 8'b0; out <= 8'b0;
else else
out <= out + 1; out <= out + 1;
endmodule endmodule

102
tests/arch/common/fsm.v
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@ -1,51 +1,51 @@
module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 ); module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
input clock,reset,req_0,req_1; input clock,reset,req_0,req_1;
output gnt_0,gnt_1; output gnt_0,gnt_1;
wire clock,reset,req_0,req_1; wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1; reg gnt_0,gnt_1;
parameter SIZE = 3; parameter SIZE = 3;
parameter IDLE = 3'b001; parameter IDLE = 3'b001;
parameter GNT0 = 3'b010; parameter GNT0 = 3'b010;
parameter GNT1 = 3'b100; parameter GNT1 = 3'b100;
parameter GNT2 = 3'b101; parameter GNT2 = 3'b101;
reg [SIZE-1:0] state; reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state; reg [SIZE-1:0] next_state;
always @ (posedge clock) always @ (posedge clock)
begin : FSM begin : FSM
if (reset == 1'b1) begin if (reset == 1'b1) begin
state <= #1 IDLE; state <= #1 IDLE;
gnt_0 <= 0; gnt_0 <= 0;
gnt_1 <= 0; gnt_1 <= 0;
end end
else else
case(state) case(state)
IDLE : if (req_0 == 1'b1) begin IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0; state <= #1 GNT0;
gnt_0 <= 1; gnt_0 <= 1;
end else if (req_1 == 1'b1) begin end else if (req_1 == 1'b1) begin
gnt_1 <= 1; gnt_1 <= 1;
state <= #1 GNT0; state <= #1 GNT0;
end else begin end else begin
state <= #1 IDLE; state <= #1 IDLE;
end end
GNT0 : if (req_0 == 1'b1) begin GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0; state <= #1 GNT0;
end else begin end else begin
gnt_0 <= 0; gnt_0 <= 0;
state <= #1 IDLE; state <= #1 IDLE;
end end
GNT1 : if (req_1 == 1'b1) begin GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2; state <= #1 GNT2;
gnt_1 <= req_0; gnt_1 <= req_0;
end end
GNT2 : if (req_0 == 1'b1) begin GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1; state <= #1 GNT1;
gnt_1 <= req_1; gnt_1 <= req_1;
end end
default : state <= #1 IDLE; default : state <= #1 IDLE;
endcase endcase
end end
endmodule endmodule

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tests/arch/common/shifter.v
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module top(out, clk, in); module top(out, clk, in);
output [7:0] out; output [7:0] out;
input signed clk, in; input signed clk, in;
reg signed [7:0] out = 0; reg signed [7:0] out = 0;
always @(posedge clk) always @(posedge clk)
begin begin
out <= out >> 1; out <= out >> 1;
out[7] <= in; out[7] <= in;
end end
endmodule endmodule