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Merge pull request #4879 from YosysHQ/krys/ub_fixes 

Fixing undefined behaviours
This commit is contained in:
Martin Povišer 2025-02-03 09:56:48 +01:00 committed by GitHub
parent 18a7c00382 cf52cf3009
commit 92afe26d6b
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2 changed files with 7 additions and 4 deletions
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5
frontends/ast/simplify.cc
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@ -2936,7 +2936,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
lsb_expr->children[stride_ix]->detectSignWidth(stride_width, stride_sign);
max_width = std::max(i_width, stride_width);
// Stride width calculated from actual stride value.
stride_width = std::ceil(std::log2(std::abs(stride)));
if (stride == 0)
stride_width = 0;
else
stride_width = std::ceil(std::log2(std::abs(stride)));
if (i_width + stride_width > max_width) {
// For (truncated) i*stride to be within the range of dst, the following must hold:

6
kernel/celledges.cc
View File

@ -253,13 +253,13 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
if (a_width == 1 && is_signed) {
int skip = 1 << (k + 1);
int base = skip -1;
if (i % skip != base && i - a_width + 2 < 1 << b_width)
if (i % skip != base && i - a_width + 2 < 1 << b_width_capped)
db->add_edge(cell, ID::B, k, ID::Y, i, -1);
} else if (is_signed) {
if (i - a_width + 2 < 1 << b_width)
if (i - a_width + 2 < 1 << b_width_capped)
db->add_edge(cell, ID::B, k, ID::Y, i, -1);
} else {
if (i - a_width + 1 < 1 << b_width)
if (i - a_width + 1 < 1 << b_width_capped)
db->add_edge(cell, ID::B, k, ID::Y, i, -1);
}
// right shifts