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abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling

This commit is contained in:
Eddie Hung 2020-03-06 10:20:30 -08:00
parent 2335c59e5b
commit 91a7a74ac4
2 changed files with 9 additions and 11 deletions
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7
backends/aiger/xaiger.cc
View File

@ -174,11 +174,12 @@ struct XAigerWriter
undriven_bits.insert(bit); undriven_bits.insert(bit);
unused_bits.insert(bit); unused_bits.insert(bit);
bool keep = wire->get_bool_attribute(ID::keep); bool scc = wire->attributes.count(ID(abc9_scc));
if (wire->port_input || keep) if (wire->port_input || scc)
input_bits.insert(bit); input_bits.insert(bit);
if (wire->port_output || keep) { bool keep = wire->get_bool_attribute(ID::keep);
if (wire->port_output || keep || scc) {
if (bit != wirebit) if (bit != wirebit)
alias_map[wirebit] = bit; alias_map[wirebit] = bit;
output_bits.insert(wirebit); output_bits.insert(wirebit);

13
passes/techmap/abc9_ops.cc
View File

@ -110,14 +110,13 @@ void mark_scc(RTLIL::Module *module)
if (c.second.is_fully_const()) continue; if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) { if (cell->output(c.first)) {
SigBit b = c.second.as_bit(); SigBit b = c.second.as_bit();
// TODO: Don't be as heavy handed as to
// mark the entire wire as part of the scc
Wire *w = b.wire; Wire *w = b.wire;
w->set_bool_attribute(ID::keep); w->set_bool_attribute(ID(abc9_scc));
w->attributes[ID(abc9_scc_id)] = id.as_int();
} }
} }
} }
module->fixup_ports();
} }
void prep_dff(RTLIL::Module *module) void prep_dff(RTLIL::Module *module)
@ -967,10 +966,8 @@ void reintegrate(RTLIL::Module *module)
RTLIL::Wire *mapped_wire = mapped_mod->wire(port); RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port); RTLIL::Wire *wire = module->wire(port);
log_assert(wire); log_assert(wire);
if (wire->attributes.erase(ID(abc9_scc_id))) { wire->attributes.erase(ID(abc9_scc));
auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
log_assert(r);
}
RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire)); RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire));