mirror of https://github.com/YosysHQ/yosys.git
Ensure smt2 comments are associated with accessors
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87b9ee330d
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@ -824,38 +824,49 @@ struct Smt2Worker
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is_register = true;
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if (wire->port_id || is_register || wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) {
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RTLIL::SigSpec sig = sigmap(wire);
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std::vector<std::string> comments;
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if (wire->port_input)
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decls.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width));
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comments.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width));
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if (wire->port_output)
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decls.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width));
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comments.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width));
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if (is_register)
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decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width));
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comments.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width));
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if (wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\'))
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decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width));
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comments.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width));
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if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig)))
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decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire),
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comments.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire),
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clock_posedge.count(sig) ? " posedge" : "", clock_negedge.count(sig) ? " negedge" : ""));
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if (bvmode && GetSize(sig) > 1) {
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std::string sig_bv = get_bv(sig);
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if (!comments.empty())
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decls.insert(decls.end(), comments.begin(), comments.end());
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decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
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get_id(module), get_id(wire), get_id(module), GetSize(sig), get_bv(sig).c_str()));
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get_id(module), get_id(wire), get_id(module), GetSize(sig), sig_bv.c_str()));
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if (wire->port_input)
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ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
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get_id(module), get_id(wire), get_id(module), get_id(wire)));
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} else {
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for (int i = 0; i < GetSize(sig); i++)
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std::vector<std::string> sig_bool;
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for (int i = 0; i < GetSize(sig); i++) {
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sig_bool.push_back(get_bool(sig[i]));
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}
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if (!comments.empty())
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decls.insert(decls.end(), comments.begin(), comments.end());
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for (int i = 0; i < GetSize(sig); i++) {
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if (GetSize(sig) > 1) {
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decls.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n",
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get_id(module), get_id(wire), i, get_id(module), get_bool(sig[i]).c_str()));
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get_id(module), get_id(wire), i, get_id(module), sig_bool[i].c_str()));
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if (wire->port_input)
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ex_input_eq.push_back(stringf(" (= (|%s_n %s %d| state) (|%s_n %s %d| other_state))",
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get_id(module), get_id(wire), i, get_id(module), get_id(wire), i));
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} else {
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decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n",
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get_id(module), get_id(wire), get_id(module), get_bool(sig[i]).c_str()));
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get_id(module), get_id(wire), get_id(module), sig_bool[i].c_str()));
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if (wire->port_input)
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ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
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get_id(module), get_id(wire), get_id(module), get_id(wire)));
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}
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}
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}
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}
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}
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