mirror of https://github.com/YosysHQ/yosys.git
Add assert/assume support to verific front-end
This commit is contained in:
Clifford Wolf
parent
249ddbc16c
commit
911c44d164
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@ -6,7 +6,7 @@ only have the i386 eval version of Verific:
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1.) Use a Makefile.conf like the following one:
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--snip--
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CONFIG := clang
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CONFIG := gcc
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ENABLE_TCL := 0
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ENABLE_PLUGINS := 0
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ENABLE_VERIFIC := 1
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@ -49,7 +49,13 @@ USING_YOSYS_NAMESPACE
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using namespace Verific ;
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#endif
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static void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
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#endif
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PRIVATE_NAMESPACE_BEGIN
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#ifdef YOSYS_ENABLE_VERIFIC
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void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
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{
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log("VERIFIC-%s [%s] ",
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msg_type == VERIFIC_NONE ? "NONE" :
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@ -65,7 +71,13 @@ static void msg_func(msg_type_t msg_type, const char *message_id, linefile_type
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log("\n");
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}
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static void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
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struct VerificImporter
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{
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RTLIL::Module *module;
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std::map<Net*, RTLIL::SigBit> net_map;
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std::map<Net*, Net*> sva_posedge_map;
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void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
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{
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MapIter mi;
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Att *attr;
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@ -78,7 +90,7 @@ static void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, D
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attributes[RTLIL::escape_id(attr->Key())] = RTLIL::Const(std::string(attr->Value()));
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}
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static RTLIL::SigSpec operatorInput(Instance *inst, std::map<Net*, RTLIL::SigBit> &net_map)
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RTLIL::SigSpec operatorInput(Instance *inst)
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{
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RTLIL::SigSpec sig;
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for (int i = int(inst->InputSize())-1; i >= 0; i--)
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@ -89,7 +101,7 @@ static RTLIL::SigSpec operatorInput(Instance *inst, std::map<Net*, RTLIL::SigBit
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return sig;
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}
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static RTLIL::SigSpec operatorInput1(Instance *inst, std::map<Net*, RTLIL::SigBit> &net_map)
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RTLIL::SigSpec operatorInput1(Instance *inst)
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{
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RTLIL::SigSpec sig;
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for (int i = int(inst->Input1Size())-1; i >= 0; i--)
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@ -100,7 +112,7 @@ static RTLIL::SigSpec operatorInput1(Instance *inst, std::map<Net*, RTLIL::SigBi
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return sig;
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}
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static RTLIL::SigSpec operatorInput2(Instance *inst, std::map<Net*, RTLIL::SigBit> &net_map)
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RTLIL::SigSpec operatorInput2(Instance *inst)
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{
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RTLIL::SigSpec sig;
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for (int i = int(inst->Input2Size())-1; i >= 0; i--)
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@ -111,7 +123,7 @@ static RTLIL::SigSpec operatorInput2(Instance *inst, std::map<Net*, RTLIL::SigBi
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return sig;
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}
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static RTLIL::SigSpec operatorInport(Instance *inst, const char *portname, std::map<Net*, RTLIL::SigBit> &net_map)
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RTLIL::SigSpec operatorInport(Instance *inst, const char *portname)
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{
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PortBus *portbus = inst->View()->GetPortBus(portname);
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if (portbus) {
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@ -137,7 +149,7 @@ static RTLIL::SigSpec operatorInport(Instance *inst, const char *portname, std::
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}
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}
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static RTLIL::SigSpec operatorOutput(Instance *inst, std::map<Net*, RTLIL::SigBit> &net_map, RTLIL::Module *module)
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RTLIL::SigSpec operatorOutput(Instance *inst)
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{
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RTLIL::SigSpec sig;
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RTLIL::Wire *dummy_wire = NULL;
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@ -155,7 +167,7 @@ static RTLIL::SigSpec operatorOutput(Instance *inst, std::map<Net*, RTLIL::SigBi
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return sig;
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}
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static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, RTLIL::SigBit> &net_map, Instance *inst)
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bool import_netlist_instance_gates(Instance *inst)
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{
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if (inst->Type() == PRIM_AND) {
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module->addAndGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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@ -246,7 +258,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*,
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return false;
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}
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static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*, RTLIL::SigBit> &net_map, Instance *inst)
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bool import_netlist_instance_cells(Instance *inst)
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{
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if (inst->Type() == PRIM_AND) {
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module->addAnd(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput()));
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@ -334,10 +346,10 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
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return true;
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}
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#define IN operatorInput(inst, net_map)
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#define IN1 operatorInput1(inst, net_map)
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#define IN2 operatorInput2(inst, net_map)
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#define OUT operatorOutput(inst, net_map, module)
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#define IN operatorInput(inst)
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#define IN1 operatorInput1(inst)
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#define IN2 operatorInput2(inst)
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#define OUT operatorOutput(inst)
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#define SIGNED inst->View()->IsSigned()
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if (inst->Type() == OPER_ADDER) {
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@ -503,8 +515,8 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
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}
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if (inst->Type() == OPER_WIDE_DFFRS) {
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RTLIL::SigSpec sig_set = operatorInport(inst, "set", net_map);
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RTLIL::SigSpec sig_reset = operatorInport(inst, "reset", net_map);
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RTLIL::SigSpec sig_set = operatorInport(inst, "set");
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RTLIL::SigSpec sig_reset = operatorInport(inst, "reset");
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if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool())
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module->addDff(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), IN, OUT);
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else
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@ -521,7 +533,7 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
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return false;
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}
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static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo, bool mode_gates)
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void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo, bool mode_gates)
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{
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std::string module_name = nl->IsOperator() ? std::string("$verific$") + nl->Owner()->Name() : RTLIL::escape_id(nl->Owner()->Name());
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@ -531,14 +543,12 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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return;
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}
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RTLIL::Module *module = new RTLIL::Module;
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module = new RTLIL::Module;
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module->name = module_name;
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design->add(module);
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log("Importing module %s.\n", RTLIL::id2cstr(module->name));
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std::map<Net*, RTLIL::SigBit> net_map;
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SetIter si;
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MapIter mi, mi2;
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Port *port;
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@ -694,8 +704,59 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
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{
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if (inst->Type() == PRIM_SVA_POSEDGE) {
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Net *in_net = inst->GetInput();
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Net *out_net = inst->GetOutput();
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sva_posedge_map[out_net] = in_net;
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continue;
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}
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}
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FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
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{
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if (inst->Type() == PRIM_SVA_POSEDGE)
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continue;
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// log(" importing cell %s (%s).\n", inst->Name(), inst->View()->Owner()->Name());
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if (inst->Type() == PRIM_SVA_AT)
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{
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Net *in1 = inst->GetInput1();
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Net *in2 = inst->GetInput2();
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Net *out = inst->GetOutput();
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if (sva_posedge_map.count(in2))
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std::swap(in1, in2);
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log_assert(sva_posedge_map.count(in1));
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Net *clk = sva_posedge_map.at(in1);
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SigBit outsig = net_map.at(out);
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log_assert(outsig.wire && GetSize(outsig.wire) == 1);
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outsig.wire->attributes["\\init"] == Const(0, 1);
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module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
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continue;
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}
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if (inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT || inst->Type() == PRIM_SVA_ASSERT) {
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Net *in = inst->GetInput();
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module->addAssert(NEW_ID, net_map.at(in), State::S1);
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continue;
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}
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if (inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME || inst->Type() == PRIM_SVA_ASSUME) {
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Net *in = inst->GetInput();
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module->addAssume(NEW_ID, net_map.at(in), State::S1);
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continue;
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}
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if (inst->Type() == PRIM_SVA_IMMEDIATE_COVER || inst->Type() == PRIM_SVA_COVER) {
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// Net *in = inst->GetInput();
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// module->addCover(NEW_ID, net_map.at(in), State::S1);
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continue;
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}
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if (inst->Type() == PRIM_PWR) {
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module->connect(net_map.at(inst->GetOutput()), RTLIL::State::S1);
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continue;
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@ -727,8 +788,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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if (memory->width != int(inst->OutputSize()))
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log_error("Import of asymetric memories from Verific is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
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RTLIL::SigSpec addr = operatorInput1(inst, net_map);
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RTLIL::SigSpec data = operatorOutput(inst, net_map, module);
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RTLIL::SigSpec addr = operatorInput1(inst);
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RTLIL::SigSpec data = operatorOutput(inst);
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RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memrd");
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cell->parameters["\\MEMID"] = memory->name.str();
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@ -750,8 +811,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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if (memory->width != int(inst->Input2Size()))
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log_error("Import of asymetric memories from Verific is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
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RTLIL::SigSpec addr = operatorInput1(inst, net_map);
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RTLIL::SigSpec data = operatorInput2(inst, net_map);
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RTLIL::SigSpec addr = operatorInput1(inst);
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RTLIL::SigSpec data = operatorInput2(inst);
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RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memwr");
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cell->parameters["\\MEMID"] = memory->name.str();
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@ -773,12 +834,12 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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}
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if (!mode_gates) {
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if (import_netlist_instance_cells(module, net_map, inst))
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if (import_netlist_instance_cells(inst))
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continue;
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if (inst->IsOperator())
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log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name());
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} else {
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if (import_netlist_instance_gates(module, net_map, inst))
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if (import_netlist_instance_gates(inst))
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continue;
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}
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@ -817,11 +878,10 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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}
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}
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}
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};
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#endif /* YOSYS_ENABLE_VERIFIC */
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YOSYS_NAMESPACE_BEGIN
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struct VerificPass : public Pass {
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VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
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virtual void help()
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@ -982,8 +1042,10 @@ struct VerificPass : public Pass {
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while (!nl_todo.empty()) {
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Netlist *nl = *nl_todo.begin();
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if (nl_done.count(nl) == 0)
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import_netlist(design, nl, nl_todo, mode_gates);
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if (nl_done.count(nl) == 0) {
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VerificImporter importer;
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importer.import_netlist(design, nl, nl_todo, mode_gates);
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}
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nl_todo.erase(nl);
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nl_done.insert(nl);
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}
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@ -1001,5 +1063,5 @@ struct VerificPass : public Pass {
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#endif
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} VerificPass;
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YOSYS_NAMESPACE_END
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PRIVATE_NAMESPACE_END
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