mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
anlogic: Use dfflegalize.
This commit is contained in:
Miodrag Milanović
GitHub
commit
910f421324
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@ -1,31 +1,17 @@
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module \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
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module \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(1'b0)); endmodule
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module \$_DFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_DFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_DFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_DFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
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module \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
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module \$_SDFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_SDFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_SDFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_SDFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
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module \$_DLATCH_N_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = !E ? D : Q;
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endmodule
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module \$_DLATCH_P_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = E ? D : Q;
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endmodule
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module \$_DLATCH_NN0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E) ,.ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_DLATCH_NN1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_DLATCH_NP0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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module \$_DLATCH_NP1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
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`ifndef NO_LUT
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module \$lut (A, Y);
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@ -10,9 +10,6 @@ module AL_MAP_SEQ (
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parameter SRMUX = "SR"; //SR/INV
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parameter SRMODE = "SYNC"; //SYNC/ASYNC
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wire clk_ce;
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assign clk_ce = ce ? clk : 1'b0;
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wire srmux;
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generate
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case (SRMUX)
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@ -38,18 +35,18 @@ module AL_MAP_SEQ (
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begin
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if (SRMODE == "ASYNC")
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begin
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always @(posedge clk_ce, posedge srmux)
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always @(posedge clk, posedge srmux)
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if (srmux)
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q <= regset;
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else
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else if (ce)
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q <= d;
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end
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else
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begin
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always @(posedge clk_ce)
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always @(posedge clk)
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if (srmux)
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q <= regset;
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else
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else if (ce)
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q <= d;
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end
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end
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@ -58,21 +55,23 @@ module AL_MAP_SEQ (
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// DFFMODE == "LATCH"
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if (SRMODE == "ASYNC")
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begin
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always @(clk_ce, srmux)
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always @*
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if (srmux)
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q <= regset;
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else
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else if (~clk & ce)
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q <= d;
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end
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else
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begin
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always @(clk_ce)
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always @*
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if (~clk) begin
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if (srmux)
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q <= regset;
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else
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else if (ce)
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q <= d;
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end
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end
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end
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endgenerate
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endmodule
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@ -182,8 +182,8 @@ struct SynthAnlogicPass : public ScriptPass
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if (check_label("map_ffs"))
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{
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run("dfflegalize -cell $_DFFE_P??P_ r -cell $_SDFFE_P??P_ r -cell $_DLATCH_N??_ r");
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run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
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run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
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run("opt_expr -mux_undef");
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run("simplemap");
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}
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@ -3,31 +3,33 @@ design -save read
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hierarchy -top latchp
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_anlogic
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equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
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design -load postopt
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT3
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select -assert-none t:AL_MAP_LUT3 %% t:* %D
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-count 1 t:AL_MAP_LUT1
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select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT1 %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_anlogic
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equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
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design -load postopt
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT3
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select -assert-none t:AL_MAP_LUT3 %% t:* %D
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_SEQ %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_anlogic
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equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
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design -load postopt
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT5
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select -assert-none t:AL_MAP_LUT5 %% t:* %D
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-count 2 t:AL_MAP_LUT3
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select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT3 %% t:* %D
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