riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed xilinx FDSE sim model

This commit is contained in:
Clifford Wolf 2015-01-24 11:03:22 +01:00
parent 75bbeb828a
commit 909a95182b
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/xilinx/cells_sim.v
View File

@ -119,8 +119,8 @@ module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] IS_S_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
generate case (|IS_C_INVERTED) generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate endcase endgenerate
endmodule endmodule