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coolrunner2: Also construct the XOR cell in the macrocell

This commit is contained in:
Robert Ou 2017-06-25 02:20:42 -07:00
parent a64b56648d
commit 908ce3fdce
2 changed files with 34 additions and 7 deletions
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14
techlibs/coolrunner2/cells_sim.v
View File

@ -41,3 +41,17 @@ module ORTERM(IN, OUT);
end end
end end
endmodule endmodule
module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
parameter INVERT_PTC = 0;
parameter INVERT_OUT = 0;
input IN_PTC;
input IN_ORTERM;
output wire OUT;
wire xor_intermed;
assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
assign xor_intermed = INVERT_PTC ? IN_ORTERM ^ ~IN_PTC : IN_ORTERM ^ IN_PTC;
endmodule

27
techlibs/coolrunner2/coolrunner2_sop.cpp
View File

@ -83,21 +83,34 @@ struct Coolrunner2SopPass : public Pass {
and_cell->setPort("\\IN_B", and_in_comp); and_cell->setPort("\\IN_B", and_in_comp);
} }
// If there is only one term, don't construct an OR cell // TODO: Find the $_NOT_ on the output
if (sop_depth == 1) if (sop_depth == 1)
{ {
yosys_xtrace = 1; // If there is only one term, don't construct an OR cell. Directly construct the XOR gate
module->connect(sop_output, *intermed_wires.begin()); auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
log("one\n"); xor_cell->setParam("\\INVERT_PTC", 0);
xor_cell->setParam("\\INVERT_OUT", 0);
xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
xor_cell->setPort("\\OUT", sop_output);
} }
else else
{ {
log("more\n"); // Wire from OR to XOR
// Construct the cell auto or_to_xor_wire = module->addWire(NEW_ID);
// Construct the OR cell
auto or_cell = module->addCell(NEW_ID, "\\ORTERM"); auto or_cell = module->addCell(NEW_ID, "\\ORTERM");
or_cell->setParam("\\WIDTH", sop_depth); or_cell->setParam("\\WIDTH", sop_depth);
or_cell->setPort("\\IN", intermed_wires); or_cell->setPort("\\IN", intermed_wires);
or_cell->setPort("\\OUT", sop_output); or_cell->setPort("\\OUT", or_to_xor_wire);
// Construct the XOR cell
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_PTC", 0);
xor_cell->setParam("\\INVERT_OUT", 0);
xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
xor_cell->setPort("\\OUT", sop_output);
} }
// Finally, remove the $sop cell // Finally, remove the $sop cell