Merge pull request #1850 from boqwxp/cleanup_backends

Cleanup pseudo-private member usage and outdated `RTLIL::id2cstr()` in backends

backends/blif/blif.cc

@@ -138,9 +138,9 @@ struct BlifDumper
 	{
 		if (!config->gates_mode)
 			return "subckt";
-		if (!design->modules_.count(RTLIL::escape_id(cell_type)))
+		if (design->module(RTLIL::escape_id(cell_type)) == nullptr)
 			return "gate";
-		if (design->modules_.at(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
+		if (design->module(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
 			return "gate";
 		return "subckt";
 	}
@@ -148,7 +148,7 @@ struct BlifDumper
 	void dump_params(const char *command, dict<IdString, Const> &params)
 	{
 		for (auto &param : params) {
-			f << stringf("%s %s ", command, RTLIL::id2cstr(param.first));
+			f << stringf("%s %s ", command, log_id(param.first));
 			if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
 				std::string str = param.second.decode_string();
 				f << stringf("\"");
@@ -172,8 +172,7 @@ struct BlifDumper
 
 		std::map<int, RTLIL::Wire*> inputs, outputs;
 
-		for (auto &wire_it : module->wires_) {
+		for (auto wire : module->wires()) {
-			RTLIL::Wire *wire = wire_it.second;
 			if (wire->port_input)
 				inputs[wire->port_id] = wire;
 			if (wire->port_output)
@@ -229,10 +228,8 @@ struct BlifDumper
 				f << stringf(".names $undef\n");
 		}
 
-		for (auto &cell_it : module->cells_)
+		for (auto cell : module->cells())
 		{
-			RTLIL::Cell *cell = cell_it.second;
-
 			if (config->unbuf_types.count(cell->type)) {
 				auto portnames = config->unbuf_types.at(cell->type);
 				f << stringf(".names %s %s\n1 1\n",
@@ -649,25 +646,24 @@ struct BlifBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		if (top_module_name.empty())
-			for (auto & mod_it:design->modules_)
+			for (auto module : design->modules())
-				if (mod_it.second->get_bool_attribute("\\top"))
+				if (module->get_bool_attribute("\\top"))
-					top_module_name = mod_it.first.str();
+					top_module_name = module->name.str();
 
 		*f << stringf("# Generated by %s\n", yosys_version_str);
 
 		std::vector<RTLIL::Module*> mod_list;
 
 		design->sort();
-		for (auto module_it : design->modules_)
+		for (auto module : design->modules())
 		{
-			RTLIL::Module *module = module_it.second;
 			if (module->get_blackbox_attribute() && !config.blackbox_mode)
 				continue;
 
 			if (module->processes.size() != 0)
-				log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
+				log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", log_id(module->name));
 			if (module->memories.size() != 0)
-				log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
+				log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", log_id(module->name));
 
 			if (module->name == RTLIL::escape_id(top_module_name)) {
 				BlifDumper::dump(*f, module, design, config);

backends/edif/edif.cc

@@ -171,13 +171,12 @@ struct EdifBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		if (top_module_name.empty())
-			for (auto & mod_it:design->modules_)
+			for (auto module : design->modules())
-				if (mod_it.second->get_bool_attribute("\\top"))
+				if (module->get_bool_attribute("\\top"))
-					top_module_name = mod_it.first.str();
+					top_module_name = module->name.str();
 
-		for (auto module_it : design->modules_)
+		for (auto module : design->modules())
 		{
-			RTLIL::Module *module = module_it.second;
 			if (module->get_blackbox_attribute())
 				continue;
 
@@ -185,14 +184,13 @@ struct EdifBackend : public Backend {
 				top_module_name = module->name.str();
 
 			if (module->processes.size() != 0)
-				log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
+				log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", log_id(module->name));
 			if (module->memories.size() != 0)
-				log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
+				log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", log_id(module->name));
 
-			for (auto cell_it : module->cells_)
+			for (auto cell : module->cells())
 			{
-				RTLIL::Cell *cell = cell_it.second;
+				if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
-				if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_blackbox_attribute()) {
 					lib_cell_ports[cell->type];
 					for (auto p : cell->connections())
 						lib_cell_ports[cell->type][p.first] = GetSize(p.second);
@@ -277,11 +275,11 @@ struct EdifBackend : public Backend {
 
 		// extract module dependencies
 		std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
-		for (auto &mod_it : design->modules_) {
+		for (auto module : design->modules()) {
-			module_deps[mod_it.second] = std::set<RTLIL::Module*>();
+			module_deps[module] = std::set<RTLIL::Module*>();
-			for (auto &cell_it : mod_it.second->cells_)
+			for (auto cell : module->cells())
-				if (design->modules_.count(cell_it.second->type) > 0)
+				if (design->module(cell->type) != nullptr)
-					module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
+					module_deps[module].insert(design->module(cell->type));
 		}
 
 		// simple good-enough topological sort
@@ -292,12 +290,12 @@ struct EdifBackend : public Backend {
 				for (auto &dep : it.second)
 					if (module_deps.count(dep) > 0)
 						goto not_ready_yet;
-				// log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
+				// log("Next in topological sort: %s\n", log_id(it.first->name));
 				sorted_modules.push_back(it.first);
 			not_ready_yet:;
 			}
 			if (sorted_modules_idx == sorted_modules.size())
-				log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
+				log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", log_id(module_deps.begin()->first->name));
 			while (sorted_modules_idx < sorted_modules.size())
 				module_deps.erase(sorted_modules.at(sorted_modules_idx++));
 		}
@@ -339,8 +337,7 @@ struct EdifBackend : public Backend {
 			*f << stringf("      (view VIEW_NETLIST\n");
 			*f << stringf("        (viewType NETLIST)\n");
 			*f << stringf("        (interface\n");
-			for (auto &wire_it : module->wires_) {
+			for (auto wire : module->wires()) {
-				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_id == 0)
 					continue;
 				const char *dir = "INOUT";
@@ -378,8 +375,7 @@ struct EdifBackend : public Backend {
 				*f << stringf("          (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
 				*f << stringf("          (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
 			}
-			for (auto &cell_it : module->cells_) {
+			for (auto cell : module->cells()) {
-				RTLIL::Cell *cell = cell_it.second;
 				*f << stringf("          (instance %s\n", EDIF_DEF(cell->name));
 				*f << stringf("            (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
 						lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
@@ -459,8 +455,7 @@ struct EdifBackend : public Backend {
 						add_prop(p.first, p.second);
 				*f << stringf("\n          )\n");
 			}
-			for (auto &wire_it : module->wires_) {
+			for (auto wire : module->wires()) {
-				RTLIL::Wire *wire = wire_it.second;
 				if (!wire->get_bool_attribute(ID::keep))
 					continue;
 				for(int i = 0; i < wire->width; i++) {

backends/ilang/ilang_backend.cc

@@ -358,10 +358,10 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
 
 	if (!flag_m) {
 		int count_selected_mods = 0;
-		for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
+		for (auto module : design->modules()) {
-			if (design->selected_whole_module(it->first))
+			if (design->selected_whole_module(module->name))
 				flag_m = true;
-			if (design->selected(it->second))
+			if (design->selected(module))
 				count_selected_mods++;
 		}
 		if (count_selected_mods > 1)
@@ -374,11 +374,11 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
 		f << stringf("autoidx %d\n", autoidx);
 	}
 
-	for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
+	for (auto module : design->modules()) {
-		if (!only_selected || design->selected(it->second)) {
+		if (!only_selected || design->selected(module)) {
 			if (only_selected)
 				f << stringf("\n");
-			dump_module(f, "", it->second, design, only_selected, flag_m, flag_n);
+			dump_module(f, "", module, design, only_selected, flag_m, flag_n);
 		}
 	}
 

backends/intersynth/intersynth.cc

@@ -122,70 +122,67 @@ struct IntersynthBackend : public Backend {
 		for (auto lib : libs)
 			ct.setup_design(lib);
 
-		for (auto module_it : design->modules_)
+		for (auto module : design->modules())
 		{
-			RTLIL::Module *module = module_it.second;
 			SigMap sigmap(module);
 
 			if (module->get_blackbox_attribute())
 				continue;
-			if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
+			if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells().size() == 0)
 				continue;
 
 			if (selected && !design->selected_whole_module(module->name)) {
 				if (design->selected_module(module->name))
-					log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module->name));
+					log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
 				continue;
 			}
 
-			log("Generating netlist %s.\n", RTLIL::id2cstr(module->name));
+			log("Generating netlist %s.\n", log_id(module->name));
 
 			if (module->memories.size() != 0 || module->processes.size() != 0)
 				log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
 
 			std::set<std::string> constcells_code;
-			netlists_code += stringf("# Netlist of module %s\n", RTLIL::id2cstr(module->name));
+			netlists_code += stringf("# Netlist of module %s\n", log_id(module->name));
-			netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
+			netlists_code += stringf("netlist %s\n", log_id(module->name));
 
 			// Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
-			for (auto wire_it : module->wires_) {
+			for (auto wire : module->wires()) {
-				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_input || wire->port_output) {
 					celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
-							RTLIL::id2cstr(wire->name), wire->width, wire->port_input ? "*" : "",
+							log_id(wire->name), wire->width, wire->port_input ? "*" : "",
-							wire->port_input ? "input" : "output", RTLIL::id2cstr(wire->name), wire->width, RTLIL::id2cstr(wire->name)));
+							wire->port_input ? "input" : "output", log_id(wire->name), wire->width, log_id(wire->name)));
-					netlists_code += stringf("node %s %s PORT %s\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(wire->name),
+					netlists_code += stringf("node %s %s PORT %s\n", log_id(wire->name), log_id(wire->name),
 							netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
 				}
 			}
 
 			// Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
-			for (auto cell_it : module->cells_)
+			for (auto cell : module->cells())
 			{
-				RTLIL::Cell *cell = cell_it.second;
 				std::string celltype_code, node_code;
 
 				if (!ct.cell_known(cell->type))
-					log_error("Found unknown cell type %s in module!\n", RTLIL::id2cstr(cell->type));
+					log_error("Found unknown cell type %s in module!\n", log_id(cell->type));
 
-				celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type));
+				celltype_code = stringf("celltype %s", log_id(cell->type));
-				node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
+				node_code = stringf("node %s %s", log_id(cell->name), log_id(cell->type));
 				for (auto &port : cell->connections()) {
 					RTLIL::SigSpec sig = sigmap(port.second);
 					if (sig.size() != 0) {
 						conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
-						celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
+						celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", log_id(port.first));
-						node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
+						node_code += stringf(" %s %s", log_id(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
 					}
 				}
 				for (auto &param : cell->parameters) {
-					celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first));
+					celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first));
 					if (param.second.bits.size() != 32) {
-						node_code += stringf(" %s '", RTLIL::id2cstr(param.first));
+						node_code += stringf(" %s '", log_id(param.first));
 						for (int i = param.second.bits.size()-1; i >= 0; i--)
 							node_code += param.second.bits[i] == State::S1 ? "1" : "0";
 					} else
-						node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int());
+						node_code += stringf(" %s 0x%x", log_id(param.first), param.second.as_int());
 				}
 
 				celltypes_code.insert(celltype_code + "\n");

backends/smt2/smt2.cc

@@ -1523,12 +1523,12 @@ struct Smt2Backend : public Backend {
 				for (auto &dep : it.second)
 					if (module_deps.count(dep) > 0)
 						goto not_ready_yet;
-				// log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
+				// log("Next in topological sort: %s\n", log_id(it.first->name));
 				sorted_modules.push_back(it.first);
 			not_ready_yet:;
 			}
 			if (sorted_modules_idx == sorted_modules.size())
-				log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
+				log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", log_id(module_deps.begin()->first->name));
 			while (sorted_modules_idx < sorted_modules.size())
 				module_deps.erase(sorted_modules.at(sorted_modules_idx++));
 		}

backends/spice/spice.cc

@@ -70,14 +70,13 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 	idict<IdString, 1> inums;
 	int cell_counter = 0, conn_counter = 0, nc_counter = 0;
 
-	for (auto &cell_it : module->cells_)
+	for (auto cell : module->cells())
 	{
-		RTLIL::Cell *cell = cell_it.second;
 		f << stringf("X%d", cell_counter++);
 
 		std::vector<RTLIL::SigSpec> port_sigs;
 
-		if (design->modules_.count(cell->type) == 0)
+		if (design->module(cell->type) == nullptr)
 		{
 			log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
 					log_id(cell->type), log_id(module), log_id(cell));
@@ -88,11 +87,10 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 		}
 		else
 		{
-			RTLIL::Module *mod = design->modules_.at(cell->type);
+			RTLIL::Module *mod = design->module(cell->type);
 
 			std::vector<RTLIL::Wire*> ports;
-			for (auto wire_it : mod->wires_) {
+			for (auto wire : mod->wires()) {
-				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_id == 0)
 					continue;
 				while (int(ports.size()) < wire->port_id)
@@ -202,16 +200,15 @@ struct SpiceBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		if (top_module_name.empty())
-			for (auto & mod_it:design->modules_)
+			for (auto module : design->modules())
-				if (mod_it.second->get_bool_attribute("\\top"))
+				if (module->get_bool_attribute("\\top"))
-					top_module_name = mod_it.first.str();
+					top_module_name = module->name.str();
 
 		*f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
 		*f << stringf("\n");
 
-		for (auto module_it : design->modules_)
+		for (auto module : design->modules())
 		{
-			RTLIL::Module *module = module_it.second;
 			if (module->get_blackbox_attribute())
 				continue;
 
@@ -226,8 +223,7 @@ struct SpiceBackend : public Backend {
 			}
 
 			std::vector<RTLIL::Wire*> ports;
-			for (auto wire_it : module->wires_) {
+			for (auto wire : module->wires()) {
-				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_id == 0)
 					continue;
 				while (int(ports.size()) < wire->port_id)

backends/verilog/verilog_backend.cc

@@ -73,12 +73,12 @@ void reset_auto_counter(RTLIL::Module *module)
 
 	reset_auto_counter_id(module->name, false);
 
-	for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it)
+	for (auto w : module->wires())
-		reset_auto_counter_id(it->second->name, true);
+		reset_auto_counter_id(w->name, true);
 
-	for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) {
+	for (auto cell : module->cells()) {
-		reset_auto_counter_id(it->second->name, true);
+		reset_auto_counter_id(cell->name, true);
-		reset_auto_counter_id(it->second->type, false);
+		reset_auto_counter_id(cell->type, false);
 	}
 
 	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
@@ -1719,9 +1719,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 	if (!noexpr)
 	{
 		std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
-		for (auto &it : module->cells_)
+		for (auto cell : module->cells())
 		{
-			RTLIL::Cell *cell = it.second;
 			if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q"))
 				continue;
 
@@ -1734,9 +1733,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 						reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i));
 			}
 		}
-		for (auto &it : module->wires_)
+		for (auto wire : module->wires())
 		{
-			RTLIL::Wire *wire = it.second;
 			for (int i = 0; i < wire->width; i++)
 				if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
 					goto this_wire_aint_reg;
@@ -1751,8 +1749,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 	bool keep_running = true;
 	for (int port_id = 1; keep_running; port_id++) {
 		keep_running = false;
-		for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) {
+		for (auto wire : module->wires()) {
-			RTLIL::Wire *wire = it->second;
 			if (wire->port_id == port_id) {
 				if (port_id != 1)
 					f << stringf(", ");
@@ -1764,14 +1761,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 	}
 	f << stringf(");\n");
 
-	for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it)
+	for (auto w : module->wires())
-		dump_wire(f, indent + "  ", it->second);
+		dump_wire(f, indent + "  ", w);
 
 	for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
 		dump_memory(f, indent + "  ", it->second);
 
-	for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it)
+	for (auto cell : module->cells())
-		dump_cell(f, indent + "  ", it->second);
+		dump_cell(f, indent + "  ", cell);
 
 	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
 		dump_process(f, indent + "  ", it->second);
@@ -1995,16 +1992,16 @@ struct VerilogBackend : public Backend {
 		design->sort();
 
 		*f << stringf("/* Generated by %s */\n", yosys_version_str);
-		for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
+		for (auto module : design->modules()) {
-			if (it->second->get_blackbox_attribute() != blackboxes)
+			if (module->get_blackbox_attribute() != blackboxes)
 				continue;
-			if (selected && !design->selected_whole_module(it->first)) {
+			if (selected && !design->selected_whole_module(module->name)) {
-				if (design->selected_module(it->first))
+				if (design->selected_module(module->name))
-					log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first));
+					log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
 				continue;
 			}
-			log("Dumping module `%s'.\n", it->first.c_str());
+			log("Dumping module `%s'.\n", module->name.c_str());
-			dump_module(*f, "", it->second);
+			dump_module(*f, "", module);
 		}
 
 		auto_name_map.clear();