From 9018d06a33d2d66f57ad825053c31f85417339a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 19 Sep 2024 11:21:09 +0200 Subject: [PATCH] quicklogic: Avoid carry chains in division mapping The default mapping rules for division-like operations (div/divfloor/ mod/modfloor) invoke subtractions which can get mapped to carry chains in FPGA flows. Optimizations across carry chains are weak, so in practice this ends up too costly compared to implementing the division purely in soft logic. For this reason arrange for `techmap.v` ignoring division operations under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry chains for divisions. --- techlibs/common/techmap.v | 3 ++- techlibs/quicklogic/synth_quicklogic.cc | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 68b276588..119296147 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -304,6 +304,7 @@ endmodule // Divide and Modulo // -------------------------------------------------------- +`ifndef NODIV module \$__div_mod_u (A, B, Y, R); parameter WIDTH = 1; @@ -531,7 +532,7 @@ module _90_modfloor (A, B, Y); .R(Y) ); endmodule - +`endif // -------------------------------------------------------- // Power diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 0e7aaa752..76ef44570 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -266,7 +266,8 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("map_gates")) { if (inferAdder && family == "qlf_k6n10f") { - run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)"); + run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v -D NODIV", "(unless -no_adder)"); + run("techmap", "(unless -no_adder)"); } else { run("techmap"); }